TWI692039B - Manufacturing method of semiconductor device - Google Patents

Abstract

A manufacturing method of a semiconductor device includes the following steps. A substrate is provided. The substrate has a first side and a second side opposite to the first side. A first III-V compound layer is formed at the first side of the substrate. A drain trench and a contact trench are formed at the second side of the substrate. The drain trench extends from the first side of the substrate toward the second side of the substrate and penetrates the substrate. The contact trench extends from the first side of the substrate toward the second side of the substrate and penetrates the substrate. The drain trench and the contact trench are formed concurrently by the same process. A drain electrode is formed in the drain trench. A back side contact structure is formed in the contact trench.

Description

Manufacturing method of semiconductor device

The invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a semiconductor device having a drain trench and a contact trench.

Group III-V compounds can be used to form many types of integrated circuit devices due to their semiconductor characteristics, such as high-power field effect transistors, high-frequency transistors, or high electron mobility transistors (HEMT). In recent years, gallium nitride (GaN) series materials are suitable for high-power and high-frequency products due to their wide energy gap and high saturation rate. Gallium nitride series semiconductor devices generate two-dimensional electron gas (2DEG) due to the piezoelectric effect of the material itself. The electron speed and density are both high, so it can be used to increase the switching speed. However, as the performance requirements of related semiconductor devices are getting higher and higher, it is necessary to continuously improve the density of transistors or/and the electrical performance of semiconductor devices through design changes in structure or/and manufacturing processes to meet product requirements.

The invention provides a method for manufacturing a semiconductor device, which utilizes forming a drain trench and a contact trench on the back side of the substrate, forming a drain in the drain trench and forming a back contact structure in the contact trench, thereby To achieve the effect of improving the transistor density or/and simplifying the related lead layout design and manufacturing process. In addition, the drain trench and the contact trench can be formed together with the same process, thereby achieving the effect of simplifying the process.

According to an embodiment of the invention, the invention provides a method for manufacturing a semiconductor device, including the following steps. First, a substrate is provided. The substrate has a first side and a second side opposite to the first side. A first group III-V compound layer is formed on the first side of the substrate. A drain trench and a contact trench are formed from the second side of the substrate. The drain trench extends from the second side of the substrate toward the first side and penetrates the substrate, the contact trench extends from the second side of the substrate toward the first side and penetrates the substrate, and the drain trench and the contact trench are formed by the same process Formed together. A drain is formed in the drain trench. A back contact structure is formed in the contact trench.

The following detailed description of the invention has disclosed sufficient details to enable those skilled in the art to practice the invention. The embodiments set forth below should be considered illustrative rather than restrictive. It will be apparent to those of ordinary skill in the art that various changes and modifications in form and details can be made without departing from the spirit and scope of the present invention.

The use of the terms "on", "above" or/and "above" in this text should be interpreted in the broadest possible way, so that "on" not only means "directly on" On things but also on something with intervening features or layers in between, and "above" or "above" not only means "above" or "above" something, but It can also include the meaning that it is “above” or “above” something with no other intervening features or layers in between (ie, directly on something).

In addition, for ease of description, such as "below", "below", "below", "above", "above", "on", etc. may be used herein Spatially relative terms describe the relationship between one element or feature and another element or feature as shown in the drawings. In addition to the orientation shown in the drawings, spatial relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and can also interpret the spatially related descriptors used herein accordingly.

The term "forming" or "setting" is used herein to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

Reference herein to "one embodiment", "an embodiment", "some embodiments", etc. indicates that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include the specific Features, structures, or characteristics. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when specific features, structures, or characteristics are described in conjunction with the embodiments, whether or not explicitly described, combining other embodiments to implement such features, structures, or characteristics will be within the knowledge of those skilled in the relevant art.

Please refer to Figure 1 to Figure 5. FIGS. 1 to 5 are schematic diagrams of the manufacturing method of the semiconductor device according to the first embodiment of the present invention, wherein FIG. 2 illustrates the schematic diagram of the manufacturing method after FIG. 1, and FIG. 3 illustrates the second diagram. A schematic diagram of the manufacturing method after that, FIG. 4 shows a schematic diagram of the manufacturing method after FIG. 3, and FIG. 5 shows a schematic diagram of the manufacturing method after FIG. 4. As shown in FIG. 5, this embodiment provides a method for manufacturing a semiconductor device 101, including the following steps. First, a substrate 10 is provided. The substrate 10 has a first side 10A and a second side 10B, and the first side 10A and the second side 10B can be regarded as the substrate 10 in the thickness direction (such as shown in FIG. 5) The first direction D1) is opposite or/and opposite sides, but not limited to this. Then, a first III-V compound layer 16 is formed on the first side 10A of the substrate 10, and a drain trench TR1 and a contact trench TR2 are formed from the second side 10B of the substrate 10. The drain trench TR1 may extend from the second side 10B of the substrate 10 toward the first side 10A and penetrate the substrate 10, and the contact trench TR2 may also extend from the second side 10B of the substrate 10 toward the first side 10A and penetrate the substrate 10. And the drain trench TR1 and the contact trench TR2 can be formed together by the same process. Then, a drain DE is formed in the drain trench TR1, and a back contact structure CS2 is formed in the contact trench TR2.

To further explain, the manufacturing method of the semiconductor device 101 of this embodiment may include but is not limited to the following steps. First, as shown in FIG. 1, the first group III-V compound layer 16 may be formed before the first side 10A of the substrate 10. In some embodiments, the substrate 10 may include a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate or other suitable materials, and the first group III-V compound layer 16 may include gallium nitride ( gallium nitride (GaN), indium gallium nitride (InGaN) or/and other suitable group III-V compound semiconductor materials. In some embodiments, before the first III-V compound layer 16 is formed, a buffer layer 12 may be formed on the first side 10A of the substrate 10 and a second III-V compound layer may be formed on the buffer layer 12 14, but not limited to this. At least part of the buffer layer 12 may be located between the substrate 10 and the first III-V compound layer 16 in the first direction D1, and the second III-V compound layer 14 may be located in the first III in the first direction D1 -Between the group V compound layer 16 and the buffer layer 12. The buffer layer 12 may include a buffer material to help form a III-V group compound layer on the substrate 10 by epitaxial growth, so the material of the buffer layer 12 may include, for example, gallium nitride, aluminum gallium nitride, AlGaN) or other suitable buffer materials. The second group III-V compound layer 14 may include gallium nitride, indium gallium nitride, and/or other suitable group III-V compound semiconductor materials. In some embodiments, the first III-V compound layer 16 and the second III-V compound layer 14 may be the same III-V compound material but have different doping concentrations. For example, the first III-V compound layer 16 may include an N-type lightly doped gallium nitride layer, and the second III-V compound layer 14 may include an N-type heavily doped (heavily doped) gallium nitride layer, but not limited to this. The N-type dopant may include silicon, germanium, or other suitable dopants. In addition, in some embodiments, a nitride layer 20 may be formed on the first III-V compound layer 16. The nitride layer 20 can be used as a barrier layer or a cap layer in a semiconductor device. When used as a barrier layer, aluminum gallium nitride, aluminum indium nitride (AlInN) or/and nitrogen can be used Aluminum nitride (AlN) and other materials are used to form the nitride layer 20, and when used as a capping layer, materials such as aluminum gallium nitride, aluminum nitride, gallium nitride, and/or silicon nitride can be used to form the nitride layer 20 20, but not limited to this.

In some embodiments, the manufacturing method may further include forming a third group III-V compound layer 18 on the first side 10A of the substrate 10, and at least a portion of the first group III-V compound layer 16 may be in the first direction D1 The upper portion is located between the third III-V compound layer 18 and the second III-V compound layer 14. In some embodiments, the third group III-V compound layer 18 may be located in the first group III-V compound layer 16, and the third group III-V compound layer 18 may have an opening 18V. In this situation, the first portion P1 of the first III-V compound layer 16 may be located between the third III-V compound layer 18 and the second III-V compound layer 14, the first III-V compound layer The second portion P2 of 16 may be located in the opening 18V, and the third portion P3 of the first III-V compound layer 16 may be located between the nitride layer 20 and the third III-V compound layer 18, but not This is limited. In some embodiments, the third III-V compound layer 18 and the second III-V compound layer 14 may be the same III-V compound material but have different types of doping conditions. For example, the second III-V compound layer 14 may include an N-type heavily doped gallium nitride layer, and the third III-V compound layer 18 may include a P-type doped gallium nitride layer. The first portion P1 of a III-V compound layer 16 may include an N-type lightly doped gallium nitride layer, and the second portion P2 of the first III-V compound layer 16 may include an N-type doped gallium nitride layer The third portion P3 of the first III-V compound layer 16 may include an unintentionally doped (UID) gallium nitride layer, but it is not limited thereto. P-type dopants may include magnesium or other suitable dopants. In some embodiments, the third III-V compound layer 18 may also have a III-V compound material different from the second III-V compound layer 14. It is worth noting that the above-mentioned buffer layer 12, the second III-V group compound layer 14, the first III-V group compound layer 16, the third III-V group compound layer 18, and the nitride layer 20 can use an epitaxial process It is formed on the first side 10A of the substrate 10 with a suitable dopant, but the invention is not limited thereto. In some embodiments, the above-mentioned material layers may also be formed in other suitable film-forming methods as needed.

In some embodiments, a first region R1 and a second region R2 can be defined on the substrate 10. In some embodiments, the above-mentioned buffer layer 12, the second III-V compound layer 14, the first III-V compound layer 16, the third III-V compound layer 18 or/and the nitride layer 20 may be formed On the first region R1 and the second region R2 of the substrate 10. Then, part of the buffer layer 12, the second III-V compound layer 14, the first III-V compound layer 16, the third III-V compound layer 18, and/or the nitride layer 20 may be removed (e.g. (The nitride layer 20, the first III-V compound layer 16, the third III-V compound layer 18, the second III-V compound layer 14 and part of the buffer layer 12 on the second region R2 are removed) A mesa structure is formed on the first region R1, and the mesa structure may include a buffer layer 12, a second III-V compound layer 14, and a first III-V compound layer 16 on the first region R1 , The third III-V group compound layer 18 and the nitride layer 20, but not limited thereto. In some embodiments, a plurality of the above platform structures can be formed, and an isolation structure 24 can be formed between the plurality of platform structures after the platform structure is formed, so as to achieve the effect of isolating adjacent platform structures. The isolation structure 24 may include a single layer or multiple layers of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials. In some embodiments, the isolation structure 24 may be formed on the first side 10A of the substrate 10 and located on the second region R2 of the substrate 10, so the first region R1 may be regarded as a platform structure region and the second region R2 may be regarded as It is a non-platform structure area, but not limited to this.

Then, a gate electrode GE, a source electrode SE, and a contact structure CS1 can be formed on the first side 10A of the substrate 10. The gate electrode GE and the source electrode SE may be formed on the first region R1 of the substrate 10, and the contact structure CS1 may be formed on the second region R2 of the substrate 10. In addition, the gate GE may be formed on the nitride layer 20, and part of the nitride layer 20 and part of the first III-V compound layer 16 may be located between the gate GE and the substrate 10 in the first direction D1. In some embodiments, a gate dielectric layer 22 may be formed on the nitride layer 20 before the gate electrode GE and the source electrode SE are formed, and the gate electrode GE may be formed on the gate dielectric layer 22. In some embodiments, the source SE may penetrate the gate dielectric layer 22 and the nitride layer 20 in the first direction D1 and be partially located in the first III-V compound layer 16, and the source SE may be in the horizontal direction ( For example, the second direction D2) shown in FIG. 1 is located on both sides of the gate electrode GE and/or surrounds the gate electrode GE, and part of the first III-V compound layer 16 may be located in the source in the first direction D1 Between the pole SE and the substrate 10, but not limited to this. In addition, the contact structure CS1 may be formed on the second region R2 of the substrate 10 and at least partially formed in the isolation structure 24. The gate electrode GE, the source electrode SE, and the contact structure CS1 may include metal conductive materials or other suitable conductive materials, respectively. The above-mentioned metal conductive materials may include gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta ), palladium (Pd), platinum (Pt), compounds, composite layers or alloys of the above materials, but not limited thereto. In some embodiments, the source electrode SE and the contact structure CS1 may be formed together in the same process, or the gate electrode GE and the contact structure CS1 may be formed together in the same process, but not limited to this. In some embodiments, the gate electrode GE, the source electrode SE, and the contact structure CS1 can also be formed in different processes as needed.

As shown in FIGS. 1 to 2, in some embodiments, after the gate electrode GE, the source electrode SE, and the contact structure CS1 are formed, the substrate 10 may be turned so that the second side 10B of the substrate 10 faces upward, and The substrate 10 is joined to a carrier board 28. In some embodiments, a dielectric layer 26 may be formed to cover the gate electrode GE, the source electrode SE, and the contact structure CS1 before bonding the carrier board 28 to the dielectric layer 26. In some embodiments, the dielectric layer 26 itself may be a viscous dielectric material, or the dielectric layer 26 and the carrier board 28 may be joined by another adhesive layer (not shown). The carrier board 28 may include a glass carrier board, a plastic carrier board, a ceramic carrier board, a sapphire carrier board, a stainless steel carrier board or other suitable materials. Then, a thinning process 90 may be performed on the substrate 10 from the second side 10B of the substrate 10. The thinning process 90 may include, but is not limited to, a dry etching process, a wet etching process, a polishing process (such as a chemical mechanical polishing process), or Other suitable methods can be used to reduce the thickness of the substrate 10 to facilitate subsequent processes for forming trenches.

Thereafter, as shown in FIGS. 2 to 3, after the thinning process 90, the drain trench TR1 and the contact trench TR2 may be formed together by the same process, thereby achieving the effect of simplifying the process. In other words, the thinning process 90 can be performed on the substrate 10 from the second side 10B of the substrate 10 before forming the drain trench TR1 and the contact trench TR2. In some embodiments, the process of forming the drain trench TR1 and the contact trench TR2 may include, but is not limited to, forming a patterned mask (such as patterned photoresist or other suitable patterning) on the second side 10B of the substrate 10 Mask material, not shown), and then perform an etching process (such as a dry etching process or/and a wet etching process) to form the drain trench TR1 and the contact trench TR2 together. In some embodiments, the drain trench TR1 may extend from the second side 10B of the substrate 10 toward the first side 10A, penetrate the substrate 10 and the buffer layer 12 and be partially formed in the second III-V compound layer 14, and The contact trench TR2 may extend from the second side 10B of the substrate 10 toward the first side 10A, penetrate the substrate 10 and the buffer layer 12 and be partially formed in the isolation structure 24 and expose a portion of the contact structure CS1, but this is not the case limit. In other words, the isolation structure 24 may be formed before the contact trench TR2, but it is not limited thereto. In addition, when the stacking conditions corresponding to the drain trench TR1 and the contact trench TR2 are different, the drain trench TR1 and the contact trench TR2 formed together in the same process may have different depths, but this is not the case Limited.

Then, as shown in FIGS. 3 to 4, a drain DE can be formed in the drain trench TR1, and a back contact structure CS2 can be formed in the contact trench TR2. The back contact structure CS2 can contact the contact structure CS1 and An electrical connection is formed, and the back contact structure CS2 is electrically separated from the drain electrode DE. It is worth noting that before the drain electrode DE and the back contact structure CS2 are formed, a wet cleaning process, a plasma cleaning process or/and other suitable cleaning processes may be performed on the drain trench TR1 and the contact trench TR2 as needed. This removes etching by-products and/or particles that may be formed when forming the drain trench TR1 and the contact trench TR2. In addition, the drain electrode DE and the back contact structure CS2 may include metal conductive materials or other suitable conductive materials, and the metal conductive materials may include gold, tungsten, cobalt, nickel, titanium, molybdenum, copper, aluminum, tantalum, palladium, Platinum, compounds of the above materials, composite layers or alloys, but not limited to this. In some embodiments, the drain electrode DE and the back contact structure CS2 can be formed together in the same process, thereby achieving the effect of process simplification, and the material composition of the back contact structure CS2 can therefore be the same as the material composition of the drain electrode DE, but Not limited to this. For example, a first conductive layer 30 may be formed after the formation of the drain trench TR1 and the contact trench TR2, and the first conductive layer 30 may be partially formed in the drain trench TR1 and partially formed in the contact trench TR2 And the patterning process of the first conductive layer 30 can form the drain electrode DE and the back contact structure CS2 together. In some embodiments, different conductive materials and/or processes may be used to form the drain DE and the back contact structure CS2 respectively.

Then, after the drain electrode DE and the back contact structure CS2 are formed, the carrier board 28 can be removed to form the semiconductor device 101 shown in FIG. 5. As shown in FIGS. 1 to 5, in some embodiments, the gate electrode GE and the contact structure CS1 may be formed before the drain trench TR1 and the contact trench TR2, but the invention is not limited thereto. In addition, in some embodiments, the contact structure CS1 may be electrically connected to the source electrode SE or the gate electrode GE through other conductive structures (not shown) on the first side 10A of the substrate 10, or the source electrode SE or / And the gate electrode GE are directly connected to the contact structure CS1 and electrically connected to the back contact structure CS2 through the contact structure CS1, but not limited to this. In some embodiments, the semiconductor device may include a plurality of contact structures CS1 and corresponding back contact structures CS2, so that a wire bonding process may be performed on the second side 10B of the substrate 10 to respectively contact the drain DE and the source The electrode SE and the gate electrode GE form an electrical connection, thereby achieving the effect of simplifying the related lead layout design or/and manufacturing process. In addition, in some embodiments, the third group III-V compound layer 18 may be regarded as a current blocking layer (CBL), and the first portion P1 of the first group III-V compound layer 16 may be regarded as A drift region, a two-dimensional electron gas (2DEG) may be defined in the third portion P3 of the first III-V compound layer 16 and located on the side close to the nitride layer 20, and in the semiconductor device 101 The portion of the first region R1 may be regarded as a current-aperture vertical electron transistor (CAVET), but it is not limited thereto. It is worth noting that the structure of the semiconductor device of the present invention is not limited to the situation shown in FIG. 1, and the drain trench TR1 penetrating the substrate 10 is formed from the back side of the substrate 10 (eg, the second side 10B) of the present invention The manufacturing method of the contact trench TR2 may also be matched with other types of semiconductor structures or/and semiconductor processes having the first III-V compound layer 16 on the front side of the substrate 10 (eg, the first side 10A) as needed.

In the following, different embodiments of the present invention will be described, and to simplify the description, the following description will mainly describe the differences between the embodiments, without repeating the similarities. In addition, the same elements in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

Please refer to Figure 6 to Figure 9. 6 to 9 are schematic diagrams of the method for manufacturing the semiconductor device 102 according to the second embodiment of the invention. As shown in FIGS. 6 to 7, after the buffer layer 12, the second III-V compound layer 14, the first III-V compound layer 16, and the nitride layer 20 are formed, the substrate 10 may be turned over so that The second side 10B of the base 10 faces upward, and joins the base 10 with the carrier board 28. In some embodiments, a viscous dielectric layer 26 may be used to bond with the carrier board 28, but not limited to this. Then, the substrate 10 may be thinned 90 from the second side 10B of the substrate 10 to reduce the thickness of the substrate 10. Then, as shown in FIGS. 7 to 8, after the thinning process 90, the drain trench TR1 and the contact trench TR2 can be formed together by the same process, and in the drain trench TR1 and the contact trench TR2 The drain electrode DE and the back contact structure CS2 are formed respectively. In some embodiments, the contact trench TR2 may be partially disposed in the second III-V compound layer 14 through the substrate 10 and the buffer layer 12. In some embodiments, the nitride layer 20, the first group III-V compound layer 16, the second group III-V compound layer 14 on the second region R2 and some of the The buffer layer 12 is removed and an isolation structure 24 as shown in the above figure 2 is formed on the second region R2, but it is not limited to this. Then, as shown in FIGS. 8 to 9, after the drain electrode DE and the back contact structure CS2 are formed, the carrier board 28 and the dielectric layer 26 can be removed, and the gate electrode can be formed on the first side 10A of the substrate 10 The dielectric layer 22, the gate electrode GE, the source electrode SE, and the contact structure CS1. In some embodiments, after forming the drain electrode DE and the back contact structure CS2 and another carrier (not shown), the gate dielectric layer 22, the gate electrode GE, the source electrode SE and the Contact structure CS1, but not limited to this. In addition, the contact structure CS1 may penetrate the nitride layer 20, the first III-V group compound layer 16 and part of the second III-V group compound layer 14 in the first direction D1 to contact the back contact structure CS2 to form electrical properties connection. With the manufacturing method of this embodiment, the gate dielectric layer 22, the gate electrode GE, the source electrode SE and the contact structure can be formed after the drain trench TR1, the contact trench TR2, the drain DE and the back contact structure CS2 are formed CS1, thereby avoiding the related processes of forming the drain trench TR1, the contact trench TR2, the drain DE or/and the back contact structure CS2 to negatively affect the gate dielectric layer 22, thereby improving the electrical performance of the semiconductor device 102 which performed.

Please refer to Figure 10. FIG. 10 is a schematic diagram of a method for manufacturing a semiconductor device according to a third embodiment of the invention. As shown in FIG. 10, the difference from the first embodiment described above is that the contact structure CS1 of this embodiment can penetrate the nitride layer 20, the first III-V group compound layer 16 and part of the The second III-V compound layer 14 and the drain trench TR1 and the contact trench TR2 may be formed after the contact structure CS1, the gate GE, and the source SE are formed.

Please refer to Figure 11. FIG. 11 is a schematic diagram of a method for manufacturing a semiconductor device according to a fourth embodiment of the invention. As shown in FIG. 11, the difference from the first embodiment described above is that the manufacturing method of this embodiment may further include forming an insulation on the second side 10B of the substrate 10 after the drain electrode DE and the back contact structure CS2 are formed The layer 32 covers the drain electrode DE and the back contact structure CS2, thereby forming a protective effect. The insulating layer 32 may include a single layer or multiple layers of insulating materials, such as inorganic insulating materials (such as silicon oxide, silicon nitride, or silicon oxynitride), organic insulating materials (such as acrylic resin), or other suitable insulating materials. In some embodiments, the insulating layer 32 may be partially formed in the drain trench TR1 and the contact trench TR2. In some embodiments, the drain trench TR1 may be filled with the insulating layer 32 and the drain DE, and the contact trench TR2 may be filled with the insulating layer 32 and the back contact structure CS2, but not limited thereto. In addition, in some embodiments, a planarization process may be performed after the insulating layer 32 is formed to planarize the surface of the insulating layer 32. The above planarization process may include a dry etching process, a wet etching process, a polishing process (such as a chemical mechanical polishing process), or other suitable planarization methods. In addition, the insulating layer 32 of this embodiment can also be applied to other embodiments of this case as needed.

Please refer to Figure 12. FIG. 12 is a schematic diagram of a method for manufacturing a semiconductor device according to a fifth embodiment of the invention. As shown in FIG. 12, the difference from the first embodiment described above is that the drain electrode DE and the back contact structure CS2 of this embodiment may include a first conductive layer 30 and a second conductive layer 31. The first conductive layer 30 may be conformally formed in the drain trench TR1, the contact trench TR2, and the substrate 10, and the second conductive layer 31 may cover the first conductive layer 30, and the second conductive layer The material of 31 may be different from the material of the first conductive layer 30. For example, the first conductive layer 30 may include titanium nitride, tantalum nitride, or other suitable conductive materials with better barrier effect, and the second conductive layer 31 may include a conductive material with relatively low resistivity, such as copper, Aluminum, tungsten, etc., but not limited to this. In this embodiment, the first conductive layer 30 and the second conductive layer 31 may be patterned to form the drain electrode DE and the back contact structure CS2. In some embodiments, the drain trench TR1 may be filled with the drain DE, and the contact trench TR2 may be filled with the back contact structure CS2, but it is not limited thereto. In some embodiments, a planarization process may be performed after the second conductive layer 31 is formed to planarize the surface of the second conductive layer 31. The above planarization process may include a dry etching process, a wet etching process, a polishing process (such as a chemical mechanical polishing process), or other suitable planarization methods. In addition, an insulating layer 32 may be formed on the second conductive layer 31 as needed. The insulating layer 32 covers the drain electrode DE and the back contact structure CS2 to form a protective effect. The method of using the first conductive layer 30 and the second conductive layer 31 to form the drain electrode DE and the back contact structure CS2 in this embodiment can also be applied to other embodiments of this case as needed. In addition, in some embodiments, the drain electrode DE and the back contact structure CS2 may be formed with different conductive materials as needed, and the drain trench TR1 may be filled with the drain electrode DE, and the contact trench TR2 may be contacted by the back Structure CS2 is filled.

In summary, in the semiconductor device of the present invention, a drain trench and a contact trench can be formed on the back side of the substrate, a drain can be formed in the drain trench and a back contact structure can be formed in the contact trench, In this way, the effect of increasing the transistor density or/and simplifying the layout design and manufacturing process of the relevant leads is achieved. In addition, the drain trench and the contact trench can be formed together with the same process, thereby achieving the effect of simplifying the process. The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: base 10A: first side 10B: Second side 12: buffer layer 14: Second III-V compound layer 16: The first III-V compound layer 18: Third III-V compound layer 18V: opening 20: Nitride layer 22: Gate dielectric layer 24: Isolation structure 26: Dielectric layer 28: Carrier board 30: first conductive layer 31: Second conductive layer 32: Insulation 90: Thinning process 101-102: Semiconductor devices CS1: contact structure CS2: back contact structure D1: First direction D2: Second direction DE: Jiji GE: Gate P1: Part One P2: Part Two P3: Part III R1: District 1 R2: District 2 SE: source TR1: Drain trench TR2: contact groove

FIGS. 1 to 5 are schematic diagrams of the manufacturing method of the semiconductor device according to the first embodiment of the present invention, in which Figure 2 shows a schematic diagram of the manufacturing method after Figure 1; Figure 3 shows a schematic diagram of the manufacturing method after Figure 2; Figure 4 shows a schematic diagram of the manufacturing method after Figure 3; Figure 5 shows a schematic diagram of the manufacturing method after Figure 4. 6 to 9 are schematic diagrams of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, in which Figure 7 shows a schematic diagram of the manufacturing method after Figure 6; Figure 8 shows a schematic diagram of the manufacturing method after Figure 7; Figure 9 shows a schematic diagram of the manufacturing method after Figure 8. FIG. 10 is a schematic diagram of a method for manufacturing a semiconductor device according to a third embodiment of the invention. FIG. 11 is a schematic diagram of a method for manufacturing a semiconductor device according to a fourth embodiment of the invention. FIG. 12 is a schematic diagram of a method for manufacturing a semiconductor device according to a fifth embodiment of the invention.

10: base

10A: first side

10B: Second side

12: buffer layer

14: Second III-V compound layer

16: The first III-V compound layer

18: Third III-V compound layer

18V: opening

20: Nitride layer

22: Gate dielectric layer

24: Isolation structure

26: Dielectric layer

28: Carrier board

30: first conductive layer

CS1: contact structure

CS2: back contact structure

D1: First direction

D2: Second direction

DE: Jiji

GE: Gate

P1: Part One

P2: Part Two

P3: Part III

R1: District 1

R2: District 2

SE: source

TR1: Drain trench

TR2: contact groove

Claims (20)

A method for manufacturing a semiconductor device includes: Providing a substrate having a first side and a second side opposite to the first side; Forming a first III-V compound layer on the first side of the substrate; A drain trench and a contact trench are formed from the second side of the substrate, wherein the drain trench extends from the second side of the substrate toward the first side through the substrate, and the contact trench is The second side of the substrate extends toward the first side and penetrates the substrate, and the drain trench and the contact trench are formed together by the same process; Forming a drain in the drain trench; and A back contact structure is formed in the contact trench. The method for manufacturing a semiconductor device according to claim 1, wherein the back contact structure is electrically separated from the drain electrode. The method for manufacturing a semiconductor device according to claim 1, further comprising: Forming a gate on the first side of the substrate, wherein part of the first III-V compound layer is located between the gate and the substrate; and A contact structure is formed on the first side of the substrate, wherein the contact structure is electrically connected to the back contact structure. The method for manufacturing a semiconductor device according to claim 3, wherein the gate electrode and the contact structure are formed before the drain trench and the contact trench. The method for manufacturing a semiconductor device according to claim 3, wherein the gate electrode and the contact structure are formed after the drain electrode and the back contact structure. The method for manufacturing a semiconductor device according to claim 1, further comprising: Before forming the drain trench and the contact trench, a thinning process is performed on the substrate from the second side of the substrate. The method for manufacturing a semiconductor device according to claim 1, further comprising: Forming a buffer layer on the first side of the substrate, and at least a portion of the buffer layer is located between the substrate and the first III-V compound layer; and A second III-V compound layer is formed on the buffer layer, wherein the second III-V compound layer is located between the first III-V compound layer and the buffer layer. The method for manufacturing a semiconductor device according to claim 7, wherein the drain trench further penetrates the buffer layer and is partially disposed in the second III-V compound layer. The method for manufacturing a semiconductor device according to claim 7, wherein the contact trench further penetrates the buffer layer and is partially disposed in the second III-V compound layer. The method for manufacturing a semiconductor device according to claim 7, wherein the first group III-V compound layer includes an N-type lightly doped gallium nitride layer, and the second group III-V compound layer includes an N-type heavily doped GaN layer. The method for manufacturing a semiconductor device according to claim 1, further comprising: An isolation structure is formed on the first side of the substrate, and the contact trench is further formed in the isolation structure. The method for manufacturing a semiconductor device according to claim 11, further comprising: Forming a gate on the first side of the substrate, wherein part of the first III-V compound layer is located between the gate and the substrate; and A contact structure is formed on the first side of the substrate, wherein the contact structure is at least partially formed in the isolation structure, and the contact structure is electrically connected to the back contact structure. The method for manufacturing a semiconductor device according to claim 11, wherein the isolation structure is formed before the contact trench. The method for manufacturing a semiconductor device according to claim 1, further comprising: After the drain and the back contact structure are formed, an insulating layer is formed on the second side of the substrate to cover the drain and the back contact structure. The method for manufacturing a semiconductor device according to claim 14, wherein the insulating layer is partially formed in the drain trench and the contact trench. The method for manufacturing a semiconductor device according to claim 15, wherein the drain trench is filled by the insulating layer and the drain, and the contact trench is filled by the insulating layer and the back contact structure. The method for manufacturing a semiconductor device according to claim 1, wherein the drain trench is filled by the drain, and the contact trench is filled by the back contact structure. The method for manufacturing a semiconductor device according to claim 1, wherein the material composition of the back contact structure is the same as the material composition of the drain electrode. The method for manufacturing a semiconductor device according to claim 1, further comprising: A source electrode is formed on the first side of the substrate, and a portion of the first III-V compound layer is located between the source electrode and the substrate. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate includes a silicon substrate.

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