JP5468609B2 - Vertical transistor, method for manufacturing the same, and semiconductor device - Google Patents

Description

  The present invention relates to a vertical transistor, a manufacturing method thereof, and a semiconductor device. More specifically, the present invention relates to a vertical transistor using a nitride-based semiconductor and a manufacturing method thereof. The present invention also relates to a semiconductor device on which the vertical transistor is mounted.

  Nitride-based semiconductors such as GaN, AlGaN, InGaN, InAlN, and InAlGaN have the characteristics of having high dielectric breakdown strength, high thermal conductivity, and high electron saturation speed. For this reason, nitride-based semiconductors are promising as semiconductor materials for use in the production of power devices for power control such as high-frequency devices and switching elements. In recent years, field-effect transistors using nitride-based semiconductor materials have been actively developed and developed.

  In the application of nitride-based semiconductors to high-frequency devices and power devices for power control, nitride semiconductors are epitaxially grown on inexpensive dissimilar substrates such as sapphire, silicon carbide (SiC), and silicon (Si) to produce devices. It has become common to do. Compared to the case of using a GaN substrate with extremely high manufacturing cost, the manufacturing cost can be reduced.

  In the development of power devices using nitride semiconductors, lateral transistors using two-dimensional electron gas (2DEG) accumulated as a carrier at the epitaxially grown AlGaN / GaN heterojunction interface have been developed. It is ahead. However, in the lateral transistor, (1) both the source electrode and the drain electrode must be formed on the wafer surface, and (2) a long drift region for obtaining a high breakdown voltage must be formed along the surface. As a result, the device area tends to increase. Therefore, from the viewpoint of reducing the on-resistance per unit area, it is desired to develop a vertical transistor in which the drain electrode is formed on the back surface and the drift region is formed in the thickness direction of the substrate.

  Here, consider a case where a vertical transistor is manufactured using a wafer obtained by epitaxially growing a nitride semiconductor on a substrate such as sapphire, silicon carbide (SiC), or silicon (Si). In order to obtain a high-quality epitaxial layer on these substrates, it is generally known that it is necessary to grow a buffer layer including an AlN layer on the substrate. A nitride semiconductor epitaxial layer such as GaN or AlGaN is grown on the buffer layer. A vertical transistor is manufactured by forming a source electrode on the front surface of the wafer and a drain electrode on the back surface of the substrate.

  However, in the vertical transistor having the above structure, an AlN layer having a large band gap between the substrate and the nitride semiconductor epitaxial layer serves as a barrier. In other words, a large resistance exists between the substrate and the nitride semiconductor epitaxial layer. As a result, it has been difficult to reduce the on-resistance of the transistor.

As means for solving this problem, Patent Document 1 discloses a vertical transistor manufactured by bonding a GaN thin film to a different substrate. FIG. 7 is a schematic cross-sectional view of a GaN-based vertical transistor disclosed in Patent Document 1. A GaN-based vertical transistor described in Patent Document 1 has a conductive (carrier concentration: 4 × 10 ¹⁸ cm ⁻³ , specific resistance: 0.01 Ωcm) on a conductive Si substrate (heterogeneous substrate) 150A as a substrate. GaN thin film bonded substrate 150 to which single crystal GaN thin film 150B is bonded is used.

On the GaN thin film bonded substrate 150, a 10 μm thick n ⁻ -type GaN layer 113 (electron concentration: 1 × 10 ¹⁶ cm ⁻ ) formed by MOCVD (Metal Organic Chemical Vapor Deposition) as a GaN-based semiconductor layer 120. ³ ), a p-type layer 114 implanted with Mg ions is formed in a partial region of the n ⁻ -type GaN layer 113, and n ⁺ implanted with Si ions in a partial region of the p-type layer 114. A mold layer 115 is formed.

An insulating film 116 made of SiO ₂ having a thickness of 50 nm formed by p-CVD (Chemical Vapor Deposition) method is formed on the GaN-based semiconductor layer 120, and the insulating film 116 is partially opened. A source electrode 152 made of Ti / Al / Ti / Au is formed in the region. In addition, a gate electrode 151 made of Al is formed on a part of the insulating film 116 to form a MIS (metal-insulator-semiconductor) structure. A drain electrode 153 made of Ti / Al / Ti / Au is formed on the back surface of the conductive Si substrate (different substrate) 150A.

  According to Patent Document 1, since there is no AlN layer having a large band gap between the Si substrate (heterogeneous substrate) 150A and the GaN thin film 150B, a method of epitaxially growing a nitride-based semiconductor layer on the Si substrate described above is used. In comparison, the on-resistance can be reduced.

JP 2008-10766 A

  However, in the vertical transistor having the configuration shown in FIG. 7, it is difficult to sufficiently reduce the resistance at the bonding interface between the conductive Si substrate 150A and the conductive GaN thin film 150B. The reduction effect was not sufficient.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a vertical transistor capable of effectively reducing on-resistance, a manufacturing method thereof, and a semiconductor device.

The vertical transistor according to the present invention includes a conductive semiconductor substrate, a conductive oxide film formed on the surface of the conductive semiconductor substrate, having a specific resistance of 3 × 10 ⁻⁴ Ωcm or less, and is attached on the conductive oxide film. And an n ⁺ -type or p ⁺ -type nitride semiconductor thin film having an impurity concentration of 5 × 10 ¹⁷ cm ⁻³ or more, and a nitride semiconductor epitaxially grown on the nitride semiconductor thin film. A stack, a source electrode or emitter electrode formed on the surface of the stack, a drain electrode or collector electrode formed on the back surface of the conductive semiconductor substrate, and between the source electrode and the drain electrode, or And a gate electrode having a function of controlling a magnitude of a current flowing between the emitter electrode and the collector electrode.

  In the method for manufacturing a vertical transistor according to the present invention, a conductive oxide film is formed on a conductive semiconductor substrate, a nitride semiconductor thin film is formed on the conductive oxide film, and the nitride semiconductor thin film is formed. A layered body made of a nitride semiconductor is epitaxially grown on the upper layer, a source electrode or an emitter electrode is formed on the surface of the layered body, and a drain electrode or a collector electrode is formed on the back surface of the conductive semiconductor substrate. .

  According to the present invention, there is an excellent effect that it is possible to provide a vertical transistor capable of sufficiently reducing the on-resistance, a manufacturing method thereof, and a semiconductor device.

FIG. 2 is a schematic cross-sectional view schematically illustrating an example of a configuration of a vertical transistor according to the first embodiment. FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment. FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment. FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment. FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment. FIG. 4 is a manufacturing process cross-sectional view of the vertical transistor according to the first embodiment. FIG. 5 is a schematic cross-sectional view schematically illustrating an example of a configuration of a vertical transistor according to a second embodiment. FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment. FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment. FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment. FIG. 5 is a schematic cross-sectional view schematically illustrating an example of a configuration of a vertical transistor according to a third embodiment. FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment. FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment. FIG. 10 is a manufacturing process cross-sectional view of a vertical transistor according to the second embodiment. FIG. 10 is a schematic cross-sectional view of a vertical transistor described in Patent Document 1.

In the vertical transistor according to the present invention, a conductive oxide film having a specific resistance of 3 × 10 ⁻⁴ Ωcm or less is formed on the surface of a conductive semiconductor substrate. An n ⁺ type or p ⁺ type nitride-based semiconductor thin film formed by bonding is disposed on the conductive oxide film. The impurity concentration of the nitride-based semiconductor thin film is set to 5 × 10 ¹⁷ cm ⁻³ or more. Further, on the nitride semiconductor thin film, a laminated body made of the nitride semiconductor epitaxially grown is formed. The source electrode or emitter electrode of the vertical transistor is formed on the surface of the stacked body. On the other hand, the drain electrode or the collector electrode is formed on the back side of the conductive semiconductor substrate. The gate electrode has a function of controlling the magnitude of a current flowing between the source electrode and the drain electrode or between the emitter electrode and the collector electrode.

  As a result of intensive studies to obtain a vertical transistor capable of effectively reducing on-resistance and a method for manufacturing the same, the present inventors have found that the object of the present invention can be achieved in the above-described configuration. The invention has been completed. Hereinafter, an example of an embodiment to which the present invention is applied will be described with a specific example. The following specific examples are examples of the best embodiment of the present invention, but the present invention is not limited to these embodiments. Moreover, the size and ratio of each member in the following drawings are for convenience of explanation, and are different from actual ones.

[Embodiment 1]
FIG. 1 is a cross-sectional view schematically showing the structure of the vertical transistor according to the first embodiment. The vertical transistor 1 according to the first embodiment includes a conductive semiconductor substrate 50, a gate electrode 51, a source electrode 52, a drain electrode 53, a conductive oxide film 11, a nitride semiconductor thin film 12, and a stacked semiconductor film. The body 20 and the insulating film 16 are provided.

  The conductive semiconductor substrate 50 can be applied without particular limitation as long as it does not depart from the spirit of the present invention. From the viewpoint of reducing the manufacturing cost, it is preferable to select a material that can obtain a large-diameter substrate of 6 inches or more at a low cost. Suitable examples of such a conductive semiconductor substrate material include Si, poly-Si, poly-SiC and the like. By applying these, a low on-resistance vertical transistor can be manufactured at low cost. In the first embodiment, n-type Si having a specific resistance of 0.02 Ωcm is applied.

The conductive oxide film 11 is formed on the conductive semiconductor substrate 50. The specific resistance of the conductive oxide film 11 is at least 3 × 10 ⁻⁴ Ωcm or less. By setting it to 3 × 10 ⁻⁴ Ωcm or less, it is possible to obtain an effect that the on-resistance can be lowered as compared with the case where the nitride-based semiconductor thin film 12 is directly bonded to the conductive semiconductor substrate 50 as in the prior art. A more preferable range is 2 × 10 ⁻⁴ Ωcm or less, and a particularly preferable range is 1 × 10 ⁻⁴ Ωcm or less. The lower limit value of the specific resistance of the conductive oxide film 11 is not particularly limited, but is preferably 2 × 10 ⁻⁶ Ωcm or more in order to realize a high-quality film quality that does not deteriorate strength or resistance due to long-term conduction. The material of the conductive oxide film 11 can be applied without particular limitation as long as it does not depart from the spirit of the present invention. From the viewpoint of obtaining a stable and strong bonded substrate, the conductive oxide film 11 preferably has a melting point of 1300 ° C. or higher. By using a material having a high melting point in this way, even for manufacturing processes that require high temperatures of about 1000 ° C., such as crystal growth of nitride-based semiconductors by metal organic vapor phase epitaxy (MOVPE). A stable and strong bonded substrate can be obtained. The upper limit of the melting point of the conductive oxide film 11 is not particularly limited. In Embodiment 1, Al-doped ZnO (ZAO) having a specific resistance of 2 × 10 ⁻⁴ Ωcm is used as the conductive oxide film 11.

  Although the film thickness of the conductive oxide film 11 is not specifically limited, For example, it can be set to 5 nm or more and 1000 nm or less. A more preferable range is 10 nm or more and 500 nm or less, and a particularly preferable range is 20 nm or more and 300 nm or less.

The nitride-based semiconductor thin film 12 can be formed by bonding a nitride-based semiconductor bulk crystal on the conductive oxide film 11 and dividing it in the thickness direction. The impurity concentration of the nitride-based semiconductor thin film 12 is set to 5 × 10 ¹⁷ cm ⁻³ or more. By setting it as 5 * 10 < ¹⁷ > cm < ^-3 > or more, the effect that the nitride-type semiconductor thin film 12 and the electroconductive oxide film 11 can be connected by resistance low enough is acquired. A more preferable range is 1 × 10 ¹⁸ cm ⁻³ or more. The upper limit of the impurity concentration of the nitride-based semiconductor thin film 12 is preferably 5 × 10 ²⁰ cm ⁻³ or less. When it exceeds 5 × 10 ²⁰ cm ⁻³ , the crystallinity of the stacked body 20 formed on the nitride-based semiconductor thin film 12 is deteriorated, and the reliability of the device may be impaired. By introducing impurities, it becomes a P ⁺ type or an n ⁺ type. In the first embodiment, n ⁺ -GaN having an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ and a film thickness of 0.1 μm is formed.

The stacked body 20 made of a nitride-based semiconductor is formed on the nitride-based semiconductor thin film 12. The stacked body 20 is obtained by epitaxial growth. In the stacked body 20, the drift layer 13, the channel layer 14, and the contact layer 15 are formed in this order from the nitride-based semiconductor thin film 12 side. In the first embodiment, n ⁻ -GaN having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ and a film thickness of 3 μm is used as the drift layer 13, and a film having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ is used as the channel layer 14. P-GaN having a thickness of 0.6 μm was used as the contact layer 15 and n ⁺ -GaN having an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ and a thickness of 0.5 μm was applied.

  The source electrode 52 is formed on the surface of the contact layer 15, and the drain electrode 53 is formed on the back surface of the conductive semiconductor substrate 50. For the source electrode 52 and the drain electrode 53, in the first embodiment, an electrode made of Ti / Al (Ti is a lower layer side and Al is an upper layer side (hereinafter the same)) is applied.

A part of the stacked body 20 is formed with an upper surface side trench 21 reaching the drift layer 13 from the surface thereof, and contacts extending from the inner and bottom surfaces of the upper surface side trench 21 and the inner wall of the upper surface side trench 21. A part of the surface of the layer 15 is covered with a gate insulating film 16 made of SiO ₂ . Furthermore, a gate electrode 51 made of Ni / Au is formed on the inner wall and bottom surface of the upper surface side trench 21.

  The first embodiment is a so-called trench gate type field effect transistor in which a channel is formed by the channel layer 14 in contact with the side surface of the upper side trench 21 being an inversion region.

  Next, a method for manufacturing the vertical transistor according to the first embodiment will be described. First, the conductive oxide film 11 is formed on the conductive semiconductor substrate 50, and the nitride-based semiconductor thin film 12 is formed on the conductive oxide film 11. Then, the stacked body 20 made of the nitride-based semiconductor is epitaxially grown on the nitride-based semiconductor thin film 12 to form the source electrode 52 on the surface of the stacked body 20. Then, the drain electrode 53 is formed on the back surface of the conductive semiconductor substrate 50. Hereinafter, a specific example of the method for manufacturing the vertical transistor according to the first embodiment will be described with reference to FIGS. 2A to 2E. 2A to 2E are cross-sectional views schematically showing the manufacturing process of the vertical transistor according to the first embodiment.

  First, a nitride-based semiconductor bulk crystal 30 whose surface to be bonded to the conductive semiconductor substrate 50 is mirror-polished is prepared. In the first embodiment, a GaN bulk crystal is prepared as the nitride-based semiconductor bulk crystal 30. Then, hydrogen ions are implanted, for example, to a depth of 0.1 μm from the bonding surface (hereinafter also referred to as “N surface (nitrogen atom surface)”) (FIG. 2A). Note that helium ions or nitrogen ions may be used instead of hydrogen ions. Further, mirror polishing of a nitride semiconductor bulk crystal is not always essential. However, the surface roughness should be at a level that does not cause a problem in bonding the nitride semiconductor bulk crystal 30 and the conductive oxide film 11.

  Next, the conductive oxide film 11 made of Al-added ZnO (ZAO) is formed on the conductive semiconductor substrate 50 by sputtering (FIG. 2B). Next, the N surface of the nitride-based semiconductor bulk crystal 30 and the surface of the conductive oxide film 11 are bonded together by a fusion bonding method or the like. Thereafter, the nitride semiconductor bulk crystal 30 is divided in the thickness direction at the hydrogen ion implantation surface by performing a heat treatment at 450 ° C. Thereby, the nitride-based semiconductor thin film 12 is formed (FIG. 2C). The nitride semiconductor bulk crystal 30 is separated from the conductive semiconductor substrate 50 side at a depth of, for example, 0.1 μm.

  The bonding of the nitride-based semiconductor bulk crystal 30 and the conductive semiconductor substrate 50 is not limited to the fusion bonding method, and a known method can be applied without limitation. For example, the N surface may be bonded by a surface activation method in which the surface is activated by exposing it to plasma and then bonded. The method for obtaining the nitride-based semiconductor thin film 12 is not limited to the method using the nitride-based semiconductor bulk crystal described above, and various methods can be adopted without departing from the spirit of the present invention. it can. For example, a nitride-based semiconductor thin film may be obtained by epitaxially growing a nitride-based semiconductor on a heterogeneous substrate, and bonding the growth surface side onto a conductive oxide film, and then peeling the heterogeneous substrate.

Subsequently, the drift layer 13 made of n ⁻ -GaN having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ and a film thickness of 3 μm is formed on the nitride-based semiconductor thin film 12 by metal organic vapor phase epitaxy. A channel layer 14 made of p-GaN having a film thickness of 0.6 μm at 1 × 10 ¹⁸ cm ⁻³ and a contact made of n ⁺ -GaN having an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ and a film thickness of 0.5 μm. Layer 15 is grown in this order (FIG. 2D).

  Thereafter, the source electrode 52 is formed. Specifically, a Ti / Al (30 nm / 180 nm) electrode pattern is formed by vapor deposition / lift-off using a photoresist mask in which an opening pattern is formed in a region where the source electrode 52 is formed. The source electrode 52 is obtained by performing RTA (Rapid Thermal Anneal) at 700 ° C. for 60 seconds.

Next, an upper surface side trench 21 reaching the drift layer 13 from the surface of the contact layer 15 is formed. Specifically, it is formed by an ICP (Inductively Coupled Plasma) dry etching method using a photoresist mask in which an opening pattern is formed in a predetermined region. Then, in order to remove damage on the inner wall of the upper surface side trench 21, a wet etching process using NH ₄ OH (ammonia water) is performed. Thereafter, the gate insulating film 16 that covers the inner wall surface and the edge of the upper-side trench 21 is formed by using an ECR (Electron Cyclotron Resonance) sputtering method (FIG. 2E).

  Next, the gate electrode 51 is formed. Specifically, a Ni / Au (30 nm / 300 nm) electrode pattern is formed at a predetermined position by using a vapor deposition / lift-off method using a photoresist mask in which an opening pattern is formed in a region where the gate electrode 51 is formed. To do.

  Subsequently, the drain electrode 53 is formed. Specifically, first, the back surface of the conductive semiconductor substrate 50 is polished and thinned. Thereafter, a drain electrode 53 made of Ti / Al is formed on the back surface of the conductive semiconductor substrate 50 using a vacuum deposition method. Through the above steps, a vertical transistor made of a nitride-based semiconductor having the configuration shown in FIG. 1 is manufactured.

  Next, the reason why the vertical transistor according to Embodiment 1 can sufficiently reduce the on-resistance will be described. First, the reason why it is difficult to sufficiently reduce the on-resistance in the vertical transistor of FIG. 7 (Patent Document 1) will be described.

  In the configuration of FIG. 7, the first cause of difficulty in sufficiently reducing the resistance at the bonding interface is a large difference between the Si band gap (1.1 eV) and the GaN band gap (3.4 eV). There is. When such a band gap difference (2.3 eV) is directly bonded, a very large band discontinuity of about 1 eV exists in the conduction band and valence band of the bonding interface. When this band discontinuity becomes a large potential barrier, a large resistance is generated at the Si / GaN interface. That is, in the configuration in which the conductive Si substrate 150A and the conductive GaN thin film 150B are bonded together, it is difficult to sufficiently reduce the on-resistance of the vertical transistor.

  As a method of solving this problem, a method of using single crystal SiC (band gap: 3.2 eV) whose band gap is close to that of GaN as a substrate can be considered. However, single crystal SiC substrates are significantly expensive. Also, there is no large diameter wafer. For this reason, compared with device manufacture using a Si substrate, cost will increase remarkably. That is, with the configuration shown in FIG. 7, it is difficult to manufacture a vertical transistor with a sufficiently reduced on-resistance at a low cost.

The second cause that it is difficult to sufficiently reduce the resistance at the bonding interface is due to bonding of semiconductor materials such as the Si substrate 150A and the GaN thin film 150B. In the case of a semiconductor element using a bonded substrate, a large amount of dangling bonds (dangling bonds) exist at the bonding interface. And this unbonded hand functions as a carrier trap. For this reason, the occurrence of interface resistance due to carrier traps at the interface is inevitable at the bonding interface. In order to sufficiently reduce the interface resistance, it is effective to configure one of the materials to be bonded with a conductor having a low specific resistance (for example, 3 × 10 ⁻⁴ Ωcm or less).

However, in the vertical transistor shown in FIG. 7, the materials to be bonded are Si and GaN, both of which are semiconductors. The semiconductor material can have conductivity by adding impurities, but the specific resistance obtained in a state of maintaining good crystallinity is at most about 1 × 10 ⁻² Ωcm. That is, both layers to be bonded are made of a material having a high specific resistance, and it is difficult to sufficiently reduce the interface resistance. This problem cannot be solved even when another semiconductor substrate such as a single crystal SiC substrate is used instead of the Si substrate. As a result, with the configuration shown in FIG. 7, it was difficult to manufacture a vertical transistor with sufficiently reduced on-resistance.

On the other hand, in the first embodiment, the specific resistance is 3 × 10 ⁻⁴ Ωcm or less (in the specific example, 2 × 10 ⁻⁴ Ωcm) between the conductive semiconductor substrate 50 and the nitride-based semiconductor thin film 12. A conductive oxide film 11 is provided. Thereby, a junction can be formed without generating a large interface resistance at the interface between the conductive oxide film 11 and the conductive semiconductor substrate 50. For the same reason, a junction can be formed without generating a large interface resistance at the interface between the conductive oxide film 11 and the nitride-based semiconductor thin film 12.

  In the first embodiment, the conductive oxide film 11 is made of a material having a band gap of Al-doped ZnO (ZAO) close to GaN (ZnO: 3.3 eV, GaN: 3.4 eV). The interfacial resistance at the interface between the conductive oxide film 11 and the nitride-based semiconductor thin film 12 can be particularly reduced. Moreover, since the Si substrate is used as the conductive semiconductor substrate, there is an advantage that it is inexpensive.

  Due to the above effects, the vertical transistor 1 according to the first embodiment has an on-resistance of about several tens of percent to about half that of a gate-type field effect transistor manufactured using a conventional low-cost bonding technique. Can be reduced.

According to the first embodiment, the conductive oxide film 11 having a low specific resistance of 3 × 10 ⁻⁴ Ωcm or less is disposed between the conductive semiconductor substrate 50 and the nitride-based semiconductor thin film 12. As a result, the interface resistance can be greatly reduced at any of the interfaces of the conductive semiconductor substrate 50 / conductive oxide film 11 and conductive oxide film 11 / nitride-based semiconductor thin film 12. As a result, a low on-resistance vertical transistor can be realized.
[Embodiment 2]

  Next, an example of a vertical transistor different from the above embodiment will be described. The vertical transistor 2 according to the second embodiment is a so-called insulated gate bipolar transistor (IGBT) in which a P collector is added to the drain side of an N-channel vertical MOSFET.

  The basic structure of the vertical transistor according to Embodiment 2 is the same as that of Embodiment 1 except for the following points. In other words, the upper surface side trench 21 is formed in the stacked body 20 in the first embodiment, but the second embodiment is different in that the upper surface side trench 21 is not formed in the stacked body. Therefore, the structure of the laminate is different from that of the first embodiment. Accordingly, the shapes of the insulating film and the gate electrode arranged on the upper layer of the stacked body are different. In the first embodiment, the source electrode is disposed in the upper layer of the stacked body 20, whereas in the second embodiment, the emitter electrode is formed in the upper layer of the stacked body 20 instead of the source electrode. Is different. Further, in the first embodiment, the drain electrode is formed on the back side of the conductive semiconductor substrate 50, whereas in the second embodiment, the drain electrode is changed to the collector electrode on the back side of the conductive semiconductor substrate. The difference is that an electrode is formed.

  FIG. 3 is a sectional view schematically showing the structure of the vertical transistor according to the second embodiment. The vertical transistor 2 according to the second embodiment includes a conductive semiconductor substrate 50a, a gate electrode 51a, an emitter electrode 55, a collector electrode 56, a conductive oxide film 11a, a nitride-based semiconductor thin film 12a, and a stacked layer including a nitride-based semiconductor. A body 20a, an insulating film 16a, and the like.

The vertical transistor 2 has at least the following structure. That is, the conductive oxide film 11a having a specific resistance of 3 × 10 ⁻⁴ Ωcm or less is formed on the conductive semiconductor substrate 50a. On the conductive oxide film 11a, a p ⁺ type nitride-based semiconductor thin film 12a having an impurity concentration of 5 × 10 ¹⁷ cm ⁻³ or more is formed. On the nitride semiconductor thin film 12a, a stacked body 20a made of a nitride semiconductor obtained by epitaxial growth is formed. An emitter electrode 55 is formed on the surface of the stacked body 20a, and a collector electrode 56 is formed on the back surface of the conductive semiconductor substrate 50a. A gate electrode 51a having a function of controlling the magnitude of the current flowing between the emitter electrode 55 and the collector electrode 56 is formed.

  Hereinafter, a specific example of the second embodiment will be described. The configuration, preferable materials, and the like of the conductive semiconductor substrate 50a are as described in the first embodiment. In the second embodiment, p-type poly SiC having a specific resistance of 0.04 Ωcm is used.

The specific resistance range and preferred materials of the conductive oxide film 11a are the same as those in the first embodiment. In the second embodiment, ITO having a specific resistance of 1.5 × 10 ⁻⁴ Ωcm is used as the conductive oxide film 11a. Further, p ⁺ -GaN having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ and a film thickness of 0.3 μm was used as the nitride-based semiconductor thin film 12a.

In order to more effectively realize the low on-resistance of the vertical transistor, it is preferable to select a material in which the band gap of the conductive oxide film is 2.8 eV to 4.0 eV. By using a conductive material having a band gap in this range, it is possible to more effectively reduce the interface resistance with the nitride-based semiconductor thin film formed immediately above the conductive material. This is because the band gap difference from the nitride semiconductor thin film can be reduced (when GaN is applied as the nitride semiconductor thin film, the band gap is 3.4 eV). Suitable materials of the conductive oxide film band gap becomes 2.8EV～4.0EV, mention may be made of _ITO, ZnO, and TiO _2, SnO _2, CdO, and the like. Further, in order to effectively reduce the specific resistance, a material obtained by adding a metal impurity to the above-described material can be suitably applied.

The stacked body 20a includes a drift layer 13a, a channel layer 14a, and a contact layer 15a. The drift layer 13a is made of n ⁻ -GaN having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ and a film thickness of 5 μm, and the channel layer 14a is made of p-GaN having an impurity concentration of 1 × 10 ¹⁸ cm ^−3. Applied. Further, n ⁺ -GaN having an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ was applied to the contact layer 15a.

  The shape of the drift layer 13a has a structure having a convex portion as shown in FIG. The channel layer 14a and the contact layer 15a are formed in this order on both sides of the protruding portion of the drift layer 13a (see FIG. 3).

  The emitter electrode 55 is formed at a predetermined position on the surface of the contact layer 15a. As described above, the collector electrode 56 is formed on the back side of the conductive semiconductor substrate 50a. The emitter electrode 55 and the collector electrode 56 are both made of Ti / Al. Of course, the composition ratio and the like of the emitter electrode 55 and the collector electrode 56 can be changed as appropriate and do not need to match. Different materials may be used.

  A gate insulating film 16a is formed on the surface of the stacked body 20a so as to cover a part of the surface of the contact layer 15a, the entire surface of the channel layer 14a, and at least a part of the surface of the drift layer 13a. The gate electrode 51a is formed on the gate insulating film 16a so as to be opposed to the drift layer 13a, the channel layer 14a disposed outside the gate insulating film 16a, and the contact layer 15a. In the second embodiment, Ni / Au is applied as the gate electrode 51a. The vertical transistor 2 according to the second embodiment is configured as described above.

  Next, a method for manufacturing the vertical transistor according to the second embodiment will be described. First, the conductive oxide film 11a is formed on the conductive semiconductor substrate 50a, and the nitride-based semiconductor thin film 12a is formed on the conductive oxide film 11a. Then, a stacked body 20a made of a nitride-based semiconductor is epitaxially grown on the nitride-based semiconductor thin film 12a, and an emitter electrode 55 is formed on the surface of the stacked body 20a. Then, a collector electrode 56 is formed on the back surface of the conductive semiconductor substrate 50a. Hereinafter, a specific example of the manufacturing method of the vertical transistor according to the second embodiment will be described with reference to FIGS. 4A to 4C. 4A to 4C are cross-sectional views schematically showing the manufacturing process of the vertical transistor according to the second embodiment.

  First, in the same manner as in the first embodiment, a substrate in which the conductive oxide film 11a and the nitride semiconductor thin film 12a are bonded to the conductive semiconductor substrate 50a is manufactured (FIG. 4A). The only difference from Embodiment 1 is that the materials are different as described above, and a bonded substrate can be produced in exactly the same manner as in FIGS. 2A to 2C.

Next, a drift layer 13a made of n ⁻ -GaN having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ and a film thickness of 5 μm is grown on the nitride-based semiconductor thin film 12a by metal organic vapor phase epitaxy. . Thereafter, Mg ions are implanted into a partial region of the drift layer 13a by selective ion implantation to form the channel layer 14a. Next, Si ions are implanted into part of the channel layer 14a to form the contact layer 15a, thereby obtaining a stacked body 20a made of a nitride-based semiconductor. After forming a 200 nm SiO ₂ film as a protective film (not shown) on the surface of the stacked body 20a, heat treatment is performed at 1250 ° C. for 60 seconds. Thereby, the implanted ions are activated. Thereafter, the protective film is removed with buffered hydrofluoric acid (FIG. 4B).

A gate insulating film 16a made of Al ₂ O ₃ is formed on the stacked body 20a by using an ALD (Atomic Layer Deposition) method. A portion of the gate insulating film 16a is etched with buffered hydrofluoric acid using a photoresist mask in which an opening pattern is formed in the region where the emitter electrode 55 is to be formed. 30 nm / 180 nm) electrodes are formed at predetermined positions. Next, RTA is performed at 700 ° C. for 60 seconds to obtain the emitter electrode 55 (FIG. 4C).

  A Ni / Au (30 nm / 300 nm) electrode is formed at a predetermined position using a photoresist mask having an opening pattern in a region where the gate electrode 51a is to be formed, using an evaporation / lift-off method. After the back surface of the conductive semiconductor substrate 50a is polished and thinned, a drain electrode 53a made of Ti / Al is formed on the back surface of the conductive semiconductor substrate 50a by using a vacuum deposition method, so that the configuration of FIG. 3 is obtained. A vertical transistor is manufactured.

In the second embodiment, the conductive oxide film 11a having a specific resistance of 3 × 10 ⁻⁴ Ωcm or less (in the specific example, 1.5 × 10 ⁻⁴ Ωcm) is used. A junction can be formed without generating large interface resistance at the interface with the semiconductor substrate 50a. For the same reason, a junction can be formed without generating a large interface resistance at any of the interfaces between the conductive oxide film 11a and the nitride-based semiconductor thin film 12a.

Moreover, since the conductive oxide film 11a is made of a material having a band gap of ITO close to that of GaN (ITO: 3 eV, GaN: 3.4 eV), the interface between the conductive oxide film 11a and the nitride-based semiconductor thin film 12a. The interfacial resistance can be made particularly low. Furthermore, since the band gap of ITO is close to the band gap (2.3 eV to 3.2 eV) of poly SiC used for the conductive semiconductor substrate 50a, the band gap of the conductive oxide film 11a and the conductive semiconductor substrate 50a is the same. The interface resistance can be lowered. Due to the above-described effects, the vertical transistor 2 according to the second embodiment has an on-resistance approximately several times that of an insulated gate bipolar transistor using a nitride-based semiconductor manufactured using a conventional low-cost bonding technique. It can be reduced from 10% to about half.
[Embodiment 3]

  The vertical transistor according to the third embodiment is a so-called high electron mobility transistor (HEMT).

  The basic structure of the vertical transistor according to Embodiment 3 is the same as that of Embodiment 1 except for the following points. That is, in Embodiment 1 above, no trench was formed in the conductive semiconductor substrate 50, whereas in Embodiment 3, a trench reaching the conductive oxide film was formed in the conductive semiconductor substrate. Is different. Moreover, the structure of a laminated body differs from the said Embodiment 1. FIG.

  FIG. 5 is a cross-sectional view schematically showing the structure of the vertical transistor according to the third embodiment. The vertical transistor 3 according to the third embodiment includes a conductive semiconductor substrate 50b, a gate electrode 51b, a source electrode 52b, a drain electrode 53b, a conductive oxide film 11b, a nitride-based semiconductor thin film 12b, and a stacked layer composed of a nitride-based semiconductor. A body 20b and the like are provided.

The vertical transistor 3 has at least the following structure. That is, the conductive oxide film 11b having a specific resistance of 3 × 10 ⁻⁴ Ωcm or less is formed on the conductive semiconductor substrate 50b. On the conductive oxide film 11b, an n ⁺ -type or p ⁺ -type nitride semiconductor thin film 12b having an impurity concentration of 5 × 10 ¹⁷ cm ⁻³ or more is formed. On the nitride semiconductor thin film 12b, a stacked body 20b made of a nitride semiconductor obtained by epitaxial growth is formed. A source electrode 52b is formed on the surface of the stacked body 20b. A part of the conductive semiconductor substrate 50b is formed with a back side trench 23 that reaches the conductive oxide film 11b from the back side. A drain electrode 53b is formed on the back surface of the conductive semiconductor substrate 50b and the inner wall of the back surface side trench 23 to cover them. A gate electrode 51b having a function of controlling the magnitude of current flowing between the source electrode 52b and the drain electrode 53b is formed on the stacked body 20b.

  Hereinafter, a specific example of the third embodiment will be described. The configuration, preferable materials, and the like of the conductive semiconductor substrate 50b are as described in the first embodiment. In the third embodiment, n-type Si having a specific resistance of 0.02 Ωcm is used as the conductive semiconductor substrate 50b.

The range of the specific resistance of the conductive oxide film 11b and preferred materials are the same as those in the first embodiment. The preferable impurity concentration and the like of the nitride-based semiconductor thin film 12b are also as described in the first embodiment. In the third embodiment, Nb-added TiO ₂ having a specific resistance of 3 × 10 ⁻⁴ Ωcm is used as the conductive oxide film 11b. Further, n ⁺ -GaN having an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ and a film thickness of 0.1 μm was used as the nitride-based semiconductor thin film 12b.

In the stacked body 20b, a drift layer 13b, a barrier layer 17, a channel layer 14b, and an electron supply layer 18 heterojunction with the channel layer 14b are stacked in this order. The drift layer 13b has an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ and a film thickness of 4 μm, n ⁻ -GaN, and the barrier layer 17 has an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ and a film thickness of 0. .5 μm p-GaN was used. The channel layer 14b was made of non-doped GaN having a thickness of 50 nm, and the electron supply layer 18 was made of non-doped Al _0.2 Ga _0.8 N having a thickness of 30 nm.

On the surface of the electron supply layer 18, a source electrode 52b made of Ti / Al and a gate electrode 51b made of Ni / Au are formed. Further, an n ⁺ -type region 19 having an impurity concentration of 3 × 10 ¹⁸ cm ⁻³ that functions as an electron conduction region is formed on the side where the source electrode 52 b is not opposed to the gate electrode 51 b. The n ⁺ -type region 19 functioning as an electron conducting region is formed in a region extending from at least a substantial surface of the channel layer 14b to a region closer to the nitride-based semiconductor thin film 12b side than the barrier layer 17. ing. The n ⁺ -type region 19 according to the third embodiment is formed in a region that reaches a partial region of the drift layer 13b from the surface of the channel layer 14b. The n ⁺ -type region 19 may be formed in a region extending from the surface of the electron supply layer 18 to a region closer to the nitride-based semiconductor thin film 12b side than the barrier layer 17. A part of the conductive semiconductor substrate 50b is formed with a back side trench 23 that reaches the conductive oxide film 11b from the back side, and covers the back side of the conductive semiconductor substrate 50b and the inner wall of the back side trench 23. A drain electrode 53b made of Al is formed.

  The vertical transistor according to the third embodiment is a so-called high electron mobility transistor (HEMT: High) that uses a two-dimensional electron gas 25 accumulated by a polarization effect as a channel near the interface between the channel layer 14b and the electron supply layer 18. Electron Mobility Transistor).

  Next, an example of a method for manufacturing a vertical transistor according to Embodiment 3 will be described with reference to FIGS. 6A to 6C. 6A to 6C are cross-sectional views schematically showing the manufacturing process of the vertical transistor according to the third embodiment.

First, in the same manner as in the first embodiment, a substrate in which the conductive oxide film 11b and the nitride semiconductor thin film 12b are bonded to the conductive semiconductor substrate 50b is manufactured (FIG. 6A). The only difference from the first embodiment is the difference in material in which Nb-added TiO ₂ is used for the conductive oxide film 11b. As a manufacturing method, a bonded substrate can be produced in exactly the same manner as in FIGS. 2A to 2C. .

Next, a stacked body 20b is obtained on the nitride-based semiconductor thin film 12b by using a metal organic chemical vapor deposition method. Specifically, a drift layer 13b made of n ⁻ -GaN having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ and a film thickness of 4 μm, and an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ and a film thickness of 0.5 μm. A barrier layer 17 made of p-GaN, a channel layer 14b made of non-doped GaN having a thickness of 50 nm, and an electron supply layer 18 made of non-doped Al _0.2 Ga _0.8 N having a thickness of 30 nm are grown. Next, by using selective ion implantation, Si ions are implanted into a part of the stacked body 20 b to form the n ⁺ -type region layer 19. Thereafter, a 300 nm SiO ₂ film is formed as a protective film (not shown) on the surface of the stacked body 20b, and then heat treatment is performed at 1250 ° C. for 60 seconds. Thereby, the implanted ions are activated. Thereafter, the protective film is removed with buffered hydrofluoric acid (FIG. 6B).

  Subsequently, the source electrode 52 b is formed on the electron supply layer 18. Specifically, a Ti / Al (30 nm / 180 nm) electrode pattern is formed on the electron supply layer by using a photoresist mask having an opening pattern in a region where the source electrode 52b is formed, and using an evaporation / lift-off method. 18 is formed at a predetermined position on the surface. Thereafter, RTA is performed at 700 ° C. for 60 seconds to obtain the source electrode 52b.

  Next, the gate electrode 51b is formed on the electron supply layer 18 at a position separated from the source electrode 52b. Specifically, using a photoresist mask in which an opening pattern is formed in a region where the gate electrode 51b is to be formed, a Ni / Al (30 nm / 300 nm) electrode pattern is formed on the electron supply layer by vapor deposition / lift-off method. 18 is formed at a predetermined position on the surface (FIG. 6C).

  Next, a drain electrode is formed on the back side of the conductive semiconductor substrate 50b. Specifically, after polishing and thinning the back surface of the conductive semiconductor substrate 50b, using a photoresist mask in which an opening pattern is formed at a predetermined position, using a RIE (Reactive Ion Etching) method, A back side trench 23 reaching the conductive oxide film 11b from the back side of the conductive semiconductor substrate 50b is formed. Next, a vertical electrode having the configuration of FIG. 5 is formed by forming a drain electrode 53b made of Ti / Al so as to cover the back surface of the conductive semiconductor substrate 50b and the inner wall of the back surface side trench 23 by using a vacuum evaporation method. Complete 3

  According to the vertical transistor 3, a so-called high electron mobility transistor using a two-dimensional electron gas 25 accumulated by polarization charge as a channel at the interface between the channel layer 14b and the electron supply layer 18 is manufactured.

In the third embodiment, since the conductive oxide film 11b having a specific resistance of 3 × 10 ⁻⁴ Ωcm or less (specific example: 3 × 10 ⁻⁴ Ωcm) is used, the conductive oxide film 11b and the conductive semiconductor substrate are used. Bonding can be performed without generating large interface resistance at the interface with 50b. For the same reason, a junction can be formed without generating a large interface resistance at the interface between the conductive oxide film 11b and the nitride-based semiconductor thin film 12b.

Moreover, since the conductive oxide film 11b is made of a material having a band gap of Nb-added TiO ₂ close to that of GaN (TiO ₂ : 3.2 eV, GaN: 3.4 eV), the conductive oxide film 11b and the nitride system are used. The interface resistance at the interface with the semiconductor thin film 12b can be particularly lowered. Further, in the third embodiment, the back side trench 23 reaching the conductive oxide film 11b from the back side is formed in a part of the conductive semiconductor substrate 50b, and the drain electrode 53b is in direct contact with the conductive oxide film 11b. Is formed. Thereby, the interface resistance caused by the band gap difference between the conductive semiconductor substrate 50b made of n-type Si and the conductive oxide film 11b made of Nb-added TiO ₂ can be made almost zero. Due to the above-described effects, the vertical transistor according to the third embodiment has an on-resistance that is approximately several times higher than that of a high electron mobility transistor using a nitride-based semiconductor manufactured using a conventional low-cost bonding technique. It can be reduced from 10% to about half.

  In the vertical transistor according to the third embodiment, a back-side trench 23 reaching the conductive oxide film 11b is formed in a part of the conductive semiconductor substrate 50b. In this case, the drain electrode 53b or the collector electrode is preferably formed so as to contact not only the back surface of the conductive semiconductor substrate 50b but also the side surface and the bottom surface of the back surface side trench 23. With such a configuration, the interface resistance at the interface of the conductive semiconductor substrate 50b / conductive oxide film 11b can be reduced, and a vertical transistor having a lower on-resistance can be realized.

As described above, the first to third embodiments have been described as specific examples of the present invention. However, the materials and manufacturing processes shown in the first to third embodiments are merely examples, and are not limited thereto. is not. Although a GaN-based example has been described as the nitride-based semiconductor, the present invention can also be applied to nitride-based semiconductors such as AlGaN, InGaN, InAlN, and InAlGaN. As the gate insulating films 16 and 16a, not only SiO ₂ and Al ₂ O ₃ but also SiN, SiON, AlN, MgO, Sc ₂ O ₃ , ZrO ₂ , HfO ₂ , or a stacked structure thereof can be used. Further, a MIS gate structure can be formed by providing a gate insulating film between the electron supply layer 18 and the gate electrode 51b.

  In the first to third embodiments, the structures can be freely combined. For example, each channel structure shown in the first to third embodiments is not limited to this, and each channel structure can be applied to other embodiments. For example, a trench gate type IGBT can be manufactured by applying the trench gate type channel described in the first embodiment to the second embodiment. Further, the HEMT type channel shown in the third embodiment can be applied to the first embodiment. Furthermore, the configuration in which the back-side trench 23 reaching the conductive oxide film 11b from the back surface is formed in a part of the conductive semiconductor substrate 50b shown in the third embodiment is applicable to the first and second embodiments.

Further, the structure such as the number of layers, the thickness, and the composition of the laminated body obtained by epitaxially growing the nitride-based semiconductor is not limited to the structures described in the first to third embodiments. For example, in the second embodiment, the example in which the drift layer 13a made of n ⁻ -GaN is grown on the nitride semiconductor thin film 12a made of p ⁺ -GaN obtained by bonding has been described. However, if it is difficult to obtain a good pn junction when the epitaxial growth start interface and the pn junction interface coincide with each other, the p ⁺ -GaN layer is epitaxially grown before the growth of the drift layer 13a, and then the drift layer made of n ⁻ -GaN 13a may be grown. Thereby, the epitaxial growth start interface and the pn junction interface can be located at different positions. Thus, the laminated body obtained by epitaxial growth can be used by freely combining the number of layers, thickness, composition, etc., as long as nitride semiconductors are laminated.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the invention.

  A part or all of the above embodiment can be described as in the following supplementary notes, but is not limited to the following.

(Supplementary Note 1) Impurities formed by bonding a conductive semiconductor substrate, a conductive oxide film having a specific resistance of 3 × 10 ⁻⁴ Ωcm or less formed on the surface of the conductive semiconductor substrate, and the conductive oxide film An n ⁺ -type or p ⁺ -type nitride-based semiconductor thin film having a concentration of 5 × 10 ¹⁷ cm ⁻³ or more, a laminate composed of a nitride-based semiconductor epitaxially grown on the nitride-based semiconductor thin film, A source electrode or emitter electrode formed on the surface of the laminate, a drain electrode or collector electrode formed on the back surface of the conductive semiconductor substrate, and between the source electrode and the drain electrode or between the emitter electrode and the A vertical transistor comprising a gate electrode having a function of controlling a magnitude of a current flowing between the collector electrode.

(Additional remark 2) Melting | fusing point of the said conductive oxide film is 1300 degreeC or more, The vertical transistor of Additional remark 1 characterized by the above-mentioned.

(Supplementary note 3) The vertical transistor according to Supplementary note 1 or 2, wherein a band gap of the conductive oxide film is 2.8 eV or more and 4.0 eV or less.

(Supplementary note 4) Any one of Supplementary notes 1 to 3, wherein the conductive oxide film is any one of ITO, ZnO, TiO ₂ , SnO ₂ , CdO, or a metal impurity added thereto. The vertical transistor as described.

(Supplementary note 5) The vertical transistor according to any one of supplementary notes 1 to 4, wherein the conductive semiconductor substrate is made of any one of Si, poly-Si, and poly-SiC.

(Additional remark 6) The back surface side trench which reaches the said conductive oxide film from the back surface is formed in a part of said conductive semiconductor substrate, The said drain electrode or the said collector electrode is a back surface of the said conductive semiconductor substrate. The vertical transistor according to any one of appendices 1 to 5, wherein the vertical transistor is formed so as to cover the inner wall of the backside trench.

(Additional remark 7) The laminated body which consists of the said nitride-type semiconductor was formed in the drift layer formed on the said nitride-type semiconductor thin film, the barrier layer formed on the said drift layer, and the said barrier layer A channel layer; and an electron supply layer heterojunctioned on the channel layer, wherein the gate electrode is formed on the stacked body so as to be opposed to the source electrode with a gap, and the gate The electrode extends to the side where the source electrode is not opposed to the electrode, at least from the substantial surface of the channel layer to a region closer to the nitride-based semiconductor thin film side than the barrier layer. The vertical transistor according to any one of appendices 1 to 6, further comprising an electron conduction region.

(Appendix 8) The vertical transistor according to any one of appendices 1 to 7, wherein the conductive oxide film has a thickness of 5 nm or more and 1000 nm or less.

(Supplementary note 9) The vertical transistor according to any one of supplementary notes 1 to 8, wherein the conductive oxide film has a thickness of 10 nm to 500 nm.

(Supplementary note 10) The vertical transistor according to any one of supplementary notes 1 to 9, wherein the conductive oxide film has a thickness of 20 nm to 300 nm.

(Appendix 11) The nitride semiconductor thin film according to any one of Appendices 1 to 10, wherein the impurity concentration is 1 × 10 ¹⁸ cm ⁻³ or more and 5 × 10 ²⁰ cm ⁻³ or less. Vertical transistor.

(Appendix 12) A conductive oxide film is formed on a conductive semiconductor substrate, a nitride semiconductor thin film is formed on the conductive oxide film, and a nitride semiconductor is formed on the nitride semiconductor thin film. A method of manufacturing a vertical transistor, comprising: epitaxially growing a laminate comprising: forming a source electrode or an emitter electrode on a surface of the laminate; and forming a drain electrode or a collector electrode on a back surface of the conductive semiconductor substrate.

(Appendix 13) The nitride-based semiconductor thin film is obtained by bonding a nitride-based semiconductor bulk crystal on the conductive oxide film and dividing the nitride-based semiconductor bulk crystal in the thickness direction. The manufacturing method of the vertical transistor as described in appendix 12.

(Supplementary Note 14) A semiconductor device including a vertical transistor, the semiconductor device including the vertical transistor according to any one of Supplementary Notes 1 to 11 as the vertical transistor.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2009-165358 for which it applied on July 14, 2009, and takes in those the indications of all here.

  A vertical transistor using a nitride-based semiconductor according to the present invention has a structure that can realize low on-resistance at low cost and reduce power consumption. Utilizing these advantages, it can be applied to a transistor used in a power control device such as a PC power supply or an automobile power steering.

1 to 3 Vertical transistor 11 Conductive oxide film 12 Nitride-based semiconductor thin film 13 Drift layer 14 Channel layer 15 Contact layer 16 Insulating film 17 Barrier layer 18 Electron supply layer 19 n ⁺ type region 20 Stack 21 Upper surface side trench 23 Back surface Side trench 25 Two-dimensional electron gas 30 Nitride semiconductor bulk crystal 50 Conductive semiconductor substrate 51 Gate electrode 52 Source electrode 53 Drain electrode 55 Emitter electrode 56 Collector electrode

Claims (10)

A conductive semiconductor substrate;
A conductive oxide film formed on the surface of the conductive semiconductor substrate and having a specific resistance of 3 × 10 ⁻⁴ Ωcm or less;
An n ⁺ -type or p ⁺ -type nitride-based semiconductor thin film having an impurity concentration of 5 × 10 ¹⁷ cm ⁻³ or more, which is bonded to the conductive oxide film;
A laminate made of a nitride semiconductor epitaxially grown on the nitride semiconductor thin film;
A source electrode or an emitter electrode formed on the surface of the laminate,
A drain electrode formed on the back surface of the conductive semiconductor substrate, or a collector electrode;
A vertical transistor comprising a gate electrode having a function of controlling a magnitude of a current flowing between the source electrode and the drain electrode or between the emitter electrode and the collector electrode.   The vertical transistor according to claim 1, wherein the conductive oxide film has a melting point of 1300 ° C or higher.   3. The vertical transistor according to claim 1, wherein a band gap of the conductive oxide film is 2.8 eV or more and 4.0 eV or less. 4. The conductive oxide film according to claim 1, wherein the conductive oxide film is any one of ITO, ZnO, TiO ₂ , SnO ₂ , CdO, or a metal impurity added thereto. Vertical transistor.   5. The vertical transistor according to claim 1, wherein the conductive semiconductor substrate is made of any one of Si, poly-Si, and poly-SiC. A back side trench reaching the conductive oxide film from the back side is formed in a part of the conductive semiconductor substrate,
The said drain electrode or the said collector electrode is formed so that the back surface of the said conductive semiconductor substrate and the inner wall of the said back surface side trench may be covered. Vertical transistor. The laminate composed of the nitride-based semiconductor includes a drift layer formed on the nitride-based semiconductor thin film, a barrier layer formed on the drift layer, a channel layer formed on the barrier layer, An electron supply layer heterojunction on the channel layer,
The gate electrode is formed on the stacked body so as to be opposed to the source electrode with a gap,
With respect to the gate electrode, the source electrode is disposed on the side not opposed, and upper surface immediately below the electron supply layer, or is formed so as to be located on the surface and the same surface of the electron supply layer, The vertical transistor according to any one of claims 1 to 6, further comprising an electron conduction region formed at a position where a lower surface reaches the drift layer . On the conductive semiconductor substrate, a conductive oxide film having a specific resistance of 3 × 10 ⁻⁴ Ωcm or less is formed,
On the conductive oxide film, it is formed by the impurity concentration of 5 × ¹⁰ 17 ^{cm -3} or more ^{n +} type, or bonding a ^{p +} -type nitride semiconductor thin film,
A laminate composed of a nitride-based semiconductor is epitaxially grown on the nitride-based semiconductor thin film,
Forming a source electrode or an emitter electrode on the surface of the laminate;
A method of manufacturing a vertical transistor, wherein a drain electrode or a collector electrode is formed on the back surface of the conductive semiconductor substrate. The nitride-based semiconductor thin film is bonded to a nitride-based semiconductor bulk crystal on the conductive oxide film,
The vertical transistor manufacturing method according to claim 8, wherein the nitride-based semiconductor bulk crystal is obtained by dividing the nitride-based semiconductor bulk crystal in a thickness direction.   A semiconductor device having a vertical transistor mounted thereon, wherein the semiconductor device includes the vertical transistor according to claim 1 as the vertical transistor.

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