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TWI676409B - 用於製造電子模組的方法及電子模組 - Google Patents

用於製造電子模組的方法及電子模組 Download PDF

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Publication number
TWI676409B
TWI676409B TW104142111A TW104142111A TWI676409B TW I676409 B TWI676409 B TW I676409B TW 104142111 A TW104142111 A TW 104142111A TW 104142111 A TW104142111 A TW 104142111A TW I676409 B TWI676409 B TW I676409B
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TW
Taiwan
Prior art keywords
layer
insulating material
electronic module
conductive
photoresist layer
Prior art date
Application number
TW104142111A
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English (en)
Other versions
TW201633860A (zh
Inventor
瑞斯圖 圖奧米恩
Risto Tuominen
Original Assignee
芬蘭商奇異嵌入式電子公司
Ge Embedded Electronics Oy
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Application filed by 芬蘭商奇異嵌入式電子公司, Ge Embedded Electronics Oy filed Critical 芬蘭商奇異嵌入式電子公司
Publication of TW201633860A publication Critical patent/TW201633860A/zh
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Publication of TWI676409B publication Critical patent/TWI676409B/zh

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Abstract

本發明關於一種具有至少一元件嵌入於絕緣材料中的電子模組。電子模組包含第一絕緣材料，其具有第一表面及第二表面及第一表面與第二表面之間的厚度，至少一開孔通過第一絕緣材料，其第二絕緣材料，其設於第一絕緣材料之第二表面上，至少一元件，其嵌入於第二絕緣材料中，至少一導電圖案，其設於至少一開孔中，至少一導電圖案具有第一表面及第二表面，其中，第二表面面向第二絕緣材料且第一表面背向第二絕緣材料，及第一絕緣材料之第一表面與至少一導電圖案之第二表面之間的距離係小於或大於第一絕緣材料之厚度，黏合劑，其設於第一絕緣材料與至少一元件之間，及連接元件，設於至少一導電圖案與至少一元件之間。本發明進一步關於一種用於製造電子模組的方法，電子模組具有至少一元件嵌入於絕緣層中。

Description

用於製造電子模組的方法及電子模組
本發明關於一種用於製造電子模組的方法，電子模組具有至少一元件嵌入於絕緣層中。此解決方式另可稱為電路板或模組結構，其含有埋入、嵌入或內建元件。圍繞於元件之絕緣材料層典型上為一電路板或模組結構之基本結構的一部分，其形成對於電路板或模組之最內側導電層的支撐。
本發明進一步關於一種電子模組。特別是，本發明關於一種電子模組，其包括至少一元件嵌入於一絕緣層中。電子模組可以是模組狀電路板，其包括多數個元件，元件經過在模組中製成之導電結構而彼此電連接。元件可以是被動元件、微電路、半導體元件、或元件之任意其他類型。
用於製造含有元件之電子模組或電路板結構之許多方法已屬習知。例如，美國專利5,936,847號揭露一用於將安裝及互連電子元件至基板之電路模組構造，其 可用於安裝各式各樣電子元件及導體，包括倒裝或覆晶安裝之積體電路。元件藉由一夾層式非導電性聚合物層安裝於基板，聚合物層有如黏結劑及填充膠。基板及填充膠具有和基板上之信號跡線及元件接觸點對齊的孔口，且導電性聚合物注入通過孔口，以填充基板接觸點與元件接觸點之間的區域，以確保良好的電氣連接。在一實施例中，非導電性聚合物印製在具有間隙以供接觸的基板接觸側上。在另一實施例中，在形成接觸孔及元件安裝之前，B階段非導電性聚合物塗布於基板之非接觸側上。導電性聚合物隨後注入孔口內，以形成電氣連接，並將組件固化。元件之塗布或預先處理則不需要。
此外，美國專利6,038,133號揭露一電路元件內建模組，包括一絕緣基板，絕緣基板是由包含70重量百分比至95重量百分比之無機填料及熱固性樹脂的混合物形成；複數個配線圖案，形成於絕緣基板之至少一主平面上；一電路元件，配置於絕緣基板之一內部件中且電連接於配線圖案；及一內通孔，形成於絕緣基板中，用以電連接於複數個配線圖案。因此，可以取得一具有高密度電路元件之高穩定性電路元件內建模組。
此外，美國專利6,350,633號進一步揭露一半導體晶片組件，包括一附接於一支撐電路之半導體晶片。支撐電路包括一絕緣基座、一導電跡線及一設在其頂與底表面之間的貫穿孔。貫穿孔包括一相鄰於頂表面之頂側壁部及一相鄰於底表面之底側壁部。導電跡線包括一設在頂 表面之導柱及一設在底側壁部之路由線。導柱上之一電鍍接觸端點延伸於基座上，且貫穿孔中之一電鍍連接點接觸路由線與墊片。較佳為，連接點為貫穿孔中唯一的金屬。製造組件的方法包括同時電鍍接觸端點與連接點。
美國專利申請案US 2002/0117743 A1號進一步揭述一元件內建模組，包括一由電絕緣材料形成之芯層、及形成於芯層之至少一表面上的一電絕緣層與複數個配線圖案。芯層之電絕緣材料係由一包括至少一無機填料及一熱固性樹脂的混合物形成。主動元件及/或被動元件的至少其中一個容置於芯層之一內部件中。芯層具有複數個配線圖案及由導電樹脂形成之複數內通孔。由包括有至少一無機填料及芯層之一熱固性樹脂的混合物形成之電絕緣材料在室溫下具有0.6GPa至10Gpa範圍內的彈性係數。因此，其可提供一熱傳導性元件內建模組，可以高密度填充無機填料、將主動元件(像是半導體)及被動元件(像是晶片電阻器、晶片電容器、等等)嵌入在基板之內部件中、及方便產生一多層式配線結構。
美國專利8,240,033號揭露一製造電路板結構之方法。根據此方法，製成一導體圖案及在其中製成一接觸開孔，用於元件之電接觸。隨後，元件相對於導體圖案附接，依此使元件之接觸區域或接觸凸塊相鄰於接觸開孔。隨後，導電材料被導送到接觸開孔，以利形成導體圖案與元件之間的電接觸。
此外，美國專利US 8,581,109號揭露一用於 製造電路板結構之方法。在此方法中，製成一導體層，其包含一導體箔片及一設於導體箔片表面上之導體圖案。一元件附接於導體層，且導體層之至少一些導體材料是從導體圖案外移除。
美國專利US 5,407,864號揭述一製造半導體晶片之方法，半導體晶片具有一連接墊片且連接於一電路板之前側，電路板具有一連接於貫穿孔之導電跡線。一絕緣黏合劑層(具有一相對應於墊片之孔)介置於晶片與電路板之間，使得墊片、絕緣層中之孔及電路板中之貫穿孔對準。一導電材料從電路板之後側施加到貫穿孔中，以利填注貫穿孔且連接墊片至跡線。導電材料可以使用濺鍍法、屏蔽琺、電鍍法或蒸鍍法施加。電路板之後側係經拋光以移除可能施加於貫穿孔外之電路板後側上的導電材料。
本發明之特定實施例之一目的在提供一種製造電子模組的方法，電子模組具有至少一元件嵌入於一絕緣層中。本發明之特定實施例之另一目的在提供一種電子模組。特別是，本發明之特定實施例之又一目的在提供一種電子模組，其包括嵌入於一絕緣層中之至少一元件。本發明之特定實施例之再一目的在提供一種電子模組，其包括嵌入於一絕緣層中之複數個互連元件。
上述及其他目的係藉由本發明之實施例達成，如文後及申請專利範圍所述。根據一態樣，本發明關 於一種製造電子模組之方法，方法包含：提供光阻劑層，光阻劑層具有第一表面及第二表面及第一表面與第二表面之間的厚度，提供至少一開孔通過光阻劑層，提供絕緣材料於光阻劑層之第二表面上，及至少一元件嵌入於絕緣材料中，提供至少一導電圖案於至少一開孔中，以致使至少一導電圖案具有第一表面及第二表面，其中，第二表面面向絕緣材料且第一表面背向絕緣材料，及光阻劑層之第一表面與至少一導電圖案之第二表面之間的距離係小於或大於光阻劑層之厚度，及提供至少一導電圖案與至少一元件之間的連接元件。
根據另一態樣，本實施例之目的也可以藉由一種用於製造電子模組的方法達成，電子模組具有至少一元件嵌入於絕緣材料中，方法包含以下步驟：a)配置剝離層於導電箔片之第一表面上，b)配置具有圖案及/或通孔之第一光阻劑層於剝離層之頂面上且生長導電材料，第一光阻劑層的厚度大於或小於在生長的導電材料的厚度，c)配置黏合劑層於光阻劑層與在生長的導電材料之頂面上或部分頂面上，或具有接觸區之至少一元件之接觸表面上，d)放置至少一元件，使接觸表面面向光阻劑層之第二表面，且接觸區之位置與通孔之位置重合， e)配置絕緣層，使至少一元件嵌入於絕緣層中，f)移除導電箔片及剝離層，及g)從通孔移除材料，因此形成通孔，及生長導電材料於通孔中。
根據一實施例，附加之聚合物層係形成於第一光阻劑層與黏合劑之間。
根據另一實施例，具有圖案及通孔之第二光阻劑層係在步驟b)之後配置，使第二光阻劑層之第一表面面向第一光阻劑層且生長導電材料，第二光阻劑層的厚度大於或小於在生長的導電材料的厚度。根據特定實施例，在配置第二光阻劑層後，附加之聚合物層可形成於第二光阻劑層之第二表面與黏合劑之間。
根據一實施例，導電層及/或該電子模組之下導電表面係經移除，所以便導電材料生長於通孔中之後曝露導電圖案。
根據本發明之一態樣，其提供一種電子模組，包含：第一絕緣材料，具有第一表面及第二表面及第一表面與第二表面之間的厚度，至少一開孔通過第一絕緣材料，第二絕緣材料，設於第一絕緣材料之第二表面上，至少一元件，嵌入於第二絕緣材料中，至少一導電圖案，設於至少一開孔中，至少一導電圖案具有第一表面及第二表面，其中，第二表面面向第二絕 緣材料且第一表面背向第二絕緣材料，及第一絕緣材料之第一表面與至少一導電圖案之第二表面之間的距離係小於第一絕緣材料之厚度或大於第一絕緣材料之厚度，及連接元件，設於至少一導電圖案與至少一元件之間。
在一實施例中，連接元件包含積置於絕緣材料之通孔中的導電材料。在另一實施例中，第二表面上的第二絕緣材料包含設於第一絕緣材料與至少一元件之間的絕緣層，像是黏合劑層、聚合物層或不同於第二絕緣材料之任意其他材料。聚合物層配置於第一絕緣材料之第二表面、黏合劑及/或面向第一絕緣材料的絕緣層表面之間。
在一實施例中，第一絕緣材料之第一表面與至少一導電圖案之第一表面之間的距離係大於零。
在一實施例中，從至少一導電圖案之第二表面延伸至元件之至少一接觸區之接觸表面的至少一通孔的長寬比係小於2.0、小於1.0、小於0.75、小於0.5、小於0.4、或小於0.3。在本案中，長寬比係定義成通孔之高度對直徑的比率(=h/d)。
在一實施例中，至少一導電圖案配置於第二絕緣材料之頂面上。
在一實施例中，至少一元件係被動元件、微電路、半導體元件、或任意其他類型之元件。
藉由本發明之實施例可以取得可觀之優點。一種具有至少一元件嵌入於一絕緣層中的電子模組可以根據本發明之特定實施例製成。藉由本發明，可以建立一高 接觸密度之模組。電子模組之諸層極薄，因此產生一薄型模組。製造方法容許使用通孔法達成電接觸。例如，接觸可以藉由化學或電化學生長法達成，在此情況中，可以針對導電圖案與元件之間的接觸達成優異之電氣性。也可以先藉由化學方法生長一薄層，接著使用較廉價之電化學法繼續生長。成本效益之製造方法改善了電子模組之品質及提供較佳的良率。
關於圖案之通孔對準可以在附接元件或繼續製程之前先進一步檢查。因此可以避免將昂貴元件黏接到不必要位置。再者，圖案在元件組裝成即完成及檢查，所以可避免將元件組裝到缺陷之圖案。
1‧‧‧電子模組
2‧‧‧金屬箔片
3‧‧‧剝離層
4‧‧‧第一光阻劑層
5‧‧‧通孔
6‧‧‧第二光阻劑層
7‧‧‧黏合劑
8‧‧‧元件
9‧‧‧接觸表面
10‧‧‧接觸區
11‧‧‧絕緣層
12‧‧‧導電層
13‧‧‧通孔
14‧‧‧下導電表面
15‧‧‧導電圖案
16‧‧‧導電層之導電圖案
17‧‧‧聚合物層
18‧‧‧第一或第二光阻劑層之第一表面
19‧‧‧第一或第二光阻劑層之第二表面
20‧‧‧導電圖案之第一表面
21‧‧‧導電圖案之第二表面
101‧‧‧電子模組
106‧‧‧第一絕緣材料層
107‧‧‧黏合劑層
108‧‧‧元件
109‧‧‧接觸表面
110‧‧‧接觸區
111‧‧‧第二絕緣材料層
113‧‧‧通孔
115‧‧‧導電圖案層
116‧‧‧導電層或導電圖案層
118‧‧‧第一絕緣材料層之第一表面
119‧‧‧第一絕緣材料層之第二表面
120‧‧‧導電圖案層之第一表面
121‧‧‧導電圖案層之第二表面
d1‧‧‧距離
d2‧‧‧距離
d3‧‧‧距離
d4‧‧‧距離
dvia‧‧‧距離
ha‧‧‧黏合劑層之厚度
hp‧‧‧導電圖案之厚度
hr‧‧‧光阻劑層之厚度
為了對本發明特殊實施例及其優點的徹底瞭解，請即參考連同附圖在內之以下說明。圖式中：圖1揭示根據第一實施例之電子模組之第一製造步驟之示意圖，圖2揭示根據第一實施例之電子模組之第二製造步驟之示意圖，圖3揭示根據第一實施例之電子模組之第三製造步驟之示意圖，圖4揭示根據第一實施例之電子模組之第四製造步驟之示意圖，圖5揭示根據第一實施例之電子模組之第五 製造步驟之示意圖，圖6揭示根據第一實施例之電子模組之第六製造步驟之示意圖，圖7揭示根據第一實施例之電子模組之第七製造步驟之示意圖，圖8揭示根據第一實施例之電子模組之第八製造步驟之示意圖，圖9揭示根據第一實施例之電子模組之第九製造步驟之示意圖，圖10揭示根據第一實施例之電子模組之第十製造步驟之示意圖，圖11揭示根據第二實施例之電子模組之第一製造步驟之示意圖，圖12揭示根據第二實施例之電子模組之第二製造步驟之示意圖，圖13揭示根據第二實施例之電子模組之第三製造步驟之示意圖，圖14揭示根據第二實施例之電子模組之第四製造步驟之示意圖，圖15揭示根據第二實施例之電子模組之第五製造步驟之示意圖，圖16揭示根據第二實施例之電子模組之第六製造步驟之示意圖，圖17揭示根據第二實施例之電子模組之第七 製造步驟之示意圖，圖18揭示根據第二實施例之電子模組之第八製造步驟之示意圖，圖19揭示根據第二實施例之電子模組之第九製造步驟之示意圖，圖20揭示根據第二實施例之電子模組之第十製造步驟之示意圖，圖21揭示根據第三實施例之電子模組之第一製造步驟之示意圖，圖22揭示根據第三實施例之電子模組之第二製造步驟之示意圖，圖23揭示根據第三實施例之電子模組之第三製造步驟之示意圖，圖24揭示根據第三實施例之電子模組之第四製造步驟之示意圖，圖25揭示根據第三實施例之電子模組之第五製造步驟之示意圖，圖26揭示根據第三實施例之電子模組之第六製造步驟之示意圖，圖27揭示根據第三實施例之電子模組之第七製造步驟之示意圖，圖28揭示根據第三實施例之電子模組之第八製造步驟之示意圖，圖29揭示根據第四實施例之電子模組之示意 圖，及圖30揭示根據第五實施例之電子模組之示意圖。
在圖1、圖11及圖21中，揭示根據本發明第一、第二或第三實施例之電子模組1之第一製造步驟之示意圖。在此第一製造步驟中，一導電剝離層3配置於一導電箔片2之頂面上。導電箔片2例如可由銅構成。導電箔片2及剝離層3形成一載體，用於一電子模組1之後續製造過程之步驟。導電剝離層3及導電箔片2之導電性應在製造方法之後續步驟中將電解生長所需之電流導送到供導電材料生長於其中的區域。
在圖2及圖12中，揭示根據本發明第一或第二實施例之電子模組1之第二製造步驟之示意圖。一形成通孔5之第一光阻劑層4配置於剝離層3之頂面上。接著進行導電材料之生長，例如銅、鋁、鋅、鎳、金、鈦或鐵，或是上述金屬之二或多個的組合，使第一光阻劑層4之厚度小於或大於所生長導電材料之厚度。電解生長一層導電材料是在已移除光阻劑或尚未施加光阻劑之區域中進行。
在圖3中，揭示根據本發明第一實施例之電子模組1之第三製造步驟之示意圖。一形成圖案及通孔5之第二光阻劑層6配置使得第二光阻劑層6之第一表面 18面向第一光阻劑層4。第二光阻劑層6之通孔5配置使其位置與第一光阻劑層4之通孔5之位置重合。因此，第一及第二光阻劑層4、6之通孔5形成合併之通孔5。導電材料之生長即依此方式進行，使第二光阻劑層6之厚度小於或大於所生長導電材料之厚度。導電材料不必然需要和第二製造步驟中所用者相同，但是也可以是其他替代型式或組合的其中之一。在製造方法之一後續階段，通孔5中之材料例如藉由電漿蝕刻或雷射剝蝕移除。第二光阻劑層6之剩餘部分將永久含括在電子模組1中。一通孔5係針對用於形成電接觸之各接觸區域而設。所設通孔5之表面積可以大致和相對應接觸區10之表面積一樣大。當然，通孔5之表面積也可以選擇成較小，或者，在一些實施例中，略大於相對應接觸區10之表面積。合併通孔5之對準可以在附接元件8、或繼續製程之前先進一步檢查。合併通孔5之對準檢查例如可以使用2D或3D測量系統或X射線測量系統進行，用於測量合併通孔5之位置。藉由一電子計算裝置之助，一測量信號或測量值可以對照各參考信號或各參考值來檢查，且測量信號或測量值可以根據界定之容差值分類成「OK」或「not OK」。
在圖4中，揭示根據本發明第一實施例之電子模組1之第四製造步驟之示意圖。一黏合劑層7施加於第二光阻劑層6及所生長導電材料之頂面上。黏合劑也可以成階級狀及層狀散布。黏合劑7可以僅局部施加於元件之區域中或涵蓋在整個表面上。根據特定實施例，其並不 需要各別黏合劑且元件可以直接附接於導電材料。在此情況中，當在一後續階段製成絕緣層11時，元件與導電材料之間的所有空置空間皆填滿。在一些特定實施例中，黏合劑較佳為充分散布於第二光阻劑層6之第二表面19及所生長導電材料上，使黏合劑填滿元件8與第二光阻劑層6之間剩餘的所有空間。黏合劑一詞係指可藉其使元件8附接於光阻劑層6與導電材料的材料。實施例中所用之黏合劑7例如可以是環氧樹脂。黏合劑層7之厚度例如在2μm與20μm之間的範圍內，像是在5μm與15μm之間。所用之黏合劑7依此選擇，使得所用之黏合劑充分黏合於光阻劑層6與導電材料以及元件8。黏合劑7之一有利性質為適當熱膨脹係數，所以在製程期間黏合劑之熱膨脹不致與周圍材料之熱膨脹差異過大。根據特定實施例，所選之黏合劑有短硬化時間，像是最多幾秒。根據另一特定實施例，黏合劑7在此時間內至少部分硬化，使黏合劑7可以將元件8固持定位。最後的硬化明顯花費較多時間且最後的硬化甚至可以規畫進行相關聯於後續之製程階段。典型上，黏合材料為電絕緣材料。根據特定實施例，黏合劑7之導電率係與絕緣層11之絕緣材料之導電率相同等級。根據另一特定實施例，所用之黏合劑7有其他介電性，像是不同於在後續階段製或的絕緣層11之鑿穿強度或介電常數。
在圖5中，揭示根據本發明第一實施例之電子模組1之第五製造步驟之示意圖。四元件8(像是被動 元件、微電路、半導體元件、或元件之任意其他類型，其具有一接觸表面9，接觸表面具有接觸區10)放置於黏合劑層上，且例如藉由塗膠來附接，使四元件8之接觸表面9面向第二光阻劑層6之第二表面19，且元件之接觸區10之位置與合併通孔5之位置重合。元件8可以在一或兩側上設有接觸區10。元件8之接觸區10例如可以是接觸表面9上之平坦區域或較常接觸之凸起(像是從元件8之接觸表面9凸出之接觸凸塊)。接觸區10也可以設在元件8之表面中的凹陷底部上。在元件8中通常有至少兩接觸區10或凸起。在複雜之微電路中，可以設有許多接觸區10。元件8之附接可以使用多項技藝且在一或多個階段中執行。元件8例如可以使用一適當之覆晶安裝裝置附接於黏合劑層7上。隨後，黏合劑7容許硬化(至少部分)，或者黏合劑主動硬化(至少部分)，使元件藉由黏合劑7附接於電子模組1。
在圖6中，揭示根據本發明第一實施例之電子模組1之第六製造步驟之示意圖。一絕緣層11製成使四元件8嵌入在絕緣層11中。適用於絕緣層11之材料範例為聚醯胺、FR1、FR5、聚芳醯胺、聚四氟乙烯、鐵氟龍®、LCP(液晶聚合物)及預硬化黏合劑層，亦即，預浸材。根據特定實施例，圖6中所示之結構藉由熱進一步壓製，以成為單一模組，因此達成機械性耐用構造。根據其他特定實施例，一模製過程用於形成一單一模組。根據特定實施例，一導電層12配置在絕緣層11之頂面上，通常 為銅或其他導電材料。
在圖7中，揭示根據本發明第一實施例之電子模組1之第七製造步驟之示意圖。導電箔片2及剝離層3移除。在一實施例中，其中，剝離層3之材料係經選擇，以致使其在先前之熱處理步驟期間至少部分喪失其黏含性或黏著力，金屬箔片2可以藉由此熱處理而簡單移除。當然，任意其他適用之方法及科技皆可使用。移除後。實質上無剝離層3之材料留在電子模組1中。此外，若有些許剝離層3之材料殘留物，可以藉由附加之清洗步驟輕易移除。
在圖8中，揭示根據本發明第一實施例之電子模組1之第八製造步驟之示意圖。電子模組1之通孔5中之材料移除，以致使導電材料未移除，例如藉由電漿蝕刻或低功率雷射或其組合。藉由從通孔5移除第一及第二光阻劑層4、6及黏合劑7之材料，即形成通孔13。此舉通常也清洗了元件8之接觸區10，但是也可以使用各別清洗過程以清洗接觸區10。通孔13從下導電表面14延伸通過導電材料及黏合劑層7，到達元件8之接觸區10。清洗後，可以進一步檢查元件8之對準，因為正確對準元件8之接觸區10將透過通孔13而呈現。根據特定實施例，接觸區10之對準檢驗例如可以使用2D或3D測量系統或X射線測量系統進行，用於測量接觸區10之位置。藉由一電子計算裝置之助，一測量信號或測量值可以對照各參考信號或各參考值來檢查，且測量信號或測量值可以 根據界定之容差值分類成「OK」或「not OK」。
在圖9中，揭示根據本發明第一實施例之電子模組1之第九製造步驟之示意圖。通孔13以導電材料填充，例如金屬、金屬合金、導電糊或導電聚合物，例如導電黏合劑。也可以使用不同導電材料層填充通孔13。最佳之電接觸係使用一實施例達成，其中通孔13係藉由生長金屬於通孔13內及元件8之接觸區10之頂面上而填充。接著可以在通孔13內產生一通孔結構，其實質上為純金屬。接著也可以在通孔13內產生一通孔結構，其係與元件8之接觸區10之導電村料呈冶金接觸。進行通孔13之金屬化及導電材料(例如，銅)在通孔13中之生長。換句話說，導電材料導送入通孔13中，以利形成元件8之接觸區10與下導電表面14之間的電接觸。高品質的電接觸例如可以藉由化學方式或藉由電化學法生長導電材料形成冶金連接來達成。一替代型式為藉由一化學法生長一薄層且使用較廉價之電化學法繼續生長。當然，任意其他適當方法皆可取代或附加於上述方法。因此，可行的方法例如包括電化學電鍍、電沈積法、濺鍍及蒸鍍。接觸結構可包括一、二或多數金屬之一、二或多層。可行的金屬包括但是不限定於例如銅、鋁、鋅、鎳、金、鈦或鐵。例如也可以使用導電黏合劑、導電糊或焊料。
在圖10中，揭示根據本發明第一實施例之電子模組1之第十製造步驟之示意圖。在電子模組1之此最後製造步驟中，電子模組1之導電層12及下導電表面14 移除，因此曝露導電圖案15、16。在一實施例中，從至少一導電圖案15之第二表面21延伸至元件8之至少一接觸區10之接觸表面9的至少一通孔的長寬比係小於2.0、小於1.0、小於0.75、小於0.5、小於0.4、或小於0.3。黏合劑層7強化元件8與導電圖案15之間的機械性連接，因此達成一機械性耐用構造。
在圖13中，揭示根據本發明第二實施例之電子模組1之第三製造步驟之示意圖。相反於根據第一實施例之電子模組1之第三製造步驟(參閱圖3)，一附加之聚合物層17配置於第二光阻劑層6之第二表面19之頂面上。此配置方式造成第二光阻劑層6之第二表面19與電子模組1之黏合劑層7及絕緣層11之間的一附加層。根據一特定實施例，聚合物層17施加成一單層或多層。根據另一特定實施例，聚合物層17係一使用附加之黏合劑層附接的膜。附加之聚合物層17在實施例中有其效益，其中，重要的是避免導電圖案15與元件8之間的絕緣中有任何孔隙。此孔隙例如出現在若形成黏合劑層7之黏合劑中有氣泡時。此氣泡影響導電圖案15與元件8之間的絕緣之介電性質，至少在某些應用中這是應避免的。附加之聚合物層17也可以用於調整或設定元件與導電圖案之間的絕緣層之介電性質。附加之聚合物層17也可以用於調整或設定元件與導電圖案之間的距離。附加之聚合物層17例如可由聚醯亞胺或環氧樹脂構成。
在圖14中，揭示根據本發明第二實施例之電 子模組1之第四製造步驟之示意圖。一黏合劑層7施加於附加之聚合物層17之頂面上。黏合劑層7之厚度例如在2μm與20μm之間的範圍內，像是在5μm與15μm之間。
在圖15中，揭示根據本發明第二實施例之電子模組1之第五製造步驟之示意圖。四元件8(具有接觸表面9，接觸表面具有接觸區10)放置於黏合劑層7上，使四元件8之接觸表面9面向第二光阻劑層6之第二表面19，且元件之接觸區10之位置與合併通孔5之位置重合。所附接之元件8例如可以是一積體電路，像是記憶體晶片、處理器、或專用積體電路(ASIC)。所附接之元件8例如也可以是一微機電系統(MEMS)、LED、或被動元件。所附接之元件8可容装或不容装且可包含設在其接觸區10中之接觸凸塊、凹部或平坦表面。接觸區10可配置於元件8之一或多側上。
在圖16中，揭示根據本發明第二實施例之電子模組1之第六製造步驟之示意圖。一絕緣層11製成使四元件8嵌入在絕緣層11中。根據特定實施例，一導電層12(例如，銅)配置在絕緣層11之頂面上。
在圖17中，揭示根據本發明第二實施例之電子模組1之第七製造步驟之示意圖。導電箔片2及剝離層3移除。
在圖18中，揭示根據本發明第二實施例之電子模組1之第八製造步驟之示意圖。電子模組1之通孔5 中之材料移除，例如藉由電漿蝕刻或低功率雷射或其組合。藉由從通孔5移除第一及第二光阻劑層4、6、聚合物層17及黏合劑7之材料，即形成通孔13。通孔13從下導電表面14延伸通過導電材料、聚合物層17及黏合劑層7，到達元件8之接觸區10。
在圖19中，揭示根據本發明第二實施例之電子模組1之第九製造步驟之示意圖。通孔13之金屬化及導電材料(例如，銅)在通孔13中之生長即在此步驟中進行。
在圖20中，揭示根據本發明第二實施例之電子模組之第十製造步驟之示意圖。在電子模組1之此最後製造步驟中，電子模組1之導電層12及下導電表面14移除，因此曝露導電圖案15、16。在一實施例中，從至少一導電圖案15之第二表面21延伸至元件8之至少一接觸區10之接觸表面9的至少一通孔的長寬比係小於2.0、小於1.0、小於0.75、小於0.5、小於0.4、或小於0.3。
在圖22中，揭示根據本發明第三實施例之電子模組之第二製造步驟之示意圖。一形成通孔5及一圖案之第一光阻劑層4配置於剝離層3之頂面上。接著進行導電材料之生長，例如銅、鋁、鋅、鎳、金、鈦或鐵，或是上述金屬之二或多個的組合，使第一光阻劑層4之厚度小於或大於所生長導電材料之厚度。電解生長一層導電材料是在已移除光阻劑或尚未施加光阻劑之區域中進行。通孔5之對準可以在附接元件8、或繼續製程之前先進一步檢 查。通孔5之對準檢查例如可以使用2D或3D測量系統或X射線測量系統進行，用於測量通孔5之位置。藉由一電子計算裝置之助，一測量信號或測量值可以對照各參考信號或各參考值來檢查，且測量信號或測量值可以根據界定之容差值分類成「OK」或「not OK」。
在圖23中，揭示根據本發明第三實施例之電子模組之第三製造步驟之示意圖。一黏合劑層7施加於光阻劑層4及所生長導電材料之頂面上。實施例中所用之黏合劑7例如可以是環氧樹脂。所用之黏合劑7依此選擇，使得所用之黏合劑充分黏合於光阻劑層4與導電材料以及元件8。黏合劑7之導電率較佳與絕緣層11之絕緣材料之導電率相同等級。
在圖24中，揭示根據本發明第三實施例之電子模組之第四製造步驟之示意圖。四元件8(具有接觸表面9，接觸表面具有接觸區10)放置於黏合劑層7上，使四元件8之接觸表面9面向光阻劑層4之第二表面19，且元件之接觸區10之位置與通孔5之位置重合。所附接之元件8例如可以是一積體電路，像是記憶體晶片、處理器、或ASIC。所附接之元件8例如也可以是MEMS、LED、或被動元件。所附接之元件8可容装或不容装且可包含設在其接觸區10中之接觸凸塊、凹部或平坦表面。接觸區10可配置於元件8之一或多側上。
在圖25中，揭示根據本發明第三實施例之電子模組之第五製造步驟之示意圖。一絕緣層11製成使四 元件8嵌入在絕緣層11中。根據特定實施例，一導電層12(例如，銅)配置在絕緣層11之頂面上。
在圖26中，揭示根據本發明第三實施例之電子模組之第六製造步驟之示意圖。導電箔片2及剝離層3移除。
在圖27中，揭示根據本發明第三實施例之電子模組之第七製造步驟之示意圖。電子模組1之通孔5中之材料移除，例如藉由電漿蝕刻或低功率雷射或其組合。藉由從通孔5移除光阻劑層4及黏合劑7之材料，即形成通孔13。
在圖28中，揭示根據本發明第三實施例之電子模組之第八製造步驟之示意圖。通孔13之金屬化及導電材料(例如，銅)在通孔13中之生長即在此步驟中進行。在電子模組1之此最後製造步驟中，導電層12進一步圖案化，以形成導電圖案16。在一實施例中，從至少一導電圖案15之第二表面21延伸至元件8之至少一接觸區10之接觸表面9的至少一通孔的長寬比係小於2.0、小於1.0、小於0.75、小於0.5、小於0.4、或小於0.3。黏合劑層7強化元件8與導電圖案15之間的機械性連接，因此達成一機械性較耐用構造。
在圖29中，揭示根據本發明第四實施例之電子模組101之示意圖。電子模組101具有至少一元件108，嵌入於第二絕緣材料層111中。第一絕緣材料層106具有第一表面118、及第二表面119及厚度hr。第一 絕緣材料層106聯結於第二絕緣材料層111。第一絕緣材料層106藉由一黏合劑層107聯結於第二絕緣材料層111。第二絕緣材料層111也可以設在第一絕緣材料層之第二表面119之至少一部分上。此外，具有第一表面120、第二表面121及厚度hp之至少一導電圖案層115係至少部分設在第一絕緣材料層106中之一開孔內。
第一絕緣材料層106之厚度hr可以大於第一絕緣材料層106之第一表面118與至少一導電圖案層115之第二表面121之間的距離d1。第一絕緣材料層106之厚度hr例如可以小於hr=25[μm]。
根據本發明之特定實施例，第一絕緣材料層106之厚度hr可以等於或大於hr=25[μm]。根據一範例，d3=hr-d1可以在d3=0.2[μm]與d3=5.0[μm]之間的範圍內。距離d3也可以等於或大於d3=5.0[μm]。根據特定實施例，第一絕緣材料層106之第一表面118與至少一導電圖案層115之第一表面之間的距離d2可以大於d2=0[mm]，例如，兩表面可以不齊平。根據特定範例，第一絕緣材料層106之第一表面118與至少一導電圖案層115之第一表面之間的距離d2可以是d2=0[mm]，例如，兩表面可以不齊平。
根據圖29之電子模組101進一步揭示具有一配置於第一絕緣材料層106之第二表面119與至少一元件108之一接觸表面109之間的黏合劑層107。黏合劑層107之厚度例如可以在ha=5[μm]與ha=15[μm]之間 的範圍內。根據特定範例，黏合劑層107之厚度可以等於或大於ha=15[μm]。根據又一範例，黏合劑層107之厚度可以小於ha=5[μm]。
再者，電子模組101可以具有至少一通孔113。通孔113可填以導電材料。通孔113可以連接元件108及導電圖案層115。根據一範例，通孔113之截面積之距離dvia可以小於dvia=20[μm]。根據另一範例，通孔113之截面積之距離dvia可以等於或大於dvia=20[μm]。
根據特定範例，至少一導電層或導電圖案層116可配置於絕緣層11之頂面上。至少一元件108可以是一被動元件、微電路、半導體元件。元件108也可以是元件之任意其他類型。
在其他範例中，電子模組101可以進一步包含上述之一附加聚合物層。聚合物層可配置於第一絕緣材料層106之第二表面119、黏合劑層107及面向第一絕緣材料層106的絕緣層111之表面之間。
在圖30中，揭示根據本發明第五實施例之電子模組101之示意圖。電子模組101具有嵌入於第二絕緣材料層111中之至少一元件108，電子模組包含第一絕緣材料層106，具有第一表面118、及第二表面119及厚度hr，及至少一導電圖案層115，具有第一表面120、及第二表面121及厚度hp。第一絕緣材料層106之第一表面118與至少一導電圖案層115之第二表面121之間的距離 d1大於第一絕緣材料層106之厚度hr。
第一絕緣材料層106之厚度hr例如可以小於hr=25[μm]。根據本發明之其他實施例，第一絕緣材料層106之厚度hr可以等於或大於hr=25[μm]。在一實施例中，距離d4=d1-hr通常在d4=0.2[μm]與d4=5.0[μm]之間的範圍內。
根據本發明之其他實施例，距離d4可以等於或大於d4=5.0[μm]。在一實施例中，第一絕緣材料層106之第一表面118與至少一導電圖案層115之第一表面之間的距離d2大於d2=0[mm]。根據其他實施例，第一絕緣材料層106之第一表面118與至少一導電圖案層115之第一表面之間的距離d2可以是d2=0[mm]。
根據圖30之電子模組101進一步包含一配置於第一絕緣材料層106之第二表面119與至少一元件108之一接觸表面109之間的黏合劑層107。黏合劑層107之厚度例如可以在ha=5[μm]與ha=15[μm]之間的範圍內。根據其他實施例，黏合劑層107之厚度可以等於或大於ha=15[μm]。根據又一實施例，黏合劑層107之厚度可以小於ha=5[μm]。
再者，電子模組101可以具有至少一通孔113，通孔可填以導電材料，通孔可以連接元件108及導電圖案層115。在一實施例中，通孔113之截面積之距離dvia可以小於dvia=20[μm]。根據另一實施例，通孔113之截面積之距離dvia可以等於或大於dvia=20[μm]。
根據特定範例，至少一導電圖案層116可配置於絕緣層11之頂面上。至少一元件108可以是一被動元件、微電路、半導體元件。元件108也可以是元件之任意其他類型。電子模組101可以進一步包含一附加聚合物層。聚合物層可配置於第一絕緣材料層106之第二表面119、黏合劑層107及面向第一絕緣材料層106的絕緣層111之表面之間。
根據特定實施例，一電子模組具有第一絕緣材料層，其內部具有一開孔；第二絕緣材料層，其聯結於第一絕緣材料層；一元件，係在一至少部分和聯結之第一絕緣材料層中之開孔重疊的位置至少部分嵌入於第二絕緣材料層內；及一導電圖案層，其至少部分設在第一絕緣材料層之開孔內且電耦合於元件；其中，導電圖案層並不和第一絕緣材料層之至少一表面齊平。
從圖29及30可以看出，導電圖案15係設置使其並不和第一絕緣材料層106齊平。導電圖案層可以部分延伸出第一絕緣材料層中之開孔外且伸入黏合劑層內，如圖30中所示。黏合劑層亦部分延伸於第一絕緣材料層中之開孔內，如圖29中所示。也可以在黏合劑層中設有一通孔，供元件通過此處以電氣耦合於導電層。
元件可以完全嵌入於第二絕緣材料層內。元件也可以完全嵌入於第二絕緣材料層與黏合劑層內。
此外，可以設有至少二元件，其至少部分嵌入於第二絕緣材料層內。至少二元件可以位於和第一絕緣 材料層中之開孔相對應的位置，且至少二元件可以電連接於導電圖案層。相對應是指元件和開孔對準，以致使其可以電連接於導電圖案層，如圖28中所示。
導電圖案層可以和第一絕緣材料層相同平面。此外，根據特定實施例，導電圖案層之至少一表面並不和第一絕緣材料層之對應表面齊平。如圖29及30中所示，導電圖案層無一表面和第一絕緣材料層106之任一表面118或119齊平。導電圖案層和第一絕緣材料層之非齊平表面可以是位於或最接近於和第二絕緣材料層形成界面處之表面，例如，119及121。
儘管本發明已詳細說明，以作揭示，在申請專利範圍內仍可達成許多變化及調整。此外，應該瞭解的是本發明可以想見的是在可行之範圍內，任意實施例之一或多個特徵可以和任意其他實施例之一或多個特徵組合。
應該瞭解的是，所揭露之本發明實施例並不限於本文內所述之特定結構、製程步驟、或材料，而是延伸至習於此技者所知之其等效技術。亦應瞭解的是，本文內所用之術語僅為了揭述特定實施例，並非用於限制。

Claims (18)

  1. 一種製造電子模組之方法，包含：提供光阻劑層，該光阻劑層具有第一表面及第二表面及該第一表面與該第二表面之間的厚度，提供至少一開孔通過該光阻劑層，配置黏合劑於該光阻劑層之頂上或部分頂上，其中，附加之聚合物層係形成於該光阻劑層與該黏合劑之間，提供絕緣材料於該光阻劑層之該第二表面上，及至少一元件嵌入於該絕緣材料中，提供至少一導電圖案於該至少一開孔中，以致使該至少一導電圖案具有第一表面及第二表面，其中，該第二表面面向該絕緣材料且該第一表面背向該絕緣材料，及該光阻劑層之該第一表面與該至少一導電圖案之該第二表面之間的距離係小於或大於該光阻劑層之厚度，及提供該至少一導電圖案與該至少一元件之間的連接元件。
  2. 一種用於製造電子模組的方法，該電子模組具有至少一元件嵌入於絕緣材料中，該方法包含以下步驟：a)配置剝離層於導電箔片之第一表面上，b)配置具有圖案及/或開孔之第一光阻劑層於該剝離層之頂面上且生長導電材料，該第一光阻劑層的厚度大於或小於生長的該導電材料的厚度，c)配置黏合劑於該光阻劑層與生長的該導電材料之頂面上或部分頂面上，或在具有接觸區之至少一元件之接觸表面上，d)放置該至少一元件，使該接觸表面面向該光阻劑層之第二表面，且該接觸區之位置與該開孔之位置重合，e)配置絕緣層，使該至少一元件嵌入於該絕緣層中，f)移除該導電箔片及該剝離層，及g)從該開孔移除材料，因此形成通孔，及在放置該至少一元件後，生長導電材料於該通孔中，因此使該導電材料與該至少一元件電接觸。
  3. 如申請專利範圍第2項之用於製造電子模組的方法，其中，附加之聚合物層係形成於該第一光阻劑層與該黏合劑之間。
  4. 如申請專利範圍第2項之用於製造電子模組的方法，其中，具有圖案及開孔之第二光阻劑層係在步驟b)之後配置，使該第二光阻劑層之第一表面面向該第一光阻劑層且生長導電材料，該第二光阻劑層的厚度大於或小於生長的該導電材料的厚度。
  5. 如申請專利範圍第2項之用於製造電子模組的方法，其中具有圖案及開孔之第二光阻劑層係在步驟b)之後配置，使該第二光阻劑層之第一表面面向該第一光阻劑層且生長導電材料，該第二光阻劑層的厚度大於或小於生長的該導電材料的厚度，及在配置第二光阻劑層後，附加之聚合物層係形成於該第二光阻劑層之第二表面與該黏合劑之間。
  6. 如申請專利範圍第2項之用於製造電子模組的方法，其中，導電層及/或該電子模組之下導電表面係經蝕刻，以便在該導電材料生長於該通孔中之後形成導電圖案。
  7. 如申請專利範圍第2項之用於製造電子模組的方法，其中，該黏合劑係在放置該至少一元件後主動硬化。
  8. 如申請專利範圍第2項之用於製造電子模組的方法，其中，該黏合劑係藉由熱固化活性化或UV固化活性化主動硬化。
  9. 如申請專利範圍第2項之用於製造電子模組的方法，其中，導電層配置於該絕緣層之頂面上。
  10. 一種電子模組，包含：第一絕緣材料，具有第一表面、第二表面及該第一表面與該第二表面之間的厚度，開孔，通過該第一絕緣材料，第二絕緣材料，設於該第一絕緣材料之該第二表面的至少一部分上，元件，至少部分嵌入於該第二絕緣材料中且電耦合於導電圖案，第三絕緣材料，在該元件與該第一絕緣材料之間，其中，該導電圖案至少部分在該開孔中，且該導電圖案具有第一表面及相對的第二表面，其中，該導電圖案的該第二表面面向該第二絕緣材料且該第一表面背向該第二絕緣材料，及該第一絕緣材料之該第一表面與該導電圖案之該第二表面之間的距離係小於該第一絕緣材料之厚度或大於該第一絕緣材料之厚度，及其中，在通孔中的連接元件設於該導電圖案與該元件之間，且藉由重合該元件的接觸區的位置的該通孔穿過該第三絕緣材料。
  11. 如申請專利範圍第10項之電子模組，其中，該連接元件包含積置於該絕緣材料之通孔中的導電材料。
  12. 如申請專利範圍第10項之電子模組，其中，該第一絕緣材料之該第二表面上的該第二絕緣材料包含黏合劑層或不同於該第二絕緣材料之任意其他材料。
  13. 如申請專利範圍第10項之電子模組，其中，該第一絕緣材料之該第二表面上的該第二絕緣材料包含絕緣層。
  14. 如申請專利範圍第10項之電子模組，其中，該第一絕緣材料之該第二表面上的該第二絕緣材料包含聚合物層。
  15. 如申請專利範圍第10項之電子模組，其中，該第一絕緣材料之該第一表面與該至少一導電圖案之該第一表面之間的距離係大於零。
  16. 如申請專利範圍第10項之電子模組，其中，從該至少一導電圖案之該第二表面延伸至該元件之至少一接觸區之接觸表面的至少一通孔的長寬比係小於2.0、小於1.0、小於0.75、小於0.5、小於0.4、或小於0.3。
  17. 如申請專利範圍第10項之電子模組，其中，該至少一導電圖案係配置於該第二絕緣材料之頂面上。
  18. 如申請專利範圍第10項之電子模組，其中，該至少一元件係被動元件、微電路、半導體元件、或任意其他類型之元件。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9439292B1 (en) * 2015-03-06 2016-09-06 Kinsus Interconnect Technology Corp. Method for manufacturing a circuit board with buried element having high density pin count and the circuit board structure
US10332832B2 (en) 2017-08-07 2019-06-25 General Electric Company Method of manufacturing an electronics package using device-last or device-almost last placement
KR102508540B1 (ko) * 2018-02-13 2023-03-09 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 발광 소자 패키지
CN112470553A (zh) * 2018-10-11 2021-03-09 深圳市修颐投资发展合伙企业（有限合伙） 复合工艺扇出封装方法
TWI671572B (zh) * 2018-10-22 2019-09-11 友達光電股份有限公司 顯示面板及其製造方法
CN111083879B (zh) * 2019-07-26 2021-02-02 微智医疗器械有限公司 电子元件与电路板的连接方法、电路板组件及电子设备
CN112185813A (zh) * 2020-09-17 2021-01-05 南京信光半导体科技有限公司 一种基于湿法腐蚀的薄膜图形刻蚀方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030141596A1 (en) * 2000-02-28 2003-07-31 Hidehiro Nakamura Wiring board, semiconductor device, and method of manufacturing wiring board
US20100019368A1 (en) * 2008-07-25 2010-01-28 Samsung Electronics Co., Ltd. Semiconductor chip package, stacked package comprising semiconductor chips and methods of fabricating chip and stacked packages
US20100236822A1 (en) * 2009-03-23 2010-09-23 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US20110221069A1 (en) * 2010-03-10 2011-09-15 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20140347833A1 (en) * 2013-05-27 2014-11-27 Shinko Electric Industries Co., Ltd. Electronic component device and method of manufacturing the same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950012658B1 (ko) 1992-07-24 1995-10-19 삼성전자주식회사 반도체 칩 실장방법 및 기판 구조체
US5936847A (en) 1996-05-02 1999-08-10 Hei, Inc. Low profile electronic circuit modules
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
US6350633B1 (en) 2000-08-22 2002-02-26 Charles W. C. Lin Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
JP4117603B2 (ja) * 2002-08-26 2008-07-16 ソニー株式会社 チップ状電子部品の製造方法、並びにその製造に用いる疑似ウェーハの製造方法
FI20041680A (fi) * 2004-04-27 2005-10-28 Imbera Electronics Oy Elektroniikkamoduuli ja menetelmä sen valmistamiseksi
FI117814B (fi) * 2004-06-15 2007-02-28 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
FI20041525A (fi) * 2004-11-26 2006-03-17 Imbera Electronics Oy Elektroniikkamoduuli ja menetelmä sen valmistamiseksi
FI119714B (fi) 2005-06-16 2009-02-13 Imbera Electronics Oy Piirilevyrakenne ja menetelmä piirilevyrakenteen valmistamiseksi
FI122128B (fi) 2005-06-16 2011-08-31 Imbera Electronics Oy Menetelmä piirilevyrakenteen valmistamiseksi
KR20070063748A (ko) * 2005-12-15 2007-06-20 삼성전자주식회사 웨이퍼 레벨 패키지 및 이의 제조 방법
AT12316U1 (de) * 2008-10-30 2012-03-15 Austria Tech & System Tech Verfahren zur integration eines elektronischen bauteils in eine leiterplatte
KR101047484B1 (ko) * 2008-11-07 2011-07-08 삼성전기주식회사 전자 소자 내장 인쇄회로기판 및 그 제조 방법
KR101826898B1 (ko) * 2011-05-26 2018-03-23 삼성디스플레이 주식회사 표시패널
CN104025728A (zh) * 2011-10-31 2014-09-03 名幸电子有限公司 元器件内置基板的制造方法及使用该方法制造的元器件内置基板
CN103489796B (zh) * 2012-06-13 2016-01-20 健鼎（无锡）电子有限公司 元件内埋式半导体封装件的制作方法
US9024429B2 (en) * 2013-08-29 2015-05-05 Freescale Semiconductor Inc. Microelectronic packages containing opposing devices and methods for the fabrication thereof
US9425121B2 (en) * 2013-09-11 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with guiding trenches in buffer layer
DE102014101366B3 (de) * 2014-02-04 2015-05-13 Infineon Technologies Ag Chip-Montage an über Chip hinausstehender Adhäsions- bzw. Dielektrikumsschicht auf Substrat

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030141596A1 (en) * 2000-02-28 2003-07-31 Hidehiro Nakamura Wiring board, semiconductor device, and method of manufacturing wiring board
US20100019368A1 (en) * 2008-07-25 2010-01-28 Samsung Electronics Co., Ltd. Semiconductor chip package, stacked package comprising semiconductor chips and methods of fabricating chip and stacked packages
US20100236822A1 (en) * 2009-03-23 2010-09-23 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US20110221069A1 (en) * 2010-03-10 2011-09-15 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20140347833A1 (en) * 2013-05-27 2014-11-27 Shinko Electric Industries Co., Ltd. Electronic component device and method of manufacturing the same

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