TWI647686B - Display panel and driving method thereof - Google Patents

Abstract

The display panel includes: a pixel array including a display area and an omitted area, the display area including a plurality of first scan lines, the omitted area including a plurality of second scan lines, and a scan driver coupled to the pixel array The scan driver includes a display scan drive circuit group and an omitted scan drive circuit group, the display scan drive circuit group is used to drive the first scan lines, and the omitted scan drive circuit group is used to drive the first scan lines. A second scan line; and a timing control circuit, coupled to and controlling the scan driver. In a normal mode, the timing control circuit controls the display scan drive circuit group and the omitted scan drive circuit group with a first start signal to sequentially update the first scan lines and the second scan lines. In a skip update mode, the timing control circuit controls the display scan drive circuit group with a second start signal to update the first scan lines but controls the skip scan drive circuit group to not update the second For scanning lines, the scanning frequency of the first start signal is lower than the scanning frequency of the second start signal.

Description

Display panel and driving method thereof

The invention relates to a display panel and a driving method thereof.

In today's human life, the demand for information transmission using display devices has increased dramatically. However, in a display device, if the power consumption of the display device is too large, it will be disadvantageous for an electronic device using a battery as a power source. Reducing the update frequency of the screen is a technical method often used for power saving performance, but it may also cause the problem of screen flicker. On the other hand, if the operating frequency of the scan driver is increased to increase the screen update frequency to resolve the screen flicker, this will increase the power consumption of the display device.

Therefore, this case proposes a display panel and a driving method thereof, with a view to improving existing problems or other problems.

The present invention relates to a display device and a display panel, including: a pixel array including a display area and an omitted area, the display area including a plurality of first scan lines, and the omitted area including a plurality of second scan lines; The scan driver is coupled to the pixel array. The scan driver includes a display scan drive circuit group and an omitted scan drive circuit group. The display scan drive circuit group is used to drive the first scan lines, and the omitted scan The driving circuit group is used to drive the second scan lines; and a timing control circuit is coupled to and controls the scan driver. In a normal mode, the timing control circuit starts with A first start signal controls the display scan drive circuit group and the omission scan drive circuit group to sequentially update the first scan lines and the second scan lines; and in a skip update mode, the timing control The circuit controls the display scan drive circuit group with a second start signal to update the first scan lines but controls the omitted scan drive circuit group to not update the second scan lines. The scan of the first start signal The frequency is lower than the scanning frequency of the second start signal.

The present invention also relates to a display device driving method for a display panel. The display panel includes a display scanning driving circuit group and an omitted scanning driving circuit group. The driving method includes: controlling the display scanning in a normal mode. The driving circuit group and the omitted scanning driving circuit group sequentially update the plurality of first scanning lines and the plurality of second scanning lines of the display panel at a first operating frequency; and in a omitted updating mode, controlling the The scan driving circuit group is displayed, and the first scan lines are updated with a second operating frequency, but the omitted scan driving circuit group is controlled to not update the second scanning lines, wherein the second operating frequency is the same as the First operating frequency.

The present invention further relates to a display device and a display panel, including: a pixel array including a display area and an omitted area; a scan driver coupled to the pixel array, the scan driver including a display scan driving circuit group And an omitted scanning driving circuit group, the display scanning driving circuit group is used to drive the display area, the omitted scanning driving circuit group is used to drive the omitted area, and a timing control circuit is coupled to and controls the scanning driver . In a normal mode, the timing control circuit controls the display scan drive circuit group and the omitted scan drive circuit group in normal operation; and in a province In the slightly updated mode, the timing control circuit controls the display scan drive circuit group to operate normally, and the timing control circuit controls the omitted scan drive circuit group to stop operation.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail below in conjunction with the accompanying drawings:

100‧‧‧ display panel

110‧‧‧ pixel array

120‧‧‧Scan driver

130‧‧‧sequence control circuit

L1-LN‧‧‧scan line

EN1‧‧‧First enable signal

EN2‧‧‧Second enable signal

VST1‧‧‧First start signal

VST2‧‧‧Second start signal

SR1-SR14‧‧‧Shift Register

FIG. 1 is a functional block diagram of a display panel according to an embodiment of the present invention.

FIG. 2A to FIG. 2D show various detailed circuit diagrams of the shift register according to an embodiment of the present invention.

FIG. 3A shows a driving schematic diagram of a normal mode according to an embodiment of the present invention.

FIG. 3B shows a driving schematic diagram of the omission update mode according to the embodiment of the present invention.

4A to 4C show signal waveform diagrams of the normal mode and the omitted update mode according to the embodiment of the present invention.

The technical terms in this specification refer to the customary terms in the technical field. If some terms are described or defined in this specification, the interpretation of these terms is subject to the description or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those with ordinary knowledge in the technical field may selectively implement part or all of the technical features in any embodiment, or selectively combine part or all of the technical features in these embodiments.

FIG. 1 is a functional block diagram of a display panel according to an embodiment of the present invention. As shown in FIG. 1, the display panel 100 includes a pixel array 110, a scan driver 120, and a timing control circuit 130.

The pixel array 110 includes a plurality of scanning lines L1-LN (N is a positive integer). The scanning lines L1-LN of the pixel array 110 can be divided into a display area and an omitted area. The display area includes a plurality of first scan lines, and the omitted area includes a plurality of second scan lines. How to define the display area and the omitted area will be explained below.

The scan driver 120 is coupled to the pixel array 110. The scan drivers 120 are located on both sides of the pixel array 110. The scan driver 120 includes a display scan drive circuit group and an omitted scan drive circuit group. The display scan drive circuit group is coupled to the first scan lines, and the omitted scan drive circuit group is coupled to the second scan lines. line. How to define the display scan drive circuit group and omit the scan drive circuit group will be explained below.

The timing control circuit 130 is coupled to and controls the scan driver 120. The timing control circuit 130 outputs a first enable signal EN1, a second enable signal EN2, a first start signal VST1 and a second start signal VST2 to control the scan driver 120.

FIG. 2A to FIG. 2D show various detailed circuit diagrams of the shift register according to an embodiment of the present invention. For the convenience of explanation, the type of the shift register in FIG. 2A is referred to as SRa, the type of the shift register in FIG. 2B is referred to as SRb, and the type of the shift register in FIG. 2C is referred to as SRb. It is called SRc, and the type of the shift register in FIG. 2D is called SRd.

The type of shift register (SRa) in FIG. 2A accepts two input signals (N-1 and ST) and provides an output signal (DO), but SRa is controlled by a signal (EN). The type of shift register (SRb) in Figure 2B accepts two input signals (N-1 and ST), An output signal (DO) is provided, but SRb is controlled by two signals (EN1 and EN2). The type of the shift register (SRc) in FIG. 2C accepts an input signal (ST) and provides an output signal (DO), but SRc is controlled by the signal EN. The type of shift register (SRd) in FIG. 2D accepts an input signal (ST) and provides an output signal (DO).

FIG. 3A shows a driving schematic diagram of a normal mode according to an embodiment of the present invention. FIG. 3B shows a driving schematic diagram of the omission update mode according to the embodiment of the present invention. 4A to 4C show signal waveform diagrams of the normal mode and the omitted update mode according to the embodiment of the present invention. For the convenience of description, the scan driver 120 on one side of the pixel array 110 includes shift registers SR1 to SR14 is taken as an example for description, but it is understood that the present invention is not limited to this. That is, in a possible embodiment of the present case, in the scan driver 120, the display scan drive circuit group includes shift registers SR5-SR7 and SR14, and the omitted scan drive circuit group includes shift registers SR1-SR4 and SR8-SR13, but know that this case is not limited to this.

In an embodiment of the present invention, the shift registers SR1 and SR8 are implemented as the shift register type (SRc) of FIG. 2C, and the shift registers SR5 and SR14 are shifted by the shift register of FIG. 2B. The shift register type (SRb) is implemented, and the shift registers SR2-SR4, SR6-SR7, and SR9-SR13 are implemented as the shift register type (SRd) in FIG. 2D. However, it is known that this case is not limited to this. In other possible embodiments of this case, there may be other different circuit implementations, which are all within the spirit of this case.

The following table shows the operation mode of the display panel 100 in one embodiment of the present invention, which is controlled by the first and second enable signals EN1 and EN2.

In the above table, "prohibited operation" means that when the operation mode of the display panel 100 is controlled, it cannot be controlled in this manner. For example, if the first enable signal EN1 and the second enable signal EN2 are enabled at the same time, it is a "prohibited operation", and the rest can be deduced by analogy.

In normal mode (the first enable signal EN1 is enabled (for example, VGH), and the second enable signal EN2 is disabled (or called non-enabled), such as VGL), the timing control circuit 130 starts with the first The signal VST1 controls the shift register SR1 of the scan driver 120 so that the shift register SR1 outputs a signal to the shift register SR2 of the next stage, and so on. That is, in the normal mode and under the control of the timing control circuit 130, the shift registers SR1-SR14 are all under normal operation to drive the pixel array 110. That is, when the first enable signal EN1 is enabled and the second enable signal EN2 is disabled, the shift registers SR1-SR14 are all under normal operation. In the normal mode, controlled by the first enable signal EN1, the shift register SR8 is also in normal operation. In the normal mode, under the control of the timing control circuit 130, the scanning lines L1-LN of the pixel array 110 can be normally driven and displayed.

In the omitted update mode (the first enable signal EN1 is disabled and the second enable signal EN2 is enabled), the timing control circuit 130 controls the second start signal VST2 to Scan the shift register SR5 of the driver 120, so that the shift register SR5 outputs a signal to the next-stage shift register SR6, and the shift register SR6 outputs a signal to the next-stage shift register SR7. , But the shift register SR7 outputs a signal to the shift register SR14 (instead of the shift register SR8, and the shift register SR8 is in the stop operation mode). In the omitted update mode, under the control of the timing control circuit 130, when the first enable signal EN1 is disabled and the second enable signal EN2 is enabled, the shift registers SR5-SR7 and SR14 are both at Under normal operation, the remaining shift registers SR1-SR4 and SR8-SR13 are in the stop operation mode (to save the power consumption of the display panel 100). That is, in the omitted update mode, under the control of the timing control circuit 130, among the scan lines L1-LN of the pixel array 110, they are related to (coupled to) the shift registers SR5-SR7 and SR14. The scan lines can be driven and displayed normally, but the scan lines related to (coupled to) the shift registers SR1-SR4 and SR8-SR13 will not be updated.

That is, in the embodiment of the present case, in the omitted update mode (the first enable signal EN1 is disabled and the second enable signal EN2 is enabled), the timing control circuit 130 uses a second start signal VST2 controls the display scan drive circuit group to update the first scan lines but controls the omitted scan drive circuit group to not update the second scan lines. As shown in FIG. 4A, the scanning frequency of the first start signal VST1 is lower than the scanning frequency of the second start signal VST2. That is, in the omitted update mode and under the control of the timing control circuit 130, the display scan driving circuit group updates the first scan lines (that is, in the omitted update mode, the display area is still updated), However, the second scan scan circuit group does not update the second scan lines (that is, in the omitted update mode, the omitted region is not updated).

That is, in the embodiment of the present case, in the normal mode, the display area and the omitted area have a first picture update rate. In the omitted update mode, the screen update rate of the omitted region is substantially 0, and the display region has a second screen update rate, and the first screen update rate is substantially lower than the second screen update rate. For example, when the first picture update rate is 60 Hz, in the case of FIG. 3B, the second picture update rate is 60 * (14/4) = 210 Hz.

In the embodiment of the present case, when the display panel 100 is driven in the normal mode, the display scanning driving circuit group and the omitted scanning driving circuit group are controlled to sequentially update a plurality of first pieces of the display panel with a first operating frequency. The scan line and the plurality of second scan lines, wherein the display scan drive circuit group drives / updates the first scan lines, and the omission scan drive circuit group drives / updates the second scan lines. In addition, when the display panel 100 is driven in the omitted update mode, the display scan drive circuit group is controlled to update the first scan lines at a second operating frequency, but the omitted scan drive circuit group is controlled to not update the first scan lines. Two scanning lines, wherein the second operating frequency is the same as the first operating frequency. Here, the operating frequency refers to, for example, the operating frequencies of the shift registers SR1-SR14 in FIGS. 3A and 3B. That is, in the embodiment of the present case, when switching between the normal mode and the omission update mode, the operating frequencies of the shift registers SR1-SR14 are not changed. That is, the embodiment of this case does not improve the screen update rate in the omission update mode by increasing the operating frequency of the shift registers SR1-SR14.

That is, in the display panel 100 of the embodiment of the present invention, in a normal mode, the timing control circuit 130 controls the display scan drive circuit group and the omitted scan drive circuit group of the scan driver 120 in normal operation; and In the omitted update mode, the timing control circuit 130 controls the display scan driving circuit group of the scan driver 120 Set in normal operation, and the timing control circuit 130 controls the omitted scan driving circuit group of the scan driver 120 to stop operation (to save the power consumption of the display panel 100).

As described above, in the display panel of the embodiment of the present invention, when switching to the omission update mode, the screen update rate of the display area can be improved even if the operating frequency of the scan driver is not changed / increased, so the screen flicker can be reduced. . In the display panel of the embodiment of the present invention, when switching to the omission update mode, at least a part of the scan driver is in the stop operation mode, and the power consumption of the display area can be reduced.

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (7)

A display panel includes a pixel array including a display area and an omitted area. The display area includes a plurality of first scan lines, and the omitted area includes a plurality of second scan lines. A scan driver is coupled to the picture. Element array, the scan driver includes a display scan drive circuit group and an omitted scan drive circuit group, the display scan drive circuit group is used to drive the first scan lines, and the omitted scan drive circuit group is used to drive The second scan lines; and a timing control circuit coupled to and controlling the scan driver, wherein in a normal mode, the timing control circuit controls the display scan drive circuit group and the omitted scan with a first start signal The driving circuit group sequentially updates the first scanning lines and the second scanning lines; and in a skip update mode, the timing control circuit controls the display scanning driving circuit group with a second start signal to Update the first scan lines but control the omitted scan drive circuit group so as not to update the second scan lines, the scan of the first start signal A second frequency lower than the frequency of the scanning start signal. The display panel according to item 1 of the scope of patent application, wherein in the normal mode, the display area and the omitted area have a first screen update rate; and in the omitted update mode, the screen update of the omitted area The rate is substantially 0, and the display area has a second picture update rate, and the first picture update rate is substantially lower than the second picture update rate. A driving method for a display panel includes a display scanning driving circuit group and an omitted scanning driving circuit group. The driving method includes: controlling the display scanning driving circuit group and the omitted scanning in a normal mode. A driving circuit group, which sequentially updates the plurality of first scanning lines and the plurality of second scanning lines of the display panel at a first operating frequency; and controls the display scanning driving circuit group in an omission update mode to A second operating frequency updates the first scan lines, but controls the group of omitted scan driving circuits to not update the second scan lines, wherein the second operating frequency is the same as the first operating frequency. The driving method according to item 3 of the scope of patent application, wherein in the normal mode, the display scan drive circuit group and the omitted scan drive circuit group are controlled with a first start signal to sequentially update the A first scan line and the second scan lines; and in the omission update mode, controlling the display scan drive circuit group with a second start signal to update the first scan lines, but control the omission scan The driving circuit group does not update the second scan lines, and the first start signal is lower in frequency than the second start signal. The driving method according to item 3 of the scope of patent application, wherein in the normal mode, the first scanning lines and the second scanning lines are driven by a first driving signal having a first frame update rate. ; And in the omitted update mode, driving the first scan lines with a second driving signal having a second frame update rate but the second scan lines are not driven, the first frame update rate is substantially low At the second frame update rate, the frame update rates of the second scan lines are substantially zero. A display panel includes: a pixel array including a display area and an omitted area; a scan driver coupled to the pixel array; the scan driver includes a display scan drive circuit group and an omitted scan drive circuit group The display scan driving circuit group is used to drive the display area, and the omitted scan drive circuit group is used to drive the omitted area; and a timing control circuit is coupled to and controls the scan driver, in a normal mode, The timing control circuit controls the display scan drive circuit group and the omitted scan drive circuit group to operate normally, the display area and the omitted area have a first screen update rate; and in an omitted update mode, the timing control circuit Controlling the display scan drive circuit group to operate normally, and the timing control circuit controlling the omission scan drive circuit group to stop operation, the display area has a second picture update rate, the first picture update rate is substantially lower than the second Picture update rate. The display panel according to item 6 of the scope of patent application, wherein, in the omission update mode, the screen update rate of the omitted area is substantially zero.