JP2004126551A - Electro-optical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive unit for an electro-optical device, which is equipped with a clock signal phase difference correcting circuit without increasing the layout area of the driving circuit while surely eliminating a phase difference between a clock signal and an opposite phase clock signal. <P>SOLUTION: The clock signal phase difference correcting circuit 500 is composed of a first buffer circuit, a bistable circuit and a second buffer circuit, with the second buffer circuit connected to the output section of the bistable circuit. At least an external clock signal input section is connected to a data line driving circuit 101 or a scanning line driving circuit 104 through the clock signal phase difference correcting circuit 500. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a driving circuit of an electro-optical device of an active matrix driving system by driving a thin film transistor (hereinafter, appropriately referred to as a TFT), an electro-optical device including the driving circuit, and an electronic apparatus using the electro-optical device. And especially a clock signal supplied to a driving circuit for a data line or a scanning line, and a phase difference correcting means for a clock signal having a phase opposite to that of the clock signal (hereinafter referred to as an anti-phase clock signal). It belongs to the technical fields of drive circuits, electro-optical devices, and electronic devices.
[0002]
[Prior art]
FIG. 18 shows an example of a conventional liquid crystal device of an active matrix drive system by TFT drive. In FIG. 18, a transistor 30 is formed corresponding to each of intersections of the scanning lines 31 and the data lines 35, and the scanning lines 31 of Y1 to Ym and the data lines 35 of S1 to Sn arranged vertically and horizontally, respectively. Are provided on a substrate for a liquid crystal device. In addition, various peripheral circuits including TFTs as components such as a scanning line driving circuit 104, a data line driving circuit 101, and a sampling circuit 301 are provided on such a liquid crystal device substrate.
[0003]
To the data line driving circuit 101, a driving signal is sequentially transferred to a sampling circuit driving signal line 306 which controls a sampling circuit 301 for writing an image signal VID supplied via an image signal line 304 to a data line 35. The shift register is configured as described above. Further, a shift register is configured in the first scanning line driving circuit 104 so as to sequentially transfer the scanning signal to the first scanning line 31.
[0004]
[Problems to be solved by the invention]
In the liquid crystal device having the above-described configuration, the clock signal CL output from the external control circuit (the clock signal for controlling the data line driving circuit 101 described below is denoted as CLX and the scanning line driving circuit 104 is controlled). The clock signal for performing the operation is denoted by CLY), and the inverted phase clock signal CL inverted by the external control circuit. _INV (An anti-phase clock signal for controlling the data line driving circuit 101 described later is CLX _INV And the antiphase clock signal for controlling the scanning line driving circuit 104 is CLY _INV Conventionally, it is supplied in a liquid crystal device substrate using a circuit as shown in FIG. 19A as an example. Then, the clock signal CL and the opposite phase clock signal CL _INV Are supplied first to the inverters I1 and I3 in the liquid crystal device substrate via the supply lines P1 and P1 ', and then to the respective drive circuits via the inverters I2 and I4.
[0005]
When such a circuit is used, a phase difference T occurs between the supply lines P1 and P1 'as shown in FIG. 19B, which is caused by the inverters I1 and I3 and further the inverters I2 and I2. It does not disappear even after passing through I4. That is, as shown in FIG. 19 (b), in the connection lines P2 and P2 ′ between the inverter I1 and the inverter I2 and between the inverter I3 and the inverter I4, the supply connected to the output of the inverters I2 and I4. In lines P3 and P3 ', a clock signal CL and an antiphase clock signal CL having a phase difference T with respect to the clock signal CL. _INV Is to be propagated. Therefore, in the shift registers included in the data line driving circuit 101 and the scanning line driving circuit 104, the clock signal CL and the antiphase clock signal CL _INV Once the phase difference T is generated between the scan line and the scan line, the signal waveform is deteriorated, and the start signal SP (the start signal for controlling the data line driving circuit 101 described later is referred to as SPX) A clock signal for controlling the drive circuit 104 is referred to as SPY) cannot be transferred to each stage, which causes a problem that a malfunction occurs. Such a problem also occurs in the shift register of the scan line driver circuit 104.
[0006]
Further, the clock signal CL and the antiphase clock signal CL _INV When the supply line for supplying the clock signal is routed on the substrate for the liquid crystal device, the clock signal CL and the antiphase clock signal CL depend on the capacity of the clock signal supply line. _INV Is deteriorated, an appropriate waveform is not obtained, and as a result, the drive signal cannot be normally transferred to each stage, which causes a problem that a malfunction is caused.
[0007]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problem, and reliably corrects a phase difference between a clock signal and a clock signal having an opposite phase to the clock signal to operate the scanning line driving circuit and the data line driving circuit satisfactorily. It is an object to provide a driving circuit of an electro-optical device, an electro-optical device, and an electronic device that can perform the driving.
[0008]
[Means for Solving the Problems]
2. The driving circuit for an electro-optical device according to claim 1, wherein: a plurality of data lines to which an image signal is supplied; a plurality of scanning lines to which a scanning signal is supplied; A driving circuit for an electro-optical device, comprising: a switching unit connected to each of the scanning lines; and a pixel electrode connected to the switching unit, wherein the clock signal and a clock signal having an opposite phase to the clock signal are provided. A driving means having a shift register for transferring a predetermined signal based on the above, and an input from an input unit for respectively supplying the clock signal and the clock signal of the opposite phase to the driving means is a clock signal phase difference correcting means. And supplied to the driving unit via the control unit.
[0009]
According to the driving circuit of the electro-optical device according to the first aspect, the clock signal and the clock signal having the opposite phase are supplied to the driving unit through the supply line of the clock signal and the input portion of the clock signal having the opposite phase to the clock signal, respectively. However, a clock signal phase difference correcting means is provided between these signal lines. Therefore, the clock signal phase difference correcting means is configured such that, for example, the input part of the clock signal input from the outside of the liquid crystal device is supplied to the driving means via the common clock signal phase difference correcting means. It is not necessary to provide each stage of the shift register of the means. Therefore, the size of the driving circuit of the electro-optical device can be reduced, and the size of the pixel can be reduced, so that a high-definition electro-optical device can be provided. Furthermore, the clock signal and the opposite-phase clock signal whose phase difference has been corrected are supplied to the driving means, and the transfer of the signal by the shift register is performed without malfunction.
[0010]
According to a second aspect of the present invention, in the electro-optical device driving circuit according to the first aspect, the clock signal phase difference correction unit includes the clock signal and the clock signal. Signal output means respectively connected to the input part of the antiphase clock signal for connecting the output parts of the first and second logic means for inverting the polarity of the input signal, and signal input means connected to the other input part; Signal propagation means connected to respective outputs of the first and second logic means of the feedback means.
[0011]
According to the driving circuit of the electro-optical device according to the second aspect, the clock signal is input to the first logic unit by the input unit, and the antiphase clock signal is input to the second logic unit by the supply line. The clock signal is output from the first logic means as a clock signal whose polarity is inverted by the first logic means, that is, an opposite phase clock signal. Similarly, the opposite phase clock signal is output by the second logic means. The clock signal having the inverted polarity is output from the second logic means. The output of the first logic is connected to the input of the second logic, and the output of the second logic is connected to the input of the first logic. You. Therefore, the antiphase clock signal output from the first logic means is input to the second logic means together with the antiphase clock signal supplied from the input part of the antiphase clock signal. The clock signal output from the second logic means is input to the first logic means together with the clock signal supplied from the input part of the clock signal. That is, in the first and second logic means, positive feedback is applied to the clock signal and the opposite-phase clock signal, and the clock signal and the opposite-phase clock signal supplied from the respective supply lines are output. Correction is performed to eliminate the phase difference.
[0012]
The clock signal and the opposite-phase clock signal having no phase difference as described above are input to the signal propagation means connected to the first and second logic means, and the clock signal is transmitted by the signal propagation means. , And supplied to the driving means via a supply line of the opposite phase clock signal. Therefore, the capacity added to the respective output sections of the first and second logic means depends on the connection paths between the first and second logic means and the signal propagation means, and the first and second logic means. The first and second logic means are substantially equal to each other in the positive feedback path, thereby preventing a change in the potential of the output section of the first and second logic means due to a capacitance difference. As a result, the signal drive capability for the positive feedback by the first and second logic means is maintained satisfactorily, the phase difference can be almost completely eliminated, and malfunction of the drive means is reliably prevented. be able to.
[0013]
According to a third aspect of the present invention, there is provided a driving circuit of the electro-optical device according to the first or second aspect, wherein at least two of the clock signal phase difference correcting means are provided. The capacitance value of the book wiring is substantially constant.
[0014]
According to the driving circuit of the electro-optical device according to the third aspect, the capacitance values of at least two wires of the clock signal phase difference correcting means are substantially constant. That is, a wiring path from the clock signal supply line to the first logic means, further from the first logic means to the signal propagation means without passing through the positive feedback path, and a wiring path from the clock signal supply line to the first logic means. The capacitance value of each wiring is substantially constant between the wiring path to the signal propagation means connected to the second logic means through the wiring path for feedback. The same applies to the wiring route on the second logic means side. Therefore, the capacitance added to the branch point of each wiring is substantially constant at all points, and the potential of each branch point is reliably prevented from fluctuating, so that the clock signal phase difference correcting means operates stably. Become.
[0015]
According to a fourth aspect of the present invention, in the driving circuit for an electro-optical device according to the second or third aspect, the clock signal phase difference correction unit is configured to: It is characterized by comprising a first buffer circuit for transmitting a signal to the signal feedback means, a bistable circuit as the signal feedback means, and a second buffer circuit as the signal propagation means.
[0016]
According to the driving circuit of the electro-optical device according to the fourth aspect, the clock signal supplied from the external clock signal supply unit is first corrected for the rounding of the waveform by the first buffer circuit and supplied to the bistable circuit. Is done. Next, in the bistable circuit, the phase difference between the clock signal and the opposite-phase clock signal is corrected by the positive feedback action. The clock signal and the opposite-phase clock signal output from the bistable circuit are supplied to the shift register of the driving means via the second buffer circuit, so that the capacity added after the output terminal of the second buffer circuit is reduced. Even if it increases, the driving capability of the bistable circuit does not decrease. Therefore, the clock signal whose phase difference has been corrected and the opposite phase clock signal are reliably supplied to the shift register, and malfunction of the shift register is reliably prevented.
[0017]
According to a fifth aspect of the present invention, there is provided a drive circuit for an electro-optical device according to the fourth aspect, wherein the bistable circuit is formed by a NAND circuit. Features.
[0018]
According to the drive circuit of the electro-optical device according to claim 5, the clock signal supplied from the clock signal supply line is provided in the signal feedback unit of the clock signal phase difference correction unit. Is input to the NAND circuit. On the other hand, the anti-phase clock signal supplied from the input part of the anti-phase clock signal is input to a NAND circuit as second logic means provided in the signal feedback means of the clock signal phase difference correction means. These two NAND circuits form a bistable circuit, and the output of the NAND circuit as the first logic means is input to the NAND circuit as the second logic means, and similarly, the second logic circuit The output of the NAND circuit as means is input to the NAND circuit as first logic means. Therefore, even when there is a phase difference between the clock signal and the opposite-phase clock signal, the clock signal and the opposite-phase clock signal input to the bistable circuit formed by the NAND circuit have polarities opposite to each other. A signal in which the polarity of the input signal is inverted is obtained from the two outputs of the bistable circuit formed by the NAND circuit at the timing when the inverted signal is obtained. As described above, the phase difference between the clock signal and the opposite-phase clock signal is eliminated by the bistable circuit formed by the NAND circuit. Moreover, as described above, since the signal propagation means is connected to the output section of the bistable circuit, positive feedback operation in the bistable circuit formed by the NAND circuit is reliably performed, and the phase difference Can be almost completely eliminated.
[0019]
According to a sixth aspect of the present invention, there is provided a drive circuit for an electro-optical device according to the fourth aspect, wherein the bistable circuit is formed of a NOR circuit. Features.
[0020]
According to the drive circuit of the electro-optical device according to claim 6, the clock signal supplied from the clock signal supply line is provided in the signal feedback unit of the clock signal phase difference correction unit. Is input to the NOR circuit. On the other hand, the anti-phase clock signal supplied from the input part of the anti-phase clock signal is input to a NOR circuit as second logic means provided in the signal feedback means of the clock signal phase difference correction means. These two NOR circuits form a bistable circuit, and the output of the NOR circuit as the first logic means is input to the NOR circuit as the second logic means, and similarly the second logic circuit is formed. The output of the NOR circuit as means is input to the NOR circuit as first logic means. Therefore, even when there is a phase difference between the clock signal and the anti-phase clock signal, the clock signal and the anti-phase clock signal input to the bistable circuit formed by the NOR circuit have polarities mutually. A signal in which the polarity of the input signal is inverted is obtained from the two outputs of the bistable circuit formed by the NOR circuit at the timing when the inverted signal is obtained. In this manner, the phase difference between the clock signal and the opposite-phase clock signal is eliminated by the bistable circuit formed by the NOR circuit. Moreover, as described above, the signal propagation means is connected to the output section of the bistable circuit, so that the positive feedback operation in the bistable circuit formed by the NOR circuit is reliably performed, and the phase difference Can be completely eliminated.
[0021]
According to a seventh aspect of the present invention, there is provided a drive circuit for an electro-optical device according to any one of the first to sixth aspects. The clock signal phase difference correcting means is provided at both ends of the data line or the scanning line, and the clock signal phase difference correcting means is independently provided between the input part of the clock signal and the respective driving means. Features.
[0022]
8. The driving circuit for an electro-optical device according to claim 7, wherein the clock signal phase difference correcting unit is configured to drive the clock signal phase difference between the driving unit on one side of the data line or the scanning line and a clock signal input unit and the data signal. It is provided independently between the driving means on the other side of the line or the scanning line and the clock signal input unit. Therefore, the length of the supply line of the clock signal or the supply line of the opposite-phase clock signal between each of the driving units and the clock signal phase difference correction unit is equal to the case where only one clock signal phase difference correction unit is provided. As compared with the above, the capacitance added to the output part of the signal propagation means of the clock signal phase difference correction means can be reduced. Therefore, it is possible to reduce the driving load of a supply unit such as a transistor that supplies the clock signal or the antiphase clock signal. In addition, the reduction of the capacitance can also prevent the waveforms of the clock signal and the anti-phase clock signal from deteriorating, and assure the reliable driving of the driving unit by a signal having a good waveform.
[0023]
An electro-optical device drive circuit according to claim 8 is a drive circuit for an electro-optical device according to any one of claims 1 to 7, wherein the shift register includes: A shift register driven in N (1, 2, 3,...) Series, wherein N clock signal phase difference correcting means are provided corresponding to each shift register.
[0024]
According to the drive circuit of the electro-optical device according to the eighth aspect, when the shift register is driven in N (1, 2, 3,...) Series, a clock signal and an antiphase clock are provided for each series. The clock signal phase difference correction means is provided N in correspondence with each shift register, so that the positions of the clock signal and the opposite phase clock signal are surely provided in each series. The phase difference is corrected, and malfunction of the shift register in each system is reliably prevented.
[0025]
According to a ninth aspect of the present invention, there is provided an electro-optical device including the driving circuit of the electro-optical device according to any one of the first to eighth aspects, and the electro-optical device. It is characterized by the following.
[0026]
According to the electro-optical device according to the ninth aspect, since the driving circuit for the electro-optical device according to any one of the first to eighth aspects is provided, the clock signal having the same phase and the anti-phase clock are provided. The signal allows the shift register of the driving means to operate reliably without malfunction, and a display on a liquid crystal device or the like, which is an example of the electro-optical device, can be favorably realized. Further, the clock signal phase difference correcting means for eliminating the phase difference is not provided at each stage of the shift register, but is provided between the supply unit of the clock signal or the opposite phase clock signal and the driving means. Therefore, the layout area of the shift register can be reduced, and as a result, high integration of peripheral circuits can be achieved. Therefore, a very small liquid crystal device having a high-definition electro-optical device is provided.
[0027]
According to a tenth aspect of the invention, there is provided an electronic apparatus including the electro-optical device according to the ninth aspect, in order to solve the problem.
[0028]
According to the electronic device of the tenth aspect, the electronic device includes the above-described electro-optical device according to the present invention, and can achieve a favorable display based on the clock signal having the same phase and the opposite phase clock signal. it can. Further, in the electro-optical device, a clock signal phase difference correction unit for eliminating the phase difference is not provided at each stage of the shift register, but an input unit for the clock signal or the opposite phase clock signal, Since the liquid crystal device is provided between the light emitting device and the driving means, a miniaturized liquid crystal device having a high-definition electro-optical device can reduce the size of an electronic device.
[0029]
The operation and other advantages of the present invention will become more apparent from the embodiments explained below.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0031]
(Configuration of liquid crystal device)
The configuration and operation of an embodiment of a liquid crystal device as an example of an electro-optical device according to the present invention will be described with reference to FIG. FIG. 1 is an equivalent circuit diagram showing a plurality of pixels of the liquid crystal device.
[0032]
First, as shown in FIG. 1, a plurality of pixels formed in a matrix and constituting a screen display area of the liquid crystal device according to the present embodiment have a plurality of switching elements, for example, TFTs 30 formed in a matrix, as shown in FIG. A data line 35 for supplying an image signal is electrically connected to the source of the TFT 30. The image signals to be written to the data lines 35 may be supplied to the respective data lines 35 in the order of S1, S2,..., Sn in a line-sequential manner. May also be supplied. A scanning line 31 for supplying a scanning signal is electrically connected to the gate of the TFT 30, and a scanning signal is applied to each of the scanning lines Y1, Y2,. The scan lines Y1, Y2,..., And Ym are configured to be applied in a line-sequential manner at the timing. The pixel electrode 11 is electrically connected to the drain of the TFT 30. By turning on the TFT 30 as a switching element for a predetermined period, a pixel signal supplied from the data line 35 is output at a predetermined timing. The data is written to the pixel electrode 11. An image signal of a predetermined level written in the liquid crystal via the pixel electrode 11 is held for a certain period between the image signal and a counter electrode (described later) formed on a counter substrate (described later). The liquid crystal modulates light by changing the orientation and order of a molecular group according to the applied voltage level, thereby enabling gray scale display.
[0033]
Such a liquid crystal device substrate may be provided with various peripheral circuits including a TFT, such as a scanning line driving circuit, a data line driving circuit, and a sampling circuit, in addition to the above-described components.
[0034]
For example, in the example shown in FIG. 1, a scanning line driving circuit 104 that supplies a scanning signal to the scanning line 31, a data line driving circuit 101 that supplies a driving signal to the sampling circuit 301, and an image signal that is turned on when the image signal is turned on. A sampling circuit 301 for supplying the line 35 is provided on the liquid crystal device substrate.
[0035]
The data line driving circuit 101 and the scanning line driving circuit 104 each include a shift register. The data line drive circuit 101 is configured so that a drive signal for writing an image signal to the data line 35 is sequentially output from each output stage of the shift register. Further, the scanning line driving circuit 104 is configured so that scanning signals to be written to the scanning lines 31 are sequentially output from each output stage of the shift register.
[0036]
Each of these shift registers includes a gate means such as a clocked inverter or a transmission gate at each stage, as will be described later, and a clock signal or a clock signal having an opposite phase to the clock signal (an opposite phase clock signal) is alternately provided for each stage. Signal), the drive signal for the data line or the scan line is sequentially transferred at a timing synchronized with a half cycle of the clock signal.
[0037]
As shown in FIG. 1, the liquid crystal device according to the present embodiment has CLX and CLX which are _INV A clock phase difference correction circuit 500 is provided between the data line driving circuit 101 and the driving means having a shift register, and a clock signal CLX and an antiphase clock signal CLX supplied from the external control circuit are provided. _INV Are adjusted by the clock phase difference correction circuit 500 and then supplied to the data line driving circuit 101.
[0038]
Similarly, in the scanning line driving circuit 104, CLY and CLY _INV A clock phase difference correction circuit 500 is provided between the scan line driving circuit 104 and a driving unit having a shift register, and the clock signal CLY and the antiphase clock signal CLY supplied from the external control circuit are provided. _INV Are adjusted by the clock phase difference correction circuit 500 and then supplied to the scanning line driving circuit 104.
[0039]
Therefore, a favorable operation of writing an image signal to each pixel is performed without causing a malfunction of the data line driving circuit 101 and the scanning line driving circuit 104. Hereinafter, the configuration and operation of the clock signal phase difference correction circuit of the present embodiment will be described in more detail.
[0040]
(Configuration of clock phase difference correction circuit)
In this embodiment mode, as shown in FIG. 1, a clock signal phase difference correction circuit 500 having a bistable circuit is provided on a liquid crystal device substrate, and a clock signal CL and an antiphase clock signal CL are provided. _INV Are configured to match the phases of
[0041]
The basic configuration of the clock signal phase difference correction circuit 500 of the present embodiment includes a first buffer circuit 501, a bistable circuit 502, and a second buffer circuit 503, as shown in FIG. Each circuit includes inverters 501a, 501b, 502a, 502b, 503a, and 503b.
[0042]
As shown in FIG. 2 (b), the clock signal CL has the opposite phase clock signal CL. _INV On the other hand, even if a phase difference occurs during the period T at the points R1 and R1, the phase difference is corrected by the bistable circuit 502 in the present embodiment, and the points R3 and R3 ′ output from the bistable circuit 502 are output. Does not cause a phase difference.
[0043]
In the clock signal phase difference correction circuit 500, in the buffer circuit 501 including the inverters 501a and 501b, the clock signal CL and the opposite-phase clock signal CL _INV The transistor in the circuit that supplies the input signal of the bistable circuit 502 supplies the output of one inverter 502a to the input of the other inverter 502b and the output of the other inverter 502b to the input of the one inverter 502a. , The input signals of the inverters 502a and 502b are positively fed back to eliminate the phase difference.
[0044]
In the clock signal phase difference correction circuit 500 of the present embodiment, the second buffer circuit 503 is provided after the bistable circuit 502, and the operation of the bistable circuit 502 is performed by the operation of the second buffer circuit 503. Prevents a decline in performance. In other words, the clock signal line and the antiphase clock signal CL _INV Is supplied, the clock signal CL and the antiphase clock signal CL _INV May be degraded. However, in the present embodiment, the lowering of the driving ability of the bistable circuit 502 is prevented by the second buffer circuit 503, and the clock signal CL and the opposite-phase clock signal CL are prevented. _INV Is satisfactorily supplied to each drive circuit.
[0045]
Further, in order to prevent signal deterioration due to the capacity of the clock signal line, a clock signal phase difference correction circuit may be provided at each stage of the shift register. And the second buffer circuit 503 is provided after the clock signal, the clock signal having a well-corrected phase difference and the reverse phase clock can be provided without providing a clock signal phase difference correction circuit for each of the latch circuits constituting the shift register. A signal can be supplied to the driving circuit. Therefore, the size of the liquid crystal device can be reduced without increasing the layout area of the driving circuit.
[0046]
A modified example of the configuration of the above-described clock phase difference correction circuit will be described with reference to FIGS.
[0047]
Each of the bistable circuits 502 in FIGS. 3A and 3B has the same configuration as that of the present embodiment shown in FIG. 2 except that each of the bistable circuits 502 includes NAND circuits 502c and 502d or NOR circuits 502e and 502f. It is.
[0048]
When the NAND circuits 502c and 502d shown in FIG. 3A are used, the clock signal CL and the opposite phase clock signal CL are used. _INV Due to the phase difference, even if there is a period in which both become high level signals or a period in which both become low level signals, after that, the clock signal CL or the opposite phase clock signal CL _INV , The outputs of the NAND circuits 502c and 502d change at the same time. For example, when the input signal d1 of the NAND circuit 502c is at a high level and d3 is at a low level, the output signal d2 of the NAND circuit 502c is at a high level, whereby the input signal d4 of the NAND circuit 502d is at a high level. Assuming that the input signal d6 is a high level signal, the output signal d5 of the NAND circuit 502d becomes a low level signal. In such a case, assuming that the output signal of the NAND circuits 502c and 502d changes from the initial state of each signal to the low-level signal, the output signal d5 of the NAND circuit 502d changes to the high level. Accordingly, the input signal d3 of the NAND circuit 502c also changes to the high level. Therefore, the output signal d2 of the NAND circuit 502c changes to low level, and the states of all signals are stabilized. Thus, the clock signal CL and the antiphase clock signal CL _INV Due to the phase difference described above, even if there is a period in which both become high level signals or a period in which both become low level signals, the output signals d2, d5 changes at the same time, and the clock signal CL and the opposite-phase clock signal _INV Can be eliminated.
[0049]
Further, as shown in FIG. 3B, even when the bistable circuit is constituted by the NOR circuits 502e and 502f, the circuit operates in the same manner as the NAND circuits 502c and 502d.
[0050]
As described above, by forming the bistable circuit 502 with a NAND circuit or a NOR circuit, the clock signal CL having no phase difference and the antiphase clock signal CL _INV Thus, a liquid crystal device which can drive the data line driver circuit 101 or the scan line driver circuit 104 and does not malfunction can be provided.
[0051]
(Detailed Configuration of Clock Signal Phase Difference Correction Circuit 500)
When the configuration as in the above-described embodiment is adopted, it is preferable that the on-resistance of the inverter circuits 503a and 503b of the second buffer circuit 503 shown in FIG. 4 be set to a value as low as possible. This is because if the on-resistance of the final-stage inverter circuits 503a and 503b is high, the output signal becomes dull, the voltage of the signal applied to the clocked inverter of the shift register 401 decreases, and the shift register 401 cannot be driven. It is. Therefore, it is necessary to design the inverter circuits 503a and 503b to have a sufficient driving capability with respect to the load and the driving frequency of the clock signal line electrically connected to the second buffer circuit 503.
[0052]
Further, the capacitive load of the signal transmission path constituted by the inverters A, B, C or A ', B', C 'shown in FIG. 4, and the signal transmission path constituted by the inverters A, C' or A ', C' It is preferable to design so that the capacity load becomes the same.
Therefore, it is preferable to design the inverters A, A ', B, B' to have substantially the same size. This is to ensure that the potential of one of the paths does not become dominant, and that the phase difference can be corrected reliably.
[0053]
Further, the inverter circuits 503a and 503b constituting the second buffer circuit 503 of the clock signal phase difference correction circuit 500 may be provided in one stage, and when the capacity added to the clock signal line and the opposite phase clock signal line is large, For example, as shown in FIG. 5, a configuration may be adopted in which several stages of inverter circuits are cascaded and then connected to a clock signal line and an antiphase clock signal line. At this time, the cascade-connected inverter circuits are designed to be about 2 to 4 times as large as the size of the preceding inverter circuit. In the case of a CMOS cascade, if the size of the next-stage inverter circuit electrically connected to the own-stage inverter circuit is set to be approximately e (2.72) times, the total size of the second buffer circuit 503 is increased. The delay time can be minimized (e times theorem). For example, in the example of FIG. 5, the inverter D (D ′) may be formed to have a size that is the size of the inverter C (C ′) × e (2.72). In addition, the inverter E (E ′) is preferably formed to have a size that is the size of the inverter D (D ′) × e (2.72). Further, at this time, it is preferable that the on-resistance of the final-stage inverter E (E ′) is formed so as to be as small as possible.
[0054]
(Configuration of drive circuit)
An example of a configuration of the clock signal phase difference correction circuit of the above embodiment and a data line driving circuit connected to the clock signal phase difference correction circuit will be described with reference to FIGS.
[0055]
As shown in FIG. 6, the data line driving circuit 101 includes a shift register 401, a buffer circuit 402, and a sampling circuit driving signal selection circuit 403.
[0056]
In this embodiment mode, the shift register 401 sequentially outputs a sampling circuit drive signal from each stage of the shift register 401 in a transfer direction corresponding to the direction from A to B shown in FIG. It has a function of supplying the signal to the sampling circuit 301 via the 402.
[0057]
Although the scanning line driving circuit 104 is not shown, the scanning line driving circuit 104 includes a shift register, a selection circuit, a buffer circuit, and the like similar to the data line driving circuit 101.
[0058]
The shift register 401 includes, for example, clocked inverters 130 and 132 and an inverter 131 as shown in FIG.
[0059]
The clocked inverter 130 has a function of taking in the start signal SPX supplied to the input signal line 107 in synchronization with the clock signal CLX. Further, the inverter 131 has a function of propagating the fetched signal as an output signal from the output signal line 108, and the clocked inverter 132 further includes a clock signal CLX and an opposite-phase clock signal CLX. _INV And a function of feeding back the output signal from the inverter 131 to the signal input side of the inverter 131 in synchronization with the control signal.
[0060]
Each stage of the latch circuit constituting the shift register 401 is constituted by a circuit obtained by combining the above-described clocked inverter and the inverter, and the clock signal input to the clocked inverter of the adjacent stage is the same as that of the preceding stage. Since the clock signal has a phase opposite to that of the clock signal, it is captured at the timing t0 shown in FIG. 7 in the first stage, and the output signal is captured in the second stage at the timing t1 which is shifted by a half cycle of the clock signal CLX. An output signal having the same width as the start signal SPX is obtained also at the stage. Hereinafter, in each stage, a signal is sequentially fetched at a timing shifted by a half cycle of the clock signal CLX and a signal having the same width as one cycle of the clock signal CLX is output. The transfer is performed at a timing shifted by a half cycle of CLX.
[0061]
Then, the pulse signal shifted by a half cycle of the clock signal CLX output from each stage as described above is shaped as a sampling circuit drive signal via the selection circuit 403 and the buffer circuit 402. The selection circuit 403 includes a NAND circuit as shown in FIG. 6, so that the output signal of the next output stage is input to the NAND circuit together with the output signal from the output stage of the corresponding shift register 401. It is configured. Therefore, for the TFT 302 of the sampling circuit 301, as shown in FIG. 7, during the period in which the output signals of the adjacent output stages are both at the high level, the pulse-shaped drive signals that are at the high level are in the order of Q1 to Qm. They will be output sequentially.
[0062]
In the present embodiment, since the data line driving circuit 101 as described above is provided, even if the dot frequency is very high, the clock signal CLX and the opposite-phase clock signal CLX supplied to the shift register 401 are provided. _INV Can be given a necessary and sufficient sampling period to each TFT 302 of the sampling circuit 301, and reliable writing of the image signals VID1 to VID6 to the data line 35 can be realized. Further, also in the scanning line driving circuit 104 configured in the same manner as the data line driving circuit 101, the scanning signal can be surely written to the scanning line 31, and as a result, a favorable display operation can be performed.
[0063]
(Configuration of liquid crystal device)
Next, a specific configuration example of a liquid crystal device including the above-described clock signal phase difference correction 500 will be described in detail with reference to FIGS. 8 and 9 are block diagrams each showing a configuration of various wirings, peripheral circuits, and the like provided on a liquid crystal device substrate in a liquid crystal device embodiment.
[0064]
8, the liquid crystal device 10 includes a liquid crystal device substrate 1 made of, for example, a quartz substrate, hard glass, a silicon substrate, or the like. On the liquid crystal device substrate 1, a plurality of pixel electrodes 11 arranged in a matrix, a plurality of data lines 35 arranged in the X direction, each extending in the Y direction, and a plurality of data electrodes 35 arranged in the Y direction. The scanning lines 31 each extending along the X direction and the conductive state and the non-conductive state between the data lines 35 and the pixel electrodes 11 are supplied through the scanning lines 31 respectively. And a plurality of TFTs 30 as an example of a pixel driving unit that controls each according to a scanning signal. Further, on the liquid crystal device substrate 1, a capacitance line 31 'which is a wiring for a storage capacitor is formed substantially in parallel along the scanning line 31 or by using a lower part of the preceding scanning line.
[0065]
The liquid crystal device substrate 1 further includes a precharge circuit 201 for supplying a precharge signal of a predetermined voltage level to the plurality of data lines 35 in advance of the image signal, and a plurality of data lines 35 for sampling the image signal. , A sampling circuit 301, a data line driving circuit 101, and a scanning line driving circuit 104 are provided.
[0066]
The scanning line driving circuit 104 includes a shift register, and includes a positive power supply VDDY and a negative power supply VSSY supplied from an external control circuit (not shown), a start signal SPY, a reference clock signal CLY, and a clock having an opposite phase. Signal CLY _INV Based on the above, a scanning signal is applied to the scanning line 31 line by line at a predetermined timing.
[0067]
Similarly, the data line driving circuit 101 includes a shift register, and includes a positive power supply VDDX and a negative power supply VSSX supplied from an external control circuit (not shown), a reference clock signal CLX, and a clock having an opposite phase. Signal CLX _INV In order to sample the image signals VID1 to VID6 based on the start signal SPX and the like, a sampling circuit drive signal is applied in a pulse-wise line-sequential manner for each data line 35. The sampling circuit drive signal is supplied via the sampling circuit drive signal line 306 at the timing when the scanning line drive circuit 104 applies the scan signal.
[0068]
The common electrode potential signal LCCOM is supplied to the upper and lower conductive members 106 and applied to the common electrode (not shown) formed on the opposite substrate (not shown) via the upper and lower conductive members 106 as described later. .
[0069]
Next, the precharge circuit 201 includes a TFT 202 for each data line 35, a precharge signal line 204 is connected to a source electrode of the TFT 202, and a precharge circuit drive signal line 206 is connected to a gate electrode of the TFT 202. It is connected. Then, power of a predetermined voltage required for writing the precharge signal NRS is supplied from an external power supply via a precharge signal line 204, and an image signal is supplied to each data line 35 via a precharge circuit drive signal line 206. The precharge circuit drive signal NRG is supplied from an external control circuit so that the precharge signal NRS is written at a timing preceding the precharge circuit drive signal NRS. The precharge circuit 201 preferably supplies a precharge signal (image auxiliary signal) corresponding to an image signal of an intermediate gradation level.
[0070]
The sampling circuit 301 includes a TFT 302 for each data line 35, and an image signal line 304 is connected to a source electrode of the TFT 302. A sampling circuit drive signal line 306 is connected to a gate electrode of the TFT 302. Accordingly, the TFT 302 to which the sampling circuit drive signal is input from the data line drive circuit 101 via the sampling circuit drive signal line 306 becomes conductive, and is supplied from an external control circuit (not shown) via the image signal line 304. The image signals VID1 to VID6 are written to each data line 35.
[0071]
In the present embodiment, the sampling circuit drive signal is simultaneously applied to the gate electrodes of the six adjacent TFTs 302, and the plurality of data lines 35 are sequentially selected for each group. The image signal is input to an external control circuit as a serial signal having a predetermined dot frequency, and is expanded into six-phase parallel signals in the external control circuit, and is converted into six image signals VID1 to VID6 via the TFT 302 as data signals. 35.
[0072]
The reason why the image signals are phase-expanded using the plurality of image signal lines 304 is to reduce the driving frequency of the shift register even when the dot frequency of the image signals is high. If the drive frequency of the shift register can be reduced, the load on an external control circuit that supplies a clock signal to the shift register can be reduced, and the current consumption of the shift register can be reduced. Further, the life of the TFT constituting the shift register can be extended.
[0073]
The number of phase expansions of the image signal is determined by the writing capability of the TFT 302 included in the sampling circuit 301. Although the number of phase expansions of the image signal is not limited, there is an advantage that a smaller number of phase expansions of the image signal can reduce the cost of the external control circuit. Also, the number of TFTs 302 selected at the same time does not necessarily have to be equal to the number of phase expansions of the image signal, and may be smaller than the number of phase expansions.
[0074]
Further, if the number of phase expansions of the image signal is set to a multiple of 3, such as 3, 6, 12, 18, 24, or ‥‥, the image signal line 304 can be formed in a multiple of 3, which is advantageous for video display. is there. This is because the color image signal is a multiple of 3 because of the fact that the color image signal is composed of signals related to three colors (red, green, and blue) when controlling video display such as NTSC display and PAL display. This is because it is preferable for simplifying the circuit. Needless to say, the image signal lines 304 are required at least for the number of phase expansions of the image signal.
[0075]
Then, in the liquid crystal device 10 of the present embodiment configured as described above, the clock signal phase difference correction circuit 500 having the above configuration is connected to the clock signal CL and the opposite phase clock signal as shown in FIG. CL _INV Are provided between the data line driving circuit 101 and the scanning line driving circuit 104. The location of the clock signal phase difference correction circuit 500 is not limited to the example shown in FIG. FIG. 9 shows another configuration example of the liquid crystal device. 9 has almost the same configuration as that of FIG. 8, except that the scanning line driving circuit 104 is provided on both sides of the scanning line 31, and the scanning line driving circuit 104 on one side and the clock signal CLY have opposite phases. Clock signal CLY _INV A clock signal phase difference correction circuit 500a is provided between the clock signal phase difference correction circuit 500 a _INV The clock signal phase difference correction circuit 500b is provided between each of the input sections. With this configuration, it is possible to more reliably prevent the timing of the scanning signals supplied from the left and right scanning line driving circuits 104 to the scanning lines 31 from being shifted.
[0076]
As described above, the clock signal CLX and its opposite phase clock signal CLX _INV Between the input part of the data line driving circuit 101 and the clock signal CLY and its opposite phase clock signal CLY _INV In the configuration in which the clock signal phase difference correction circuit 500 is provided at one location between the clock signal phase difference correction circuit 500 and the data line drive circuit 101 and the scan line drive circuit 104, When the clock signal line is extended for a long time, the signal may be deteriorated due to the capacity of the clock signal line.
[0077]
However, as described above, the clock signal phase difference correction circuit 500 of the present embodiment includes the second buffer circuit 503 at a stage subsequent to the bistable circuit 502, and furthermore, the second buffer circuit has an appropriate size. Therefore, even when the clock signal phase difference correction circuit 500 is arranged as in the present embodiment, the driving capability of the clock signal phase difference correction circuit 500 does not decrease, and the phase matching of the clock signal is ensured. Can be done. Hereinafter, a detailed configuration of the clock signal phase difference correction circuit 500 according to the present embodiment will be described. Note that the clock signal phase difference correction circuits 500a and 500b shown in FIG. 9 have the same configuration as the clock signal phase difference correction circuit 500.
[0078]
As an example at the time of pattern layout, if the routing resistance of the clock signal having the opposite phase to the clock signal changes, a phase difference occurs between the signals. Therefore, a polysilicon film having high resistance (formed of the same film as the scanning line) is used. The wiring to be routed has the same width and length so that both the clock signal and the opposite phase clock signal have substantially the same resistance, and the portion where the wiring length changes is a low-resistance aluminum film (formed of the same film as the data line). It is preferable that the wires are routed. Accordingly, since there is no resistance difference between the wirings, the phase difference between the clock signal input from the outside and the opposite phase clock signal can be substantially equalized, and a liquid crystal device free from malfunction can be provided.
[0079]
For example, FIG. 10 is a diagram showing an example of a pattern layout of the clock signal phase difference correction circuit 500 shown in FIG. _INV A, a with a high resistance polysilicon film (for example, formed of the same film as the scanning line) for supplying the inverters A, A ', B, B', C, C ', D, D' , B, b ', c, c', d, and d 'have the same line width and length for each inverter, and have a clock signal CL and an opposite-phase clock signal CL. _INV It is configured so as not to change the routing resistance. Further, the portions e1 to e8 where the length of the wiring is changed are configured to be routed by a low-resistance aluminum film (for example, formed of the same film as the data line) or the like, so that a resistance difference in the wiring does not occur.
[0080]
As for the size of each inverter, as shown in FIG. 10, the inverters A, A ', B, and B' are formed to have the size of the width w1 and the length h1, but the inverters C and C 'at the next stage. Is formed to have a width w1 and a length h2 (> h1) and a size larger than the inverters A, A ', B and B'. Further, the next-stage inverters D and D7 'have a width w2 (> w1), a length h1 and a size larger than the inverters C and C'. In this way, the inverter circuits connected in cascade are designed to be approximately two to four times as large as the inverter circuit of the preceding stage.
[0081]
With the above-described configuration, even when the clock signal phase difference correction circuit 500 is provided between the data line driving circuit 101 or the scanning line driving circuit 104 and the input section of the clock signal and the opposite phase clock signal, the positive feedback effect is obtained. The clock signal CL and the opposite-phase clock signal CL having the phase difference T as shown in FIG. _INV Is supplied, the clock signal and the opposite-phase clock signal having no phase difference can be output from the supply lines R3 and R3 'on the second buffer circuit 503 side.
[0082]
Further, the clock signal phase difference correction circuit 500 can be installed at a corner portion or the like of the liquid crystal device 10 and can reduce the size of the liquid crystal device 10 without increasing the layout area of the data line driving circuit 101 and the scanning line driving circuit 104. Can be realized. In particular, in the case of a configuration in which feedback is performed by a bistable circuit as in the clock signal phase difference correction circuit of the present embodiment, an inverter circuit having a complementary TFT structure is required, and the inverter circuit having a complementary TFT structure is required to have a positive polarity. Power supply and negative power supply need to be routed. However, in the present embodiment, such a circuit requiring a relatively large occupation area on the liquid crystal device substrate 1 is placed in a corner portion of the liquid crystal device 10 which does not affect the arrangement of the peripheral circuits. It can be installed and does not hinder high integration of peripheral circuits. Therefore, according to the present embodiment, it is possible to provide a small liquid crystal device which does not malfunction and incorporates a highly integrated peripheral circuit.
[0083]
Further, as shown in FIG. 9, even when the clock signal is supplied to each of the two scanning line driving circuits 104 by the clock signal phase difference correction circuits 500a and 500b, both the clock signal phase difference correction circuits 500a and 500b perform scanning. Since it can be provided at a position that does not affect the arrangement of the line drive circuit 104, high integration of the scan line drive circuit 104 is not hindered.
[0084]
When a clock signal is supplied not only to the scanning line driving circuit 104 but also to a plurality of driving circuits, a clock signal phase difference correction circuit of the present invention is provided so that phase correction can be performed before each driving circuit. Just do it. Accordingly, it is possible to prevent a shift of a signal output from each drive circuit.
[0085]
In the present embodiment, the shift register in each drive circuit is a single line. However, when a plurality of lines of shift registers are used, the number of clock signal phase difference correction circuits corresponding to the number of lines is required. It is necessary to provide. That is, when an N (N = 1, 2,...) Series shift register is used, N clock signal phase difference correction circuits may be provided. With such a configuration, malfunction can be prevented in all the series of shift registers.
[0086]
Further, the present invention can exert wide effects not only on the shift register operation of the data line driving circuit 101 or the scanning line driving circuit but also on a circuit which drives a certain signal using its inverted signal.
[0087]
Note that the clock signal phase difference correction circuit, the data line driving circuit, the sampling circuit, or the scanning line driving circuit as described above can be formed in the same thin film forming step as that of the TFT 30 in the pixel region. It is advantageous.
[0088]
(Configuration of liquid crystal device)
FIGS. 12 and 13 show an example of the liquid crystal device 10 in which the above-described liquid crystal device substrate and the counter substrate are attached to each other. FIG. 12 is a plan view of the entire liquid crystal device, and FIG. 13 is a sectional view taken along line HH ′ of FIG. As shown in FIGS. 12 and 13, the precharge circuit 201 and the sampling circuit 301 are provided on the liquid crystal device substrate 1 at positions facing the light-shielding peripheral partition 53 formed on the counter substrate 2. The data line driving circuit 101 and the scanning line driving circuit 104 are provided on a narrow and elongated peripheral portion of the liquid crystal device substrate 1 which does not face the liquid crystal layer 50.
[0089]
12 and 13, on the liquid crystal device substrate 1, a screen display region defined by a plurality of pixel electrodes 11 (that is, a liquid crystal device in which an image is actually displayed by a change in the alignment state of the liquid crystal layer 50). A seal member 52 made of a photo-curable resin and surrounding the liquid crystal layer 50 by bonding both substrates around the (region) is provided along the screen display region. A light-shielding peripheral partition 53 is provided between the screen display area on the counter substrate 2 and the sealing material 52.
[0090]
When the liquid crystal device substrate 1 is later placed in a light-shielding case provided with an opening corresponding to the screen display area, the peripheral parting 53 has an edge of the opening of the case due to a manufacturing error or the like. In order not to be hidden behind, that is, for example, to allow a displacement of about several hundred μm with respect to the case of the liquid crystal device substrate 1, a band-shaped light-shielding material having a width of at least 500 μm or more around the screen display area is used. It was formed. Such a light-shielding peripheral partition 53 is formed on the counter substrate 2 by, for example, sputtering, photolithography, and etching using a metal material such as Cr (chromium) or Ni (nickel). Alternatively, it is formed from a material such as resin black in which carbon or Ti (titanium) is dispersed in a photoresist. Further, the light-shielding peripheral partition 53 and the light-shielding layer 23 may be formed on the liquid crystal device substrate 1. With such a configuration, since the bonding accuracy of the liquid crystal device substrate 1 and the counter substrate 2 can be ignored, there is an advantage that the transmittance of the liquid crystal device does not vary.
[0091]
A data line driving circuit 101 and a mounting terminal 102 for inputting a signal from the outside are provided along a lower side of the screen display area in a region outside the sealing material 52, and two left and right sides of the screen display area are provided. The scanning line driving circuit 104 is provided along both sides of the screen display area. Here, when the driving delay of the scanning line 31 does not cause a problem, the scanning line driving circuit 104 may be formed on only one side with respect to the scanning line 31 or the data driving circuit 101 may be formed above and below the screen display area. It may be provided on both sides along two sides. At this time, for example, an odd-numbered column data line is electrically connected to one data line driving circuit 101 and an even-numbered column data line is electrically connected to the other data line driving circuit 101, so that the upper and lower lines are electrically connected. May be driven in a comb shape. Further, on the upper side of the screen display area, a plurality of wirings 105 for supplying power and a driving signal to the scanning line driving circuit 104 are provided. At least one corner of the counter substrate 2 is provided with a vertical conductive member 106 for establishing electrical connection between the liquid crystal device substrate 1 and the counter substrate 2. The opposite substrate 2 having substantially the same contour as the sealing material 52 is fixed to the liquid crystal device substrate 1 by the sealing material 52.
[0092]
In each of the above-described embodiments, a case where an external control circuit that outputs a clock signal, an image signal, or the like to the data line driving circuit 101 and the scanning line driving circuit 104 is provided outside the liquid crystal device will be described. However, the present invention is not limited to this, and the control circuit may be provided in the liquid crystal device.
[0093]
In particular, with respect to the clock signal, only the clock signal may be supplied from an external control circuit, and a circuit for generating an opposite-phase clock signal on the liquid crystal device substrate may be provided.
[0094]
The liquid crystal device 10 described above can be applied to a color liquid crystal projector or the like. In this case, three liquid crystal devices 10 are used as RGB light valves, respectively, and each panel has an RGB color separation device. The light of each color decomposed via the dichroic mirror is incident as incident light. Therefore, in each embodiment, the counter substrate 2 is not provided with a color filter. However, in the liquid crystal device 10 as well, an RGB color filter may be formed on the opposing substrate 2 together with its protective film in a predetermined region facing the pixel electrode 11 where the light-shielding layer 23 is not formed. In this way, the liquid crystal device of the present embodiment can be applied to a color liquid crystal device such as a direct-view or reflection type color liquid crystal television other than the liquid crystal projector.
[0095]
Further, the switching element used in the liquid crystal device may be a normal stagger type or coplanar type polysilicon TFT, and the present embodiment is applicable to other types of TFTs such as an inverse stagger type TFT and an amorphous silicon TFT. It is valid.
[0096]
Further, in the liquid crystal device, as an example, the liquid crystal layer 50 is formed of a nematic liquid crystal. However, if a polymer dispersed liquid crystal in which the liquid crystal is dispersed as fine particles in a polymer is used, an alignment film, and the above-described polarizing film, Since a polarizing plate or the like is not required, the advantages of higher luminance and lower power consumption of the liquid crystal device due to an increase in light use efficiency can be obtained.
[0097]
Note that the data line drive circuit 101 and the scan line drive circuit 104 are not provided on the liquid crystal device substrate 1 but are provided on a drive LSI mounted on, for example, a TAB (tape automated bonding substrate). 1 may be electrically and mechanically connected via an anisotropic conductive film provided in a peripheral portion.
[0098]
Although the configuration of the scan line driver circuit 104 is not described in detail in the above-described embodiment, a configuration similar to that of the data line driver circuit 101 can be employed particularly for a shift register portion.
[0099]
(Electronics)
Next, an embodiment of an electronic apparatus including the liquid crystal device 10 described in detail above will be described with reference to FIGS.
[0100]
First, FIG. 14 shows a schematic configuration of an electronic apparatus including the liquid crystal device 10 as described above.
[0101]
In FIG. 14, an electronic apparatus includes a display information output source 1000, a display drive circuit 1004 including the above-described external display information processing circuit 1002, the above-described scan line drive circuit 104 and the data line drive circuit 101, a liquid crystal device 10, a clock generation circuit. 1008 and a power supply circuit 1010. The display information output source 1000 is configured to include a ROM (Read Only Memory), a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit for tuning and outputting a television signal, and the like. Display information such as an image signal in a predetermined format is output to the display information processing circuit 1002 based on the clock signal. The display information processing circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit. Digital signals are sequentially generated from the input display information based on the display information and output to the display drive circuit 1004 together with the clock signal CLK. The display driving circuit 1004 drives the liquid crystal device 10 by the scanning line driving circuit 104 and the data line driving circuit 101 by the driving method described above. The power supply circuit 1010 supplies a predetermined power to each of the above-described circuits. Note that the display driving circuit 1004 may be mounted on a liquid crystal device substrate included in the liquid crystal device 10, and in addition, a display information processing circuit 1002 may be mounted.
[0102]
As an electronic apparatus having such a configuration, a liquid crystal projector shown in FIG. 15, a multimedia-compatible personal computer (PC) and an engineering workstation (EWS) shown in FIG. 16, or a mobile phone, a word processor, a television, a viewfinder type or Examples include a monitor direct-view video tape recorder, an electronic organizer, an electronic desk calculator, a car navigation device, a POS terminal, and a device having a touch panel.
[0103]
Next, FIGS. 15 to 17 show specific examples of the electronic device configured as described above.
[0104]
In FIG. 15, a liquid crystal projector 1100, which is an example of an electronic apparatus, is a projection type liquid crystal projector, and includes a light source 1110, dichroic mirrors 1113, 1114, reflection mirrors 1115, 1116, 1117, an incident lens 1118, a relay lens 1119, It comprises an emission lens 1120, liquid crystal light valves 1122, 1123, 1124, a cross dichroic prism 1125, and a projection lens 1126. The liquid crystal light valves 1122, 1123, and 1124 are prepared by preparing three liquid crystal display modules each including the liquid crystal device 10 in which the above-described drive circuit 1004 is mounted on a liquid crystal device substrate, and using them as liquid crystal light valves. The light source 1110 includes a lamp 1111 such as a metal halide and a reflector 1112 that reflects light from the lamp 1111.
[0105]
In the liquid crystal projector 1100 configured as described above, the dichroic mirror 1113 that reflects blue light and green light transmits red light of the white light flux from the light source 1110 and reflects blue light and green light. . The transmitted red light is reflected by the reflection mirror 1117 and is incident on the liquid crystal light valve 1122 for red light. On the other hand, among the color lights reflected by the dichroic mirror 1113, green light is reflected by the dichroic mirror 1114 that reflects green light, and is incident on the liquid crystal light valve 1123 for green light. The blue light also passes through the second dichroic mirror 1114. For blue light, in order to prevent light loss due to a long optical path, light guiding means 1121 composed of a relay lens system including an entrance lens 1118, a relay lens 1119, and an exit lens 1120 is provided. The light enters the liquid crystal light valve for light 1124. The three color lights modulated by the respective light valves enter the cross dichroic prism 1125. This prism is formed by bonding four right-angle prisms, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface. The three color lights are combined by these dielectric multilayer films to form light representing a color image. The synthesized light is projected on a screen 1127 by a projection lens 1126 which is a projection optical system, and an image is enlarged and displayed.
[0106]
In FIG. 16, a laptop personal computer 1200 as another example of the electronic apparatus includes a liquid crystal display 1206 in which the above-described liquid crystal device 10 is provided in a top cover case, a CPU, a memory, a modem, and the like. And a main body 1204 in which the main body 1202 is incorporated.
[0107]
As shown in FIG. 17, a TCP (Tape) in which an IC chip 1324 is mounted on a polyimide tape 1322 on which a metal conductive film is formed on one of two transparent substrates 1304a and 1304b constituting a liquid crystal device substrate 1304. Carrier Package) 1320 can be connected to produce, sell, and use a liquid crystal device as one component of an electronic device.
[0108]
As described above, in addition to the electronic devices described with reference to FIGS. 15 to 17, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic organizer, a calculator, a word processor, a workstation, and a mobile phone A telephone, a videophone, a POS terminal, a device having a touch panel, and the like are examples of the electronic device shown in FIG.
[0109]
It should be noted that the present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, the present invention is not limited to being applied to the driving of the various liquid crystal devices described above, but is also applicable to electroluminescence and plasma display devices.
[0110]
As described above, according to the present embodiment, it is possible to prevent an increase in the layout area of the drive circuit while correcting so as to surely eliminate the phase difference between the clock signal and the opposite-phase clock signal. Therefore, it is possible to realize an ultra-small liquid crystal device in which the peripheral driving circuit is built in the same substrate as the pixel TFT and in which the pixels are fine and high definition, and various electronic devices including the liquid crystal device.
[0111]
【The invention's effect】
As described above, according to the driving circuit of the electro-optical device of the present invention, the clock signal phase difference correcting means is provided at least between the clock signal supply line and the data line or scanning line driving means. Since the phase difference correcting means is provided, it is possible to eliminate a phase difference between the clock signal and the opposite phase clock signal, thereby preventing a malfunction of the driving means. Also, the clock signal phase difference correcting means is provided not at every stage of the shift register of the driving means but at least between the clock signal supply line and the driving means, so that the peripheral circuit can be highly integrated. And a driving circuit for the electro-optical device with high definition and small size can be provided.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram showing a plurality of pixels of a liquid crystal device according to an embodiment of the present invention.
2A is a circuit diagram showing a configuration of a clock signal phase difference correction circuit in the liquid crystal device of FIG. 1, and FIG. 2B is a diagram showing a signal waveform at each position in the circuit of FIG.
3A and 3B are circuit diagrams illustrating a configuration of a clock signal phase difference correction circuit in the liquid crystal device of FIG. 1, wherein FIG. 3A illustrates a case where all inverter circuits are used, and FIG. 3B illustrates a case where a NAND circuit is used as a feedback unit; And (c) is a circuit diagram when a NOR circuit is used for the feedback section.
FIG. 4 is a circuit diagram for explaining a load capacitance of each signal path in the clock signal phase difference correction circuit.
FIG. 5 is a circuit diagram in a case where a second buffer circuit is configured by a multi-stage inverter circuit in the clock signal phase difference correction circuit.
FIG. 6 is a circuit diagram showing a configuration of a data line drive circuit in the liquid crystal device of FIG.
FIG. 7 is a timing chart showing operations of the data line driving circuit and the sampling circuit of FIG.
FIG. 8 is a block diagram of various wirings, peripheral circuits, and the like in an example of the liquid crystal device substrate of the present invention.
FIG. 9 is a block diagram of various wirings, peripheral circuits, and the like in another example of the liquid crystal device substrate of the present invention.
FIG. 10 is a diagram illustrating an example of a pattern layout of a clock signal phase difference correction circuit of the liquid crystal device in FIG. 8;
FIG. 11 is a circuit diagram showing a clock signal phase difference correction circuit configured by the pattern layout of FIG. 9;
FIG. 12 is a plan view showing the overall configuration of the liquid crystal device of FIG.
FIG. 13 is a cross-sectional view illustrating the overall configuration of the liquid crystal device of FIG.
FIG. 14 is a block diagram illustrating a schematic configuration of an electronic device according to an embodiment of the present invention.
FIG. 15 is a cross-sectional view illustrating a liquid crystal projector as an example of an electronic apparatus.
FIG. 16 is a front view illustrating a personal computer as another example of the electronic apparatus.
FIG. 17 is a perspective view illustrating a liquid crystal display device using TCP as an example of an electronic apparatus.
18A is a circuit diagram illustrating a configuration of a conventional clock signal phase difference correction circuit, and FIG. 18B is a diagram illustrating a signal waveform at each position in the circuit of FIG.
FIG. 19 is an equivalent circuit diagram showing a plurality of pixels of a conventional liquid crystal device.
[Explanation of symbols]
1) Substrate for liquid crystal device
2 ‥‥ Counter substrate
10 ‥‥ liquid crystal device
11 ‥‥ pixel electrode
21 mm common electrode
23 ‥‥ Shading layer
30 ‥‥ TFT
31 ° scanning line
35 ‥‥ data line
50 ° liquid crystal layer
52 ‥‥ sealing material
53 ‥‥ Surrounding
101 ‥‥ data line drive circuit
102 ‥‥ mounting terminal
130, 132 ‥‥ clocked inverter
201 ‥‥ precharge circuit
204 ‥‥ precharge signal supply line
206 ‥‥ Precharge circuit drive signal line
301 ‥‥ sampling circuit
304 ‥‥ image signal line
306 ‥‥ Sampling circuit drive signal line
401 ‥‥ shift register
402 ‥‥ buffer circuit
403 ‥‥ selection circuit
500 ° clock signal phase difference correction circuit
501 ‥‥ First buffer circuit
502 ‥‥ bistable circuit
503 ‥‥ 2nd buffer circuit

Claims (10)

A plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, switching means connected to the data lines and the scanning lines, and a pixel electrode connected to the switching means A driving circuit for an electro-optical device comprising:
A driving unit having a shift register that transfers a predetermined signal based on a clock signal and a clock signal having a phase opposite to the clock signal;
An input from an input unit that supplies the clock signal and the clock signal of the opposite phase to the driving unit, respectively, is supplied to the driving unit via a clock signal phase difference correcting unit. Drive circuit for optical device. The clock signal phase difference correction unit is connected to an input unit of the clock signal and the input unit of the clock signal of the opposite phase, respectively, and each output unit of first and second logic units for inverting the polarity of the input signal, A signal feedback means connected to the other input section, and signal propagation means connected to respective output sections of the first and second logic means of the signal feedback means. Item 2. A driving circuit for an electro-optical device according to item 1. 3. The driving circuit for an electro-optical device according to claim 1, wherein a capacitance value of at least two wires of the clock signal phase difference correction unit is substantially constant. The clock signal phase difference correcting means includes a first buffer circuit for transmitting a signal to the signal feedback means, a bistable circuit as the signal feedback means, and a second buffer circuit as the signal propagation means. 4. A driving circuit for an electro-optical device according to claim 2, wherein the driving circuit comprises: The driving circuit for an electro-optical device according to claim 4, wherein the bistable circuit is formed by a NAND circuit. 5. The driving circuit according to claim 4, wherein the bistable circuit is formed by a NOR circuit. The driving means are provided at both ends of the data line or the scanning line, respectively, and the clock signal phase difference correcting means is independently provided between a clock signal input portion and the respective driving means. The driving circuit for an electro-optical device according to claim 1, wherein the driving circuit is provided. The shift register is a shift register driven in an N (1, 2, 3,...) Sequence, and N clock signal phase difference correction means are provided corresponding to each shift register. The driving circuit for an electro-optical device according to claim 1, wherein: An electro-optical device comprising a drive circuit for the electro-optical device according to claim 1. An electronic apparatus comprising the electro-optical device according to claim 9.

Images