[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

TWI646665B - 具有抹除元件的單層多晶矽非揮發性記憶胞結構 - Google Patents

具有抹除元件的單層多晶矽非揮發性記憶胞結構 Download PDF

Info

Publication number
TWI646665B
TWI646665B TW106104042A TW106104042A TWI646665B TW I646665 B TWI646665 B TW I646665B TW 106104042 A TW106104042 A TW 106104042A TW 106104042 A TW106104042 A TW 106104042A TW I646665 B TWI646665 B TW I646665B
Authority
TW
Taiwan
Prior art keywords
oxide
region
doped region
floating gate
memory cell
Prior art date
Application number
TW106104042A
Other languages
English (en)
Other versions
TW201824520A (zh
Inventor
孫文堂
陳緯仁
陳英哲
Original Assignee
力旺電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力旺電子股份有限公司 filed Critical 力旺電子股份有限公司
Publication of TW201824520A publication Critical patent/TW201824520A/zh
Application granted granted Critical
Publication of TWI646665B publication Critical patent/TWI646665B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一種單層多晶矽非揮發性記憶胞結構，包含一矽覆絕緣基板，包含一矽基底、一埋入氧化層及一半導體層；一第一氧化物定義區域及一第二氧化物定義區域，位於該半導體層；一絕緣區域，位於該半導體層，隔離該第一氧化物定義區域與該第二氧化物定義區域；一PMOS選擇電晶體，設於該第一氧化物定義區域；一PMOS浮置閘極電晶體，設於該第一氧化物定義區域，並串接該PMOS選擇電晶體，該PMOS浮置閘極電晶體包含一浮置閘極，位於該第一氧化物定義區域上；以及一浮置閘極延伸，由該浮置閘極連續延伸至該第二氧化物定義區域，並與該第二氧化物定義區域電容耦合。

Description

具有抹除元件的單層多晶矽非揮發性記憶胞結構
本發明係有關於非揮發性記憶體(nonvolatile memory)技術領域，特別是有關於一種具有抹除元件(erase device)且設於矽覆絕緣(SOI)基板上的單層多晶矽非揮發性記憶胞結構。
單層多晶矽非揮發性記憶體乃週知技藝。第1圖例示一單層多晶矽非揮發性記憶胞的佈局示意圖。如第1圖所示，單層多晶矽非揮發性記憶胞10包含兩個串接在一起的PMOS電晶體12及14。PMOS電晶體12包含一選擇閘極22、一P+源極摻雜區32，及一P+汲極/源極摻雜區34。PMOS電晶體14包含一浮置閘極24、P+汲極/源極摻雜區34，及一P+汲極摻雜區36。串接在一起的PMOS電晶體12及14共用P+汲極/源極摻雜區34。上述單層多晶矽非揮發性記憶胞10的優點是可以完全與CMOS邏輯製程相容。
操作時，PMOS電晶體12的選擇閘極22係耦合至一選擇閘極電壓VSG，P+源極摻雜區32係經由一源極線接觸件耦合至一源極線電壓VSL，P+汲極/源極摻雜區34及PMOS電晶體14的浮置閘極24為電性上浮置，而PMOS電晶體14的P+汲極摻雜區36則是經由一位元線接觸件耦合至位元線電壓VBL。在寫入模式下，電子被注入並儲存在浮置閘極24中。上述記憶體結構可以在低電壓條件下操作。
由於單層多晶矽非揮發性記憶體能與CMOS邏輯製程相容，因此被廣泛應用在許多領域，例如嵌入式記憶體、混合訊號電路或微控制器(如系統單 晶片)等等的嵌入式非揮發性記憶體。
目前的趨勢是將非揮發性記憶體越做越小。隨著非揮發性記憶體越做越小，可期待記憶體的單位元成本(cost per bit)也會降低。然而，過去的非揮發性記憶體的微縮能力受限於離子佈植輸出/輸入離子井(I/O ion well)的規則，其中植入基底記憶陣列區中的輸出/輸入離子井的接面深度深於淺溝絕緣結構(STI)的深度。
本發明的主要目的在提供一改良的單層多晶矽非揮發性記憶胞結構，特徵是具有一抹除元件且形成在一矽覆絕緣基板上，以解決先前技藝的不足與缺點。
本發明的主要目的在提供一改良的單層多晶矽可多次寫入(MTP)非揮發性記憶胞，其具有更小的記憶胞尺寸。
根據本發明一實施例，提供一種單層多晶矽非揮發性記憶胞結構，包含一矽覆絕緣(SOI)基板，包含一矽基底、一埋入氧化層及一半導體層；一第一氧化物定義區域及一第二氧化物定義區域，位於該半導體層；一絕緣區域，位於該半導體層，該絕緣區域隔離該第一氧化物定義區域與該第二氧化物定義區域；一PMOS選擇電晶體，設於該第一氧化物定義區域；一PMOS浮置閘極電晶體，設於該第一氧化物定義區域，並串接該PMOS選擇電晶體，其中該PMOS浮置閘極電晶體包含一浮置閘極，位於該第一氧化物定義區域上；以及一浮置閘極延伸，由該浮置閘極連續地延伸至該第二氧化物定義區域，並與該第二氧化物定義區域電容耦合。
其中該PMOS選擇電晶體包含一選擇閘極、一選擇閘極氧化層，介於該選擇閘極與該半導體層之間、一P+源極摻雜區，及一P+汲極/源極摻雜區，其中 該P+源極摻雜區耦合至一源極線。
其中該PMOS浮置閘極電晶體包含該浮置閘極、一浮置閘極氧化層，介於該浮置閘極與該半導體層之間、該P+汲極/源極摻雜區，及一P+汲極摻雜區，其中該PMOS選擇電晶體與該PMOS浮置閘極電晶體共用該P+汲極/源極摻雜區。
根據本發明一實施例，該單層多晶矽非揮發性記憶胞結構另包含一離子井，例如N型井或P型井，位於該半導體層，其中該離子井完全重疊該第二氧化物定義區域，以及一重摻雜區域，例如N+摻雜區或P+摻雜區，位於該第二氧化物定義區域內的該離子井中。該第二氧化物定義區域、該重摻雜區域、該浮置閘極氧化層，及與該重摻雜區域電容耦合的該浮置閘極延伸，共同構成一抹除元件。
根據本發明一實施例，該單層多晶矽非揮發性記憶胞結構另包含一電荷收集區域，與該第一氧化物定義區域接壤，其中電荷收集區域在該單層多晶矽非揮發性記憶體操作時收集累積在該半導體層中的多餘電子及電洞。其中該電荷收集區域包含一第三氧化物定義區域、一N+摻雜區位於該第三氧化物定義區域內，及一橋接區域，連接該N+摻雜區與該浮置閘極正下方的該半導體層。
根據本發明另一實施例，該單層多晶矽非揮發性記憶胞結構另包含一N+摻雜區，其與該P+源極摻雜區接壤，該N+摻雜區與該P+源極摻雜區位於該選擇閘極同一側，如此構成一毗接接觸區。
1、2、3、4、5、6‧‧‧單層多晶矽非揮發性記憶體
10‧‧‧單層多晶矽非揮發性記憶胞
12‧‧‧PMOS電晶體
14‧‧‧PMOS電晶體
22‧‧‧選擇閘極
24‧‧‧浮置閘極
32‧‧‧P+源極摻雜區
34‧‧‧P+汲極/源極摻雜區
36‧‧‧P+汲極摻雜區
50‧‧‧電荷收集區域
60‧‧‧毗接接觸區
102‧‧‧PMOS選擇電晶體
104‧‧‧PMOS浮置閘極電晶體
110‧‧‧選擇閘極
112‧‧‧選擇閘極氧化層
120‧‧‧浮置閘極
120a、120b‧‧‧延伸部(浮置閘極延伸)
122‧‧‧浮置閘極氧化層
132‧‧‧P+源極摻雜區
134‧‧‧P+汲極/源極摻雜區
136‧‧‧P+汲極摻雜區
138‧‧‧重摻雜區域
162‧‧‧N+摻雜區
200‧‧‧矽覆絕緣(SOI)基板
210‧‧‧矽基板
220‧‧‧埋入氧化層
230‧‧‧半導體層
250、450‧‧‧抹除元件
300‧‧‧淺溝絕緣(STI)區域
310‧‧‧N型井
320‧‧‧離子井
500‧‧‧N+摻雜區
510‧‧‧字元線接觸點
520‧‧‧橋接區域
VSG‧‧‧選擇閘極電壓
VSL‧‧‧源極線電壓
VBL‧‧‧位元線電壓
VNW‧‧‧N型井電壓
C1~C4‧‧‧記憶胞單元
OD1、OD2、OD3、OD4‧‧‧氧化物定義區域
WL1、WL2‧‧‧字元線
SL‧‧‧源極線
BL‧‧‧位元線
EL‧‧‧抹除線
第1圖例示一單層多晶矽非揮發性記憶胞的佈局示意圖。
第2圖為依據本發明一實施例所繪示的單層多晶矽非揮發性記憶體的部分佈局示意圖。
第3圖為沿著第2圖中的切線I-I’所示的記憶胞結構剖面示意圖。
第4圖為沿著第2圖中的切線II-II’所示的剖面示意圖。
第5圖至第7圖為依據本發明其他實施例所繪示的具抹除元件的單層多晶矽非揮發性記憶體的不同實施態樣。
第8圖例示適用於第2圖至第7圖中的各記憶胞的寫入(PGM)、讀取(READ)及抹除(ERS)的操作條件。
第9圖為依據本發明另一實施例所繪示的單層多晶矽非揮發性記憶體的部分佈局示意圖。
第10圖為沿著第9圖中的切線III-III’所示的剖面示意圖。
第11圖為沿著第9圖中的切線IV-IV’所示的剖面示意圖。
第12圖為依據本發明又另一實施例所繪示的具抹除元件的單層多晶矽非揮發性記憶體的實施態樣。
第13圖例示適用於第9圖及第12圖中的各記憶胞的寫入(PGM)、讀取(READ)及抹除(ERS)的操作條件。
藉由接下來的敘述及所提供的眾多特定細節，可充分了解本發明。然而對於此領域中的技術人員，在沒有這些特定細節下依然可實行本發明。再者，一些此領域中公知的系統配置和製程步驟並未在此詳述，因為這些應是此領域中的技術人員所熟知的。
同樣地，實施例的圖式為示意圖，為了清楚呈現而放大一些尺寸，並未照實際比例繪製。在此公開和描述的多個實施例中若具有共通或類似的某些特徵時，為了方便圖示及描述，類似的特徵通常會以相同的標號表示。
本發明係關於一種單層多晶矽非揮發性記憶體結構，具有一抹除元 件，可以作為可多次寫入(MTP)記憶體。本發明單層多晶矽非揮發性記憶體結構係製作在一矽覆絕緣(silicon-on-insulator或semiconductor-on-insulator，簡稱SOI)基板上。SOI基板包含一矽基底、一埋入氧化層及一矽(或半導體)主動層，設於埋入氧化層上。本發明單層多晶矽非揮發性記憶體結構係製作在所述矽(或半導體)主動層中。SOI基板可以是商業上可獲得的SOI產品，可以利用公知的SIMOX方法製作而成，但不限於此。本發明單層多晶矽非揮發性記憶體結構可以是一全空乏(fully depleted)SOI元件或部分空乏(partially depleted)SOI元件。
請參閱第2圖至第4圖。第2圖為依據本發明一實施例所繪示的單層多晶矽非揮發性記憶體的部分佈局示意圖。第3圖為沿著第2圖中的切線I-I所示的記憶胞結構剖面示意圖。第4圖為沿著第2圖中的切線II-II’所示的剖面示意圖。
如第2圖所示，本發明單層多晶矽非揮發性記憶體1包含複數個記憶胞，包括但不限於，例如，四個記憶胞單元C1~C4。應理解的是，第2圖中所示的記憶胞佈局僅為例示說明。在第2圖中，舉例來說，僅繪示三個氧化物定義(oxide define，OD)區域：OD1、OD2、OD3。根據本發明實施例，記憶胞C1及C2係製作於氧化物定義區域OD1上，記憶胞C3及C4係製作於氧化物定義區域OD2上。
根據本發明實施例，氧化物定義區域OD1、OD2可以是沿著參考y軸延伸的條狀區域。氧化物定義區域OD1、OD2、OD3藉由淺溝絕緣(shallow trench isolation，STI)區域300彼此隔離絕緣。在第2圖中，僅繪示兩條沿著參考x軸延伸且與氧化物定義區域OD1、OD2交叉的字元線WL1及WL2。在氧化物定義區域OD3上可以形成一抹除元件250。根據本發明實施例，抹除元件250可以被圖中四個記憶胞單元C1~C4共用。
根據本發明實施例，氧化物定義區域OD3係介於氧化物定義區域OD1與氧化物定義區域OD2之間。氧化物定義區域OD3與字元線WL1及WL2有一段距 離，故從第2圖的佈局示意圖中可看出，氧化物定義區域OD3不會與字元線WL1及WL2重疊。
根據本發明實施例，記憶胞單元C1與記憶胞單元C2共用同一P+汲極/源極摻雜區及相同的位元線接觸點。根據本發明實施例，記憶胞單元C3與記憶胞單元C4共用同一P+汲極/源極摻雜區及相同的位元線接觸點。
如第2圖至第4圖所示，四個記憶胞單元C1~C4的各記憶胞單元(以記憶胞單元C1為例)均包含一PMOS選擇電晶體102及一串接PMOS選擇電晶體102的PMOS浮置閘極電晶體104。PMOS選擇電晶體102及PMOS浮置閘極電晶體104一起形成在氧化物定義區域OD1上，其中氧化物定義區域OD1係定義於一SOI基板200的一半導體層230中。記憶胞單元C2的記憶胞結構係鏡面對稱於記憶胞單元C1。記憶胞單元C3及C4的記憶胞結構則分別鏡面對稱於記憶胞單元C1及C2。
半導體層230可以是一單晶矽層，但不限於此。SOI基板200可以進一步包含一埋入氧化層220及一矽基板210。半導體層230係藉由埋入氧化層220與矽基板210電性隔離。STI區域300與下方的埋入氧化層220接壤。矽基板210可以是一P型矽基板，但不限於此。在半導體層230中，可以利用離子佈植製程形成一與氧化物定義區域OD1完全重疊的N型井310。在某些實施例中，N型井310可以被省略，如此一來通道可以形成在本徵矽(intrinsic silicon)中。
PMOS選擇電晶體102包含一選擇閘極110、一選擇閘極氧化層112，介於選擇閘極110與半導體層230之間、一P+源極摻雜區132，及一P+汲極/源極摻雜區134。PMOS浮置閘極電晶體104包含一浮置閘極120、一浮置閘極氧化層122，介於浮置閘極120與半導體層230之間、P+汲極/源極摻雜區134，及一P+汲極摻雜區136。PMOS選擇電晶體102與PMOS浮置閘極電晶體104共用P+汲極/源極摻雜區134。為簡化說明，圖中選擇閘極110與浮置閘極120側壁上的側壁子並未繪示出來。
從第2圖及第4圖可看出，浮置閘極120包括一延伸部(或稱之為浮置閘極延伸)120a，其沿著參考x軸方向連續地延伸出去，並與氧化物定義區域OD3重疊。延伸部120a可以具有一寬度，其小於浮置閘極120的寬度。根據本發明實施例，延伸部120a與氧化物定義區域OD3的重疊面積小於浮置閘極120與氧化物定義區域OD1的重疊面積。
在氧化物定義區域OD3中，形成有一重摻雜區域138。重摻雜區域138可以是一N+摻雜區或一P+摻雜區。一離子井320，例如一N型井或一P型井，可以形成在半導體層230中，並與氧化物定義區域OD3完全重疊。或者，重摻雜區域138可以直接形成在本徵矽中，此時，無需在氧化物定義區域OD3中形成離子井。應理解的是，圖中的浮置閘極的形狀僅為例說明。
根據本發明實施例，氧化物定義區域OD3、重摻雜區域138、浮置閘極氧化層122及電容耦合於重摻雜區域138與氧化物定義區域OD3的延伸部120a共同構成抹除元件250。
操作時，PMOS選擇電晶體102的選擇閘極110經由一字元線接觸點510耦合至一選擇閘極電壓VSG，PMOS選擇電晶體102的P+源極摻雜區132經由一源極線(SL)接觸點耦合至一源極線電壓VSL，P+汲極/源極摻雜區134及浮置閘極120為電性浮置，而PMOS浮置閘極電晶體104的P+汲極摻雜區136係經由一位元線(BL)接觸點耦合至一位元線電壓VBL。重摻雜區域138則是經由一抹除線(EL)接觸點耦合至一抹除線電壓VEL。
在寫入模式下，電子透過通道熱電子(channel hot electron，CHE)注入機制被選擇性的注入浮置閘極120。在抹除模式下(區段或全晶片抹除)，電子則是透過福勒諾漢穿隧(Fowler-Nordheim(FN)tunneling)機制從浮置閘極120抹除。
第5圖至第7圖為依據本發明其他實施例所繪示的具抹除元件的單層多晶矽非揮發性記憶體的不同實施態樣。
如第5圖所示，第5圖中的單層多晶矽非揮發性記憶體2與第2圖中的單層多晶矽非揮發性記憶體1差異在於第5圖中的單層多晶矽非揮發性記憶體2另包含一與氧化物定義區域OD1接壤的電荷收集區域50。電荷收集區域50能夠在單層多晶矽非揮發性記憶體操作時收集累積在半導體層230中的多餘電子及電洞。
根據本發明實施例，電荷收集區域50包含一氧化物定義區域OD4、一N+摻雜區500位於氧化物定義區域OD4內，及一橋接區域520連接N+摻雜區500與浮置閘極120正下方的半導體層230。N型井310可以與橋接區域520及氧化物定義區域OD4重疊。在N+摻雜區500內可提供一N型井接觸點，使電荷收集區域50可以耦合至一N型井電壓VNW。在第5圖中，記憶胞C1及記憶胞C2共用一電荷收集區域，而記憶胞C3及記憶胞C4共用一電荷收集區域。
如第6圖所示，第6圖中的單層多晶矽非揮發性記憶體3與第2圖中的單層多晶矽非揮發性記憶體1差異在於第6圖中的單層多晶矽非揮發性記憶體3另包含一N+摻雜區162，其與P+源極摻雜區132接壤，N+摻雜區162與P+源極摻雜區132位於選擇閘極110同一側，如此構成一毗接接觸區60。N+摻雜區162與P+源極摻雜區132皆耦合至一源極線電壓VSL。
如第7圖所示，第7圖中的單層多晶矽非揮發性記憶體4與第2圖中的單層多晶矽非揮發性記憶體1差異在於第7圖中的單層多晶矽非揮發性記憶體4包含一與氧化物定義區域OD1接壤的電荷收集區域50。電荷收集區域50能夠在記憶體操作時收集累積在半導體層230中的多餘電子及電洞。電荷收集區域50的細節同第5圖所示。第7圖中的單層多晶矽非揮發性記憶體4另包含一N+摻雜區162，其與P+源極摻雜區132接壤，N+摻雜區162與P+源極摻雜區132位於選擇閘極110同一側，如此構成一毗接接觸區60。N+摻雜區162與P+源極摻雜區132皆耦合至一源極線電壓VSL。
第8圖例示適用於第2圖至第7圖中的各記憶胞的寫入(PGM)、讀取 (READ)及抹除(ERS)的操作條件。如第8圖所示，在寫入(PGM)操作時，源極線(SL)耦合至一電壓VPP，例如，電壓VPP可以介於5~9V。位元線(BL)接地(VBL=0V)。另提供選擇閘極(SG)110一介於0~1/2VPP的電壓，提供抹除線(EL)一介於0~VPP的電壓。對於具有電荷收集區域50的記憶胞，如第5圖及第7圖所示，N+摻雜區500偶合至一VPP電壓。第8圖中同時例示對記憶胞進行寫入-抑制(PGM-inhibit)操作或寫入-未選擇(PGM-unselect)操作的電壓條件。
在抹除操作時，源極線(SL)接地(VSL=0V)，位元線(BL)接地(VBL=0V)，選擇閘極(SG)110接地(VSG=0V)。另提供抹除線(EL)一VEE的電壓。舉例來說，VEE可以介於8~18V。對於具有電荷收集區域50的記憶胞，如第5圖及第7圖所示，N+摻雜區500接地(VNW=0V)。
另一抹除操作方式是，源極線(SL)耦合至一VBB電壓。舉例來說，VBB可以介於-4~-8V。位元線(BL)耦合至一VBB電壓。選擇閘極(SG)110耦合至一VBB電壓。另提供抹除線(EL)一VEE的電壓。舉例來說，VEE可以介於8~18V。對於具有電荷收集區域50的記憶胞，如第5圖及第7圖所示，N+摻雜區500耦合至一VBB電壓。
在讀取操作時，源極線(SL)耦合至一VREAD電壓。舉例來說，VREAD可以介於2~2.8V。位元線(BL)耦合至0.4V電壓(VBL=0.4V)。選擇閘極(SG)110接地(VSG=0V)。抹除線(EL)接地(VEL=0V)。對於具有電荷收集區域50的記憶胞，如第5圖及第7圖所示，N+摻雜區500耦合至VREAD電壓。第8圖中同時例示對記憶胞進行讀取-未選擇(READ-unselect)操作的電壓條件。
請參閱第9圖至第11圖。第9圖為依據本發明另一實施例所繪示的單層多晶矽非揮發性記憶體的部分佈局示意圖。第10圖為沿著第9圖中的切線III-III’所示的剖面示意圖。第11圖為沿著第9圖中的切線IV-IV’所示的剖面示意圖。
如第9圖所示，本發明單層多晶矽非揮發性記憶體5包含複數個記憶 胞，包括但不限於，例如，四個記憶胞單元C1~C4。應理解的是，第9圖中所示的記憶胞佈局僅為例示說明。在第9圖中，舉例來說，僅繪示三個氧化物定義區域：OD1、OD2、OD3。根據本發明實施例，記憶胞C1及C2係製作於氧化物定義區域OD1上，記憶胞C3及C4係製作於氧化物定義區域OD2上。
根據本發明實施例，氧化物定義區域OD1、OD2可以是沿著參考y軸延伸的條狀區域。氧化物定義區域OD1、OD2、OD3藉由淺溝絕緣(STI)區域300彼此隔離絕緣。在第9圖中，僅繪示兩條沿著參考x軸延伸且與氧化物定義區域OD1、OD2交叉的字元線WL1及WL2。在氧化物定義區域OD3上可以形成一抹除元件450。根據本發明實施例，抹除元件450可以被圖中四個記憶胞單元C1~C4共用。
根據本發明實施例，氧化物定義區域OD3係介於氧化物定義區域OD1與氧化物定義區域OD2之間。氧化物定義區域OD3與字元線WL1及WL2有一段距離，故從第9圖的佈局示意圖中可看出，氧化物定義區域OD3不會與字元線WL1及WL2重疊。
根據本發明實施例，記憶胞單元C1與記憶胞單元C2共用同一P+汲極/源極摻雜區及相同的位元線接觸點。根據本發明實施例，記憶胞單元C3與記憶胞單元C4共用同一P+汲極/源極摻雜區及相同的位元線接觸點
如第9圖至第11圖所示，四個記憶胞單元C1~C4的各記憶胞單元(以記憶胞單元C1為例)均包含一PMOS選擇電晶體102及一串接PMOS選擇電晶體102的PMOS浮置閘極電晶體104。PMOS選擇電晶體102及PMOS浮置閘極電晶體104一起形成在氧化物定義區域OD1上，其中氧化物定義區域OD1係定義於一SOI基板200的一半導體層230中。記憶胞單元C2的記憶胞結構係鏡面對稱於記憶胞單元C1。記憶胞單元C3及C4的記憶胞結構則分別鏡面對稱於記憶胞單元C1及C2。
半導體層230可以是一單晶矽層，但不限於此。SOI基板200可以進一步包含一埋入氧化層220及一矽基板210。半導體層230係藉由埋入氧化層220與矽 基板210電性隔離。STI區域300與下方的埋入氧化層220接壤。矽基板210可以是一P型矽基板，但不限於此。在半導體層230中，可以利用離子佈植製程形成一與氧化物定義區域OD1完全重疊的N型井310。在某些實施例中，N型井310可以被省略，如此一來通道可以形成在本徵矽中。
PMOS選擇電晶體102包含一選擇閘極110、一選擇閘極氧化層112，介於選擇閘極110與半導體層230之間、一P+源極摻雜區132，及一P+汲極/源極摻雜區134。PMOS浮置閘極電晶體104包含一浮置閘極120、一浮置閘極氧化層122，介於浮置閘極120與半導體層230之間、P+汲極/源極摻雜區134，及一P+汲極摻雜區136。PMOS選擇電晶體102與PMOS浮置閘極電晶體104共用P+汲極/源極摻雜區134。為簡化說明，圖中選擇閘極110與浮置閘極120側壁上的側壁子並未繪示出來。
從第9圖及第11圖可看出，浮置閘極120包括一延伸部120b，其沿著參考x軸方向延伸出去，與氧化物定義區域OD3重疊。延伸部120b可以具有一寬度，其大於浮置閘極120的寬度。根據本發明實施例，延伸部120b與氧化物定義區域OD3的重疊面積大於浮置閘極120與氧化物定義區域OD1的重疊面積。
在氧化物定義區域OD3中，形成有一重摻雜區域138。重摻雜區域138可以是一N+摻雜區或一P+摻雜區。一離子井320，例如一N型井或一P型井，可以形成在氧化物定義區域OD3。根據本發明實施例，重摻雜區域138為一N+摻雜區，離子井320為一N型井。根據本發明另一實施例，重摻雜區域138為一P+摻雜區，離子井320為一P型井。應理解的是，圖中的浮置閘極的形狀僅供例示參考。
根據本發明實施例，氧化物定義區域OD3、重摻雜區域138、浮置閘極氧化層122及電容耦合於重摻雜區域138與氧化物定義區域OD3的延伸部120b共同構成抹除元件450。氧化物定義區域OD3及重摻雜區域138可作為一控制閘極。
操作時，PMOS選擇電晶體102的選擇閘極110耦合至一選擇閘極電壓 VSG，PMOS選擇電晶體102的P+源極摻雜區132經由一源極線(SL)接觸點耦合至一源極線電壓VSL，P+汲極/源極摻雜區134及浮置閘極120為電性浮置，而PMOS浮置閘極電晶體104的P+汲極摻雜區136係經由一位元線(BL)接觸點耦合至一位元線電壓VBL。重摻雜區域138則是耦合至一控制閘極電壓VCG。
在寫入模式下，電子透過通道熱電子(CHE)注入機制被選擇性的注入浮置閘極120。在抹除模式下(區段或全晶片抹除)，電子則是透過福勒諾漢穿隧(FN tunneling)機制從浮置閘極120抹除。
第12圖為依據本發明又另一實施例所繪示的具抹除元件的單層多晶矽非揮發性記憶體的實施態樣。
如第12圖所示，第12圖中的單層多晶矽非揮發性記憶體6與第9圖中的單層多晶矽非揮發性記憶體5差異在於第12圖中的單層多晶矽非揮發性記憶體6另包含一與氧化物定義區域OD1接壤的電荷收集區域50。電荷收集區域50能夠在單層多晶矽非揮發性記憶體操作時收集累積在半導體層230中的多餘電子及電洞。
根據本發明實施例，電荷收集區域50包含一氧化物定義區域OD4、一N+摻雜區500位於氧化物定義區域OD4內，及一橋接區域520連接N+摻雜區500與浮置閘極120正下方的半導體層230。N型井310可以與橋接區域520及氧化物定義區域OD4重疊。在N+摻雜區500內可提供一N型井接觸點，使電荷收集區域50可以耦合至一N型井電壓VNW。在第12圖中，記憶胞C1及記憶胞C2共用一電荷收集區域，而記憶胞C3及記憶胞C4共用一電荷收集區域。
第13圖例示適用於第9圖及第12圖中的各記憶胞的寫入(PGM)、讀取(READ)及抹除(ERS)的操作條件。如第13圖所示，在寫入(PGM)操作時，源極線(SL)耦合至一電壓VPP，例如，電壓VPP可以介於5~9V。位元線(BL)接地(VBL=0V)。另提供選擇閘極(SG)110一介於0~1/2VPP的電壓，提供控制閘極(CG)一介於 0~1/2VPP的電壓。對於具有電荷收集區域50的記憶胞，如第12圖所示，N+摻雜區500偶合至一VPP電壓。第13圖中同時例示對記憶胞進行寫入-抑制(PGM-inhibit)操作或寫入-未選擇(PGM-unselect)操作的電壓條件。
在抹除操作時，源極線(SL)耦合至一VEE電壓。舉例來說，VEE可以介於8~18V。位元線(BL)耦合至VEE電壓。選擇閘極(SG)110耦合至VEE電壓，或者VEE-△V電壓(△V>Vt)。控制閘極(CG)接地(VCG=0V)。對於具有電荷收集區域50的記憶胞，如第12圖所示，N+摻雜區500接地(VNW=0V)。
在讀取操作時，源極線(SL)耦合至一VREAD電壓。舉例來說，VREAD可以介於2~2.8V。位元線(BL)耦合至0.4V電壓(VBL=0.4V)。選擇閘極(SG)110接地(VSG=0V)。控制閘極(CG)接地(VCG=0V)。對於具有電荷收集區域50的記憶胞，如第12圖所示，N+摻雜區500耦合至VREAD電壓。第13圖中同時例示對記憶胞進行讀取-未選擇(READ-unselect)操作的電壓條件。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (16)

  1. 一種單層多晶矽非揮發性記憶胞結構，包含：一矽覆絕緣(SOI)基板，包含一矽基底、一埋入氧化層及一半導體層；一第一氧化物定義區域及一第二氧化物定義區域，位於該半導體層；一絕緣區域，位於該半導體層，該絕緣區域隔離該第一氧化物定義區域與該第二氧化物定義區域；一PMOS選擇電晶體，設於該第一氧化物定義區域；一PMOS浮置閘極電晶體，設於該第一氧化物定義區域，並串接該PMOS選擇電晶體，其中該PMOS浮置閘極電晶體包含一浮置閘極，位於該第一氧化物定義區域上；一浮置閘極延伸，由該浮置閘極連續地延伸至該第二氧化物定義區域，並與該第二氧化物定義區域電容耦合；以及一電荷收集區域，與該第一氧化物定義區域接壤，其中該電荷收集區域包含一第三氧化物定義區域、一N+摻雜區位於該第三氧化物定義區域內，及一橋接區域，連接該N+摻雜區與該浮置閘極正下方的該半導體層。
  2. 如申請專利範圍第1項所述的單層多晶矽非揮發性記憶胞結構，其中該PMOS選擇電晶體包含一選擇閘極、一選擇閘極氧化層，介於該選擇閘極與該半導體層之間、一P+源極摻雜區，及一P+汲極/源極摻雜區，其中該P+源極摻雜區耦合至一源極線。
  3. 如申請專利範圍第2項所述的單層多晶矽非揮發性記憶胞結構，其中該PMOS浮置閘極電晶體包含該浮置閘極、一浮置閘極氧化層，介於該浮置閘極與該半導體層之間、該P+汲極/源極摻雜區，及一P+汲極摻雜區，其中該PMOS選擇電晶體與該PMOS浮置閘極電晶體共用該P+汲極/源極摻雜區。
  4. 如申請專利範圍第1項所述的單層多晶矽非揮發性記憶胞結構，其中另包含：一N型井，位於該半導體層，其中該N型井完全重疊該第一氧化物定義區域。
  5. 如申請專利範圍第3項所述的單層多晶矽非揮發性記憶胞結構，其中另包含：一離子井，位於該半導體層，其中該離子井完全重疊該第二氧化物定義區域；以及一重摻雜區域，位於該第二氧化物定義區域內的該離子井中。
  6. 如申請專利範圍第5項所述的單層多晶矽非揮發性記憶胞結構，其中該離子井包含一N型井或一P型井。
  7. 如申請專利範圍第5項所述的單層多晶矽非揮發性記憶胞結構，其中該重摻雜區域係為一N+摻雜區。
  8. 如申請專利範圍第5項所述的單層多晶矽非揮發性記憶胞結構，其中該重摻雜區域係為一P+摻雜區。
  9. 如申請專利範圍第5項所述的單層多晶矽非揮發性記憶胞結構，其中該浮置閘極跨越該第一氧化物定義區域與該第二氧化物定義區域之間的該絕緣區域，並且與該第二氧化物定義區域部分重疊以電容耦合該重摻雜區域。
  10. 如申請專利範圍第5項所述的單層多晶矽非揮發性記憶胞結構，其中該第二氧化物定義區域、該重摻雜區域、該浮置閘極氧化層，及與該重摻雜區域電容耦合的該浮置閘極延伸，共同構成一抹除元件。
  11. 如申請專利範圍第5項所述的單層多晶矽非揮發性記憶胞結構，其中操作時，該選擇閘極耦合至一選擇閘極電壓VSG，該PMOS選擇電晶體的P+源極摻雜區耦合至一源極線電壓VSL，該P+汲極/源極摻雜區及該浮置閘極為電性浮置，而該PMOS浮置閘極電晶體的該P+汲極摻雜區耦合至一位元線電壓VBL，該重摻雜區域耦合至一抹除線電壓VEL。
  12. 如申請專利範圍第1項所述的單層多晶矽非揮發性記憶胞結構，其中該浮置閘極延伸與該第二氧化物定義區域的重疊面積小於該浮置閘極與該第一氧化物定義區域的重疊面積。
  13. 如申請專利範圍第1項所述的單層多晶矽非揮發性記憶胞結構，其中該浮置閘極延伸與該第二氧化物定義區域的重疊面積大於該浮置閘極與該第一氧化物定義區域的重疊面積。
  14. 如申請專利範圍第4項所述的單層多晶矽非揮發性記憶胞結構，其中：該電荷收集區域在該單層多晶矽非揮發性記憶體操作時收集累積在該半導體層中的多餘電子及電洞。
  15. 如申請專利範圍第14項所述的單層多晶矽非揮發性記憶胞結構，其中該N型井與該橋接區域及該第三氧化物定義區域重疊。
  16. 如申請專利範圍第1項所述的單層多晶矽非揮發性記憶胞結構，其中另包含：一N+摻雜區，其與該P+源極摻雜區接壤，該N+摻雜區與該P+源極摻雜區位於該選擇閘極同一側，如此構成一毗接接觸區。
TW106104042A 2016-01-19 2017-02-08 具有抹除元件的單層多晶矽非揮發性記憶胞結構 TWI646665B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662280683P 2016-01-19 2016-01-19
US15/384,323 2016-12-20
US15/384,323 US10038003B2 (en) 2016-01-19 2016-12-20 Single-poly nonvolatile memory cell structure having an erase device

Publications (2)

Publication Number Publication Date
TW201824520A TW201824520A (zh) 2018-07-01
TWI646665B true TWI646665B (zh) 2019-01-01

Family

ID=56137184

Family Applications (11)

Application Number Title Priority Date Filing Date
TW105121411A TWI578322B (zh) 2016-01-19 2016-07-06 電壓切換電路
TW105123524A TWI613672B (zh) 2016-01-19 2016-07-26 記憶體陣列
TW105133388A TWI587455B (zh) 2016-01-19 2016-10-17 非揮發性記憶體結構
TW106100743A TWI621123B (zh) 2016-01-19 2017-01-10 非揮發性記憶體的驅動電路
TW106100807A TWI614763B (zh) 2016-01-19 2017-01-11 記憶體裝置、其週邊電路及其單一位元組資料寫入方法
TW106101257A TWI618072B (zh) 2016-01-19 2017-01-13 電源切換電路
TW106101517A TWI630615B (zh) 2016-01-19 2017-01-17 記憶體陣列
TW106104042A TWI646665B (zh) 2016-01-19 2017-02-08 具有抹除元件的單層多晶矽非揮發性記憶胞結構
TW106108098A TWI613659B (zh) 2016-01-19 2017-03-13 記憶單元
TW106113346A TWI613654B (zh) 2016-01-19 2017-04-21 記憶體單元及記憶體陣列
TW106114486A TWI641115B (zh) 2016-01-19 2017-05-02 記憶體單元及記憶體陣列

Family Applications Before (7)

Application Number Title Priority Date Filing Date
TW105121411A TWI578322B (zh) 2016-01-19 2016-07-06 電壓切換電路
TW105123524A TWI613672B (zh) 2016-01-19 2016-07-26 記憶體陣列
TW105133388A TWI587455B (zh) 2016-01-19 2016-10-17 非揮發性記憶體結構
TW106100743A TWI621123B (zh) 2016-01-19 2017-01-10 非揮發性記憶體的驅動電路
TW106100807A TWI614763B (zh) 2016-01-19 2017-01-11 記憶體裝置、其週邊電路及其單一位元組資料寫入方法
TW106101257A TWI618072B (zh) 2016-01-19 2017-01-13 電源切換電路
TW106101517A TWI630615B (zh) 2016-01-19 2017-01-17 記憶體陣列

Family Applications After (3)

Application Number Title Priority Date Filing Date
TW106108098A TWI613659B (zh) 2016-01-19 2017-03-13 記憶單元
TW106113346A TWI613654B (zh) 2016-01-19 2017-04-21 記憶體單元及記憶體陣列
TW106114486A TWI641115B (zh) 2016-01-19 2017-05-02 記憶體單元及記憶體陣列

Country Status (5)

Country Link
US (13) US9847133B2 (zh)
EP (6) EP3196883B1 (zh)
JP (4) JP6122531B1 (zh)
CN (10) CN106981311B (zh)
TW (11) TWI578322B (zh)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9965267B2 (en) 2015-11-19 2018-05-08 Raytheon Company Dynamic interface for firmware updates
US9847133B2 (en) * 2016-01-19 2017-12-19 Ememory Technology Inc. Memory array capable of performing byte erase operation
US9633734B1 (en) * 2016-07-14 2017-04-25 Ememory Technology Inc. Driving circuit for non-volatile memory
CN107768373B (zh) * 2016-08-15 2022-05-10 华邦电子股份有限公司 存储元件及其制造方法
US9882566B1 (en) * 2017-01-10 2018-01-30 Ememory Technology Inc. Driving circuit for non-volatile memory
TWI652683B (zh) * 2017-10-13 2019-03-01 力旺電子股份有限公司 用於記憶體的電壓驅動器
US10332597B2 (en) * 2017-11-08 2019-06-25 Globalfoundries Singapore Pte. Ltd. Floating gate OTP/MTP structure and method for producing the same
WO2019124350A1 (ja) 2017-12-20 2019-06-27 パナソニック・タワージャズセミコンダクター株式会社 半導体装置
KR102422839B1 (ko) * 2018-02-23 2022-07-19 에스케이하이닉스 시스템아이씨 주식회사 수평 커플링 구조 및 단일층 게이트를 갖는 불휘발성 메모리 소자
KR102385951B1 (ko) * 2018-02-23 2022-04-14 에스케이하이닉스 시스템아이씨 주식회사 프로그램 효율이 증대되는 원 타임 프로그래머블 메모리 및 그 제조방법
US10522202B2 (en) * 2018-04-23 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and compensation method therein
US10964708B2 (en) * 2018-06-26 2021-03-30 Micron Technology, Inc. Fuse-array element
CN108986866B (zh) * 2018-07-20 2020-12-11 上海华虹宏力半导体制造有限公司 一种读高压传输电路
TWI659502B (zh) * 2018-08-02 2019-05-11 旺宏電子股份有限公司 非揮發性記憶體結構
CN110828464A (zh) * 2018-08-08 2020-02-21 旺宏电子股份有限公司 非易失性存储器结构
DE102019120605B4 (de) 2018-08-20 2022-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Speicherschaltung und verfahren zu deren herstellung
US11176969B2 (en) 2018-08-20 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit including a first program device
CN109147851B (zh) * 2018-08-31 2020-12-25 上海华力微电子有限公司 一种锁存电路
KR20200031894A (ko) * 2018-09-17 2020-03-25 에스케이하이닉스 주식회사 메모리 모듈 및 이를 포함하는 메모리 시스템
US10797064B2 (en) * 2018-09-19 2020-10-06 Ememory Technology Inc. Single-poly non-volatile memory cell and operating method thereof
CN109524042B (zh) * 2018-09-21 2020-03-17 浙江大学 一种基于反型模式阻变场效应晶体管的与非型存储阵列
TWI708253B (zh) 2018-11-16 2020-10-21 力旺電子股份有限公司 非揮發性記憶體良率提升的設計暨測試方法
CN111342541B (zh) * 2018-12-19 2021-04-16 智原微电子(苏州)有限公司 电源切换电路
KR102723994B1 (ko) * 2019-02-27 2024-10-30 삼성전자주식회사 집적회로 소자
US10924112B2 (en) 2019-04-11 2021-02-16 Ememory Technology Inc. Bandgap reference circuit
US11508719B2 (en) * 2019-05-13 2022-11-22 Ememory Technology Inc. Electrostatic discharge circuit
CN112086115B (zh) * 2019-06-14 2023-03-28 力旺电子股份有限公司 存储器系统
CN112131037B (zh) * 2019-06-24 2023-11-14 华邦电子股份有限公司 存储器装置
JP2021048230A (ja) * 2019-09-18 2021-03-25 キオクシア株式会社 半導体記憶装置
US11521980B2 (en) * 2019-11-14 2022-12-06 Ememory Technology Inc. Read-only memory cell and associated memory cell array
US11217281B2 (en) * 2020-03-12 2022-01-04 Ememory Technology Inc. Differential sensing device with wide sensing margin
US11139006B1 (en) * 2020-03-12 2021-10-05 Ememory Technology Inc. Self-biased sense amplification circuit
JP6887044B1 (ja) * 2020-05-22 2021-06-16 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置および読出し方法
TWI739695B (zh) * 2020-06-14 2021-09-11 力旺電子股份有限公司 轉壓器
CN114373489A (zh) * 2020-10-15 2022-04-19 华邦电子股份有限公司 非易失性存储器装置
US11373715B1 (en) * 2021-01-14 2022-06-28 Elite Semiconductor Microelectronics Technology Inc. Post over-erase correction method with auto-adjusting verification and leakage degree detection
TWI819457B (zh) * 2021-02-18 2023-10-21 力旺電子股份有限公司 多次編程非揮發性記憶體的記憶胞陣列
US11854647B2 (en) * 2021-07-29 2023-12-26 Micron Technology, Inc. Voltage level shifter transition time reduction
US11972800B2 (en) * 2021-12-16 2024-04-30 Ememory Technology Inc. Non-volatile memory cell and non-volatile memory cell array
US12014783B2 (en) 2022-01-10 2024-06-18 Ememory Technology Inc. Driving circuit for non-volatile memory

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200802807A (en) * 2006-06-26 2008-01-01 Ememory Technology Inc Silicon-on-insulator (SOI) memory device
US8941167B2 (en) * 2012-03-08 2015-01-27 Ememory Technology Inc. Erasable programmable single-ploy nonvolatile memory

Family Cites Families (168)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4617652A (en) 1979-01-24 1986-10-14 Xicor, Inc. Integrated high voltage distribution and control systems
JP2685966B2 (ja) 1990-06-22 1997-12-08 株式会社東芝 不揮発性半導体記憶装置
US5331590A (en) 1991-10-15 1994-07-19 Lattice Semiconductor Corporation Single poly EE cell with separate read/write paths and reduced product term coupling
JP3180608B2 (ja) 1994-03-28 2001-06-25 松下電器産業株式会社 電源選択回路
JP3068752B2 (ja) 1994-08-29 2000-07-24 松下電器産業株式会社 半導体装置
US5648669A (en) * 1995-05-26 1997-07-15 Cypress Semiconductor High speed flash memory cell structure and method
US5742542A (en) * 1995-07-03 1998-04-21 Advanced Micro Devices, Inc. Non-volatile memory cells using only positive charge to store data
US5640344A (en) * 1995-07-25 1997-06-17 Btr, Inc. Programmable non-volatile bidirectional switch for programmable logic
US6005806A (en) * 1996-03-14 1999-12-21 Altera Corporation Nonvolatile configuration cells and cell arrays
JP4659662B2 (ja) 1997-04-28 2011-03-30 ペグレ・セミコンダクターズ・リミテッド・ライアビリティ・カンパニー 半導体装置及びその製造方法
FR2767219B1 (fr) * 1997-08-08 1999-09-17 Commissariat Energie Atomique Dispositif memoire non volatile programmable et effacable electriquement compatible avec un procede de fabrication cmos/soi
JP3037236B2 (ja) * 1997-11-13 2000-04-24 日本電気アイシーマイコンシステム株式会社 レベルシフタ回路
US5959889A (en) * 1997-12-29 1999-09-28 Cypress Semiconductor Corp. Counter-bias scheme to reduce charge gain in an electrically erasable cell
DE19808525A1 (de) 1998-02-27 1999-09-02 Siemens Ag Integrierte Schaltung
JP2000021183A (ja) 1998-06-30 2000-01-21 Matsushita Electric Ind Co Ltd 半導体不揮発性メモリ
US5999451A (en) 1998-07-13 1999-12-07 Macronix International Co., Ltd. Byte-wide write scheme for a page flash device
JP3344331B2 (ja) 1998-09-30 2002-11-11 日本電気株式会社 不揮発性半導体記憶装置
JP2000276889A (ja) 1999-03-23 2000-10-06 Toshiba Corp 不揮発性半導体メモリ
CN1376313A (zh) * 1999-08-27 2002-10-23 马克罗尼克斯美国公司 用于双位存储的非易失性存储器结构及其制造方法
JP2001068650A (ja) * 1999-08-30 2001-03-16 Hitachi Ltd 半導体集積回路装置
KR100338772B1 (ko) * 2000-03-10 2002-05-31 윤종용 바이어스 라인이 분리된 비휘발성 메모리 장치의 워드라인 드라이버 및 워드 라인 드라이빙 방법
US6370071B1 (en) * 2000-09-13 2002-04-09 Lattice Semiconductor Corporation High voltage CMOS switch
AU2002339620A1 (en) * 2001-11-27 2003-06-10 Koninklijke Philips Electronics N.V. Semiconductor device having a byte-erasable eeprom memory
TW536818B (en) 2002-05-03 2003-06-11 Ememory Technology Inc Single-poly EEPROM
US6621745B1 (en) * 2002-06-18 2003-09-16 Atmel Corporation Row decoder circuit for use in programming a memory device
US6774704B2 (en) 2002-10-28 2004-08-10 Tower Semiconductor Ltd. Control circuit for selecting the greater of two voltage signals
US7038947B2 (en) * 2002-12-19 2006-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Two-transistor flash cell for large endurance application
CN1224106C (zh) * 2003-03-05 2005-10-19 力旺电子股份有限公司 只读存储器及其制作方法
JP2004326864A (ja) 2003-04-22 2004-11-18 Toshiba Corp 不揮発性半導体メモリ
FR2856185A1 (fr) 2003-06-12 2004-12-17 St Microelectronics Sa Memoire flash programmable par mot
US6963503B1 (en) 2003-07-11 2005-11-08 Altera Corporation. EEPROM with improved circuit performance and reduced cell size
JP2005051227A (ja) * 2003-07-17 2005-02-24 Nec Electronics Corp 半導体記憶装置
US7169667B2 (en) * 2003-07-30 2007-01-30 Promos Technologies Inc. Nonvolatile memory cell with multiple floating gates formed after the select gate
US7081774B2 (en) * 2003-07-30 2006-07-25 Semiconductor Energy Laboratory Co., Ltd. Circuit having source follower and semiconductor device having the circuit
US7145370B2 (en) 2003-09-05 2006-12-05 Impinj, Inc. High-voltage switches in single-well CMOS processes
US20050134355A1 (en) 2003-12-18 2005-06-23 Masato Maede Level shift circuit
US20050205969A1 (en) * 2004-03-19 2005-09-22 Sharp Laboratories Of America, Inc. Charge trap non-volatile memory structure for 2 bits per transistor
US7580311B2 (en) * 2004-03-30 2009-08-25 Virage Logic Corporation Reduced area high voltage switch for NVM
US7629640B2 (en) * 2004-05-03 2009-12-08 The Regents Of The University Of California Two bit/four bit SONOS flash memory cell
DE602004010795T2 (de) * 2004-06-24 2008-12-11 Stmicroelectronics S.R.L., Agrate Brianza Verbesserter Seitenspeicher für eine programmierbare Speichervorrichtung
US6992927B1 (en) 2004-07-08 2006-01-31 National Semiconductor Corporation Nonvolatile memory cell
US7209392B2 (en) * 2004-07-20 2007-04-24 Ememory Technology Inc. Single poly non-volatile memory
KR100633332B1 (ko) * 2004-11-09 2006-10-11 주식회사 하이닉스반도체 음의 전압 공급회로
KR100642631B1 (ko) * 2004-12-06 2006-11-10 삼성전자주식회사 전압 발생회로 및 이를 구비한 반도체 메모리 장치
US7369438B2 (en) 2004-12-28 2008-05-06 Aplus Flash Technology, Inc. Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications
US7193265B2 (en) 2005-03-16 2007-03-20 United Microelectronics Corp. Single-poly EEPROM
US7263001B2 (en) 2005-03-17 2007-08-28 Impinj, Inc. Compact non-volatile memory cell and array system
US7288964B2 (en) 2005-08-12 2007-10-30 Ememory Technology Inc. Voltage selective circuit of power source
JP4800109B2 (ja) 2005-09-13 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置
JP2007149997A (ja) 2005-11-29 2007-06-14 Nec Electronics Corp 不揮発性メモリセル及びｅｅｐｒｏｍ
US7382658B2 (en) 2006-01-26 2008-06-03 Mosys, Inc. Non-volatile memory embedded in a conventional logic process and methods for operating same
US7391647B2 (en) * 2006-04-11 2008-06-24 Mosys, Inc. Non-volatile memory in CMOS logic process and method of operation thereof
US20070247915A1 (en) * 2006-04-21 2007-10-25 Intersil Americas Inc. Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide
US7773416B2 (en) * 2006-05-26 2010-08-10 Macronix International Co., Ltd. Single poly, multi-bit non-volatile memory device and methods for operating the same
JP4901325B2 (ja) 2006-06-22 2012-03-21 ルネサスエレクトロニクス株式会社 半導体装置
US20070296034A1 (en) 2006-06-26 2007-12-27 Hsin-Ming Chen Silicon-on-insulator (soi) memory device
US7768059B2 (en) 2006-06-26 2010-08-03 Ememory Technology Inc. Nonvolatile single-poly memory device
JP5005970B2 (ja) 2006-06-27 2012-08-22 株式会社リコー 電圧制御回路及び電圧制御回路を有する半導体集積回路
CN100508169C (zh) * 2006-08-02 2009-07-01 联华电子股份有限公司 单层多晶硅可电除可程序只读存储单元的制造方法
US7586792B1 (en) * 2006-08-24 2009-09-08 National Semiconductor Corporation System and method for providing drain avalanche hot carrier programming for non-volatile memory applications
KR100805839B1 (ko) * 2006-08-29 2008-02-21 삼성전자주식회사 고전압 발생기를 공유하는 플래시 메모리 장치
US7483310B1 (en) * 2006-11-02 2009-01-27 National Semiconductor Corporation System and method for providing high endurance low cost CMOS compatible EEPROM devices
KR100781041B1 (ko) * 2006-11-06 2007-11-30 주식회사 하이닉스반도체 플래시 메모리 장치 및 그 소거 동작 제어 방법
JP4863844B2 (ja) * 2006-11-08 2012-01-25 セイコーインスツル株式会社 電圧切替回路
US8378407B2 (en) 2006-12-07 2013-02-19 Tower Semiconductor, Ltd. Floating gate inverter type memory cell and array
US7755941B2 (en) * 2007-02-23 2010-07-13 Panasonic Corporation Nonvolatile semiconductor memory device
US7436710B2 (en) 2007-03-12 2008-10-14 Maxim Integrated Products, Inc. EEPROM memory device with cell having NMOS in a P pocket as a control gate, PMOS program/erase transistor, and PMOS access transistor in a common well
JP4855514B2 (ja) * 2007-03-16 2012-01-18 富士通セミコンダクター株式会社 電源スイッチ回路及び半導体集積回路装置
US7663916B2 (en) 2007-04-16 2010-02-16 Taiwan Semicondcutor Manufacturing Company, Ltd. Logic compatible arrays and operations
US7903465B2 (en) * 2007-04-24 2011-03-08 Intersil Americas Inc. Memory array of floating gate-based non-volatile memory cells
JP4455621B2 (ja) * 2007-07-17 2010-04-21 株式会社東芝 エージングデバイス
US8369155B2 (en) * 2007-08-08 2013-02-05 Hynix Semiconductor Inc. Operating method in a non-volatile memory device
JP2009049182A (ja) 2007-08-20 2009-03-05 Toyota Motor Corp 不揮発性半導体記憶素子
US7700993B2 (en) * 2007-11-05 2010-04-20 International Business Machines Corporation CMOS EPROM and EEPROM devices and programmable CMOS inverters
KR101286241B1 (ko) 2007-11-26 2013-07-15 삼성전자주식회사 최대 전압 선택회로
US7968926B2 (en) 2007-12-19 2011-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Logic non-volatile memory cell with improved data retention ability
CN101965638B (zh) * 2008-01-18 2012-12-05 夏普株式会社 非易失性随机存取存储器
US7639536B2 (en) 2008-03-07 2009-12-29 United Microelectronics Corp. Storage unit of single-conductor non-volatile memory cell and method of erasing the same
US7800426B2 (en) 2008-03-27 2010-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Two voltage input level shifter with switches for core power off application
JP5266443B2 (ja) * 2008-04-18 2013-08-21 インターチップ株式会社 不揮発性メモリセル及び不揮発性メモリセル内蔵データラッチ
US8344443B2 (en) 2008-04-25 2013-01-01 Freescale Semiconductor, Inc. Single poly NVM devices and arrays
US8218377B2 (en) * 2008-05-19 2012-07-10 Stmicroelectronics Pvt. Ltd. Fail-safe high speed level shifter for wide supply voltage range
US7894261B1 (en) 2008-05-22 2011-02-22 Synopsys, Inc. PFET nonvolatile memory
US8295087B2 (en) * 2008-06-16 2012-10-23 Aplus Flash Technology, Inc. Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS
KR101462487B1 (ko) * 2008-07-07 2014-11-18 삼성전자주식회사 플래시 메모리 장치 및 그것의 프로그램 방법
US7983081B2 (en) 2008-12-14 2011-07-19 Chip.Memory Technology, Inc. Non-volatile memory apparatus and method with deep N-well
US8189390B2 (en) * 2009-03-05 2012-05-29 Mosaid Technologies Incorporated NAND flash architecture with multi-level row decoding
US8319528B2 (en) * 2009-03-26 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having interconnected transistors and electronic device including semiconductor device
KR101020298B1 (ko) 2009-05-28 2011-03-07 주식회사 하이닉스반도체 레벨 시프터 및 반도체 메모리 장치
CN101650972B (zh) * 2009-06-12 2013-05-29 东信和平科技股份有限公司 智能卡的非易失性存储器数据更新方法
JP2011009454A (ja) * 2009-06-25 2011-01-13 Renesas Electronics Corp 半導体装置
FR2952227B1 (fr) 2009-10-29 2013-09-06 St Microelectronics Rousset Dispositif de memoire du type electriquement programmable et effacable, a deux cellules par bit
EP2323135A1 (en) * 2009-11-12 2011-05-18 SiTel Semiconductor B.V. Method and apparatus for emulating byte wise programmable functionality into sector wise erasable memory
KR101071190B1 (ko) * 2009-11-27 2011-10-10 주식회사 하이닉스반도체 레벨 쉬프팅 회로 및 이를 이용한 비휘발성 반도체 메모리 장치
IT1397229B1 (it) * 2009-12-30 2013-01-04 St Microelectronics Srl Dispositivo di memoria ftp programmabile e cancellabile a livello di cella
CN107293322B (zh) * 2010-02-07 2021-09-21 芝诺半导体有限公司 含导通浮体晶体管、并具有永久性和非永久性功能的半导体存储元件及操作方法
US8284600B1 (en) 2010-02-08 2012-10-09 National Semiconductor Corporation 5-transistor non-volatile memory cell
KR101676816B1 (ko) * 2010-02-11 2016-11-18 삼성전자주식회사 플래시 메모리 장치 및 그것의 프로그램 방법
WO2011118076A1 (ja) 2010-03-23 2011-09-29 シャープ株式会社 半導体装置、アクティブマトリクス基板、及び表示装置
KR101653262B1 (ko) * 2010-04-12 2016-09-02 삼성전자주식회사 멀티-비트 메모리의 프로그램 방법 및 그것을 이용한 데이터 저장 시스템
US8217705B2 (en) 2010-05-06 2012-07-10 Micron Technology, Inc. Voltage switching in a memory device
US8258853B2 (en) * 2010-06-14 2012-09-04 Ememory Technology Inc. Power switch circuit for tracing a higher supply voltage without a voltage drop
US8355282B2 (en) 2010-06-17 2013-01-15 Ememory Technology Inc. Logic-based multiple time programming memory cell
US8958245B2 (en) 2010-06-17 2015-02-17 Ememory Technology Inc. Logic-based multiple time programming memory cell compatible with generic CMOS processes
US9042174B2 (en) 2010-06-17 2015-05-26 Ememory Technology Inc. Non-volatile memory cell
US8279681B2 (en) 2010-06-24 2012-10-02 Semiconductor Components Industries, Llc Method of using a nonvolatile memory cell
US20120014183A1 (en) * 2010-07-16 2012-01-19 Pavel Poplevine 3 transistor (n/p/n) non-volatile memory cell without program disturb
US8044699B1 (en) * 2010-07-19 2011-10-25 Polar Semiconductor, Inc. Differential high voltage level shifter
KR101868332B1 (ko) * 2010-11-25 2018-06-20 삼성전자주식회사 플래시 메모리 장치 및 그것을 포함한 데이터 저장 장치
US8461899B2 (en) * 2011-01-14 2013-06-11 Stmicroelectronics International N.V. Negative voltage level shifter circuit
JP5685115B2 (ja) * 2011-03-09 2015-03-18 セイコーインスツル株式会社 電源切換回路
DE112012002622B4 (de) * 2011-06-24 2017-01-26 International Business Machines Corporation Aufzeichnungseinheit für lineare Aufzeichnung zum Ausführen optimalen Schreibens beim Empfangen einer Reihe von Befehlen, darunter gemischte Lese- und Schreibbefehle, sowie Verfahren und Programm für dessen Ausführung
US9455021B2 (en) 2011-07-22 2016-09-27 Texas Instruments Incorporated Array power supply-based screening of static random access memory cells for bias temperature instability
KR20130022743A (ko) * 2011-08-26 2013-03-07 에스케이하이닉스 주식회사 고전압 생성회로 및 이를 구비한 반도체 장치
US8999785B2 (en) * 2011-09-27 2015-04-07 Tower Semiconductor Ltd. Flash-to-ROM conversion
CN103078618B (zh) * 2011-10-26 2015-08-12 力旺电子股份有限公司 电压开关电路
JP2013102119A (ja) 2011-11-07 2013-05-23 Ememory Technology Inc 不揮発性メモリーセル
US8508971B2 (en) 2011-11-08 2013-08-13 Wafertech, Llc Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate
US9165661B2 (en) * 2012-02-16 2015-10-20 Cypress Semiconductor Corporation Systems and methods for switching between voltages
US9048137B2 (en) 2012-02-17 2015-06-02 Flashsilicon Incorporation Scalable gate logic non-volatile memory cells and arrays
TWI467744B (zh) * 2012-03-12 2015-01-01 Vanguard Int Semiconduct Corp 單層多晶矽可電抹除可程式唯讀記憶裝置
US8787092B2 (en) 2012-03-13 2014-07-22 Ememory Technology Inc. Programming inhibit method of nonvolatile memory apparatus for reducing leakage current
US9390799B2 (en) * 2012-04-30 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory cell devices and methods, having a storage cell with two sidewall bit cells
TWI469328B (zh) 2012-05-25 2015-01-11 Ememory Technology Inc 具可程式可抹除的單一多晶矽層非揮發性記憶體
TWI498901B (zh) * 2012-06-04 2015-09-01 Ememory Technology Inc 利用程式化禁止方法減少漏電流的非揮發性記憶體裝置
US9729145B2 (en) * 2012-06-12 2017-08-08 Infineon Technologies Ag Circuit and a method for selecting a power supply
KR101334843B1 (ko) * 2012-08-07 2013-12-02 주식회사 동부하이텍 전압 출력 회로 및 이를 이용한 네거티브 전압 선택 출력 장치
KR102038041B1 (ko) 2012-08-31 2019-11-26 에스케이하이닉스 주식회사 전원 선택 회로
JP5988062B2 (ja) * 2012-09-06 2016-09-07 パナソニックＩｐマネジメント株式会社 半導体集積回路
US9130553B2 (en) 2012-10-04 2015-09-08 Nxp B.V. Low/high voltage selector
JP5556873B2 (ja) * 2012-10-19 2014-07-23 株式会社フローディア 不揮発性半導体記憶装置
JP6053474B2 (ja) * 2012-11-27 2016-12-27 株式会社フローディア 不揮発性半導体記憶装置
JP2014116547A (ja) 2012-12-12 2014-06-26 Renesas Electronics Corp 半導体装置
JP6078327B2 (ja) * 2012-12-19 2017-02-08 ルネサスエレクトロニクス株式会社 半導体装置
US8963609B2 (en) * 2013-03-01 2015-02-24 Arm Limited Combinatorial circuit and method of operation of such a combinatorial circuit
US9275748B2 (en) * 2013-03-14 2016-03-01 Silicon Storage Technology, Inc. Low leakage, low threshold voltage, split-gate flash cell operation
KR102095856B1 (ko) * 2013-04-15 2020-04-01 삼성전자주식회사 반도체 메모리 장치 및 그것의 바디 바이어스 방법
US9197200B2 (en) 2013-05-16 2015-11-24 Dialog Semiconductor Gmbh Dynamic level shifter circuit
US9362374B2 (en) * 2013-06-27 2016-06-07 Globalfoundries Singapore Pte. Ltd. Simple and cost-free MTP structure
US9520404B2 (en) 2013-07-30 2016-12-13 Synopsys, Inc. Asymmetric dense floating gate nonvolatile memory with decoupled capacitor
CN103456359A (zh) * 2013-09-03 2013-12-18 苏州宽温电子科技有限公司 基于串联晶体管型的改进的差分架构Nor flash存储单元
US9236453B2 (en) * 2013-09-27 2016-01-12 Ememory Technology Inc. Nonvolatile memory structure and fabrication method thereof
US9019780B1 (en) * 2013-10-08 2015-04-28 Ememory Technology Inc. Non-volatile memory apparatus and data verification method thereof
KR20150042041A (ko) * 2013-10-10 2015-04-20 에스케이하이닉스 주식회사 전압발생기, 집적회로 및 전압 발생 방법
FR3012673B1 (fr) * 2013-10-31 2017-04-14 St Microelectronics Rousset Memoire programmable par injection de porteurs chauds et procede de programmation d'une telle memoire
KR102072767B1 (ko) * 2013-11-21 2020-02-03 삼성전자주식회사 고전압 스위치 및 그것을 포함하는 불휘발성 메모리 장치
US9159425B2 (en) * 2013-11-25 2015-10-13 Stmicroelectronics International N.V. Non-volatile memory with reduced sub-threshold leakage during program and erase operations
KR102157875B1 (ko) * 2013-12-19 2020-09-22 삼성전자주식회사 불휘발성 메모리 장치 및 그것을 포함한 메모리 시스템
JP6235901B2 (ja) * 2013-12-27 2017-11-22 ルネサスエレクトロニクス株式会社 半導体装置
US9331699B2 (en) 2014-01-08 2016-05-03 Micron Technology, Inc. Level shifters, memory systems, and level shifting methods
KR20160132405A (ko) * 2014-03-12 2016-11-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN103943570A (zh) * 2014-03-20 2014-07-23 上海华力微电子有限公司 一种一次性编程存储器中金属硅化物掩膜的制备方法
US9508396B2 (en) * 2014-04-02 2016-11-29 Ememory Technology Inc. Array structure of single-ploy nonvolatile memory
JP5745136B1 (ja) * 2014-05-09 2015-07-08 力晶科技股▲ふん▼有限公司 不揮発性半導体記憶装置とその書き込み方法
FR3021804B1 (fr) * 2014-05-28 2017-09-01 Stmicroelectronics Rousset Cellule memoire non volatile duale comprenant un transistor d'effacement
FR3021806B1 (fr) * 2014-05-28 2017-09-01 St Microelectronics Sa Procede de programmation d'une cellule memoire non volatile comprenant une grille de transistor de selection partagee
JP6286292B2 (ja) 2014-06-20 2018-02-28 株式会社フローディア 不揮発性半導体記憶装置
US20160006348A1 (en) * 2014-07-07 2016-01-07 Ememory Technology Inc. Charge pump apparatus
US9431111B2 (en) * 2014-07-08 2016-08-30 Ememory Technology Inc. One time programming memory cell, array structure and operating method thereof
CN104112472B (zh) * 2014-07-22 2017-05-03 中国人民解放军国防科学技术大学 兼容标准cmos工艺的超低功耗差分结构非易失性存储器
CN104361906B (zh) * 2014-10-24 2017-09-19 中国人民解放军国防科学技术大学 基于标准cmos工艺的超低功耗非易失性存储器
US9514820B2 (en) * 2014-11-19 2016-12-06 Stmicroelectronics (Rousset) Sas EEPROM architecture wherein each bit is formed by two serially connected cells
JP6340310B2 (ja) 2014-12-17 2018-06-06 ルネサスエレクトロニクス株式会社 半導体集積回路装置およびウェラブル装置
TWI546903B (zh) * 2015-01-15 2016-08-21 聯笙電子股份有限公司 非揮發性記憶體單元
JP6457829B2 (ja) 2015-02-05 2019-01-23 ルネサスエレクトロニクス株式会社 半導体装置
CN104900266B (zh) * 2015-06-10 2018-10-26 上海华虹宏力半导体制造有限公司 Eeprom存储单元门极控制信号产生电路
US9799395B2 (en) 2015-11-30 2017-10-24 Texas Instruments Incorporated Sense amplifier in low power and high performance SRAM
US9847133B2 (en) 2016-01-19 2017-12-19 Ememory Technology Inc. Memory array capable of performing byte erase operation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200802807A (en) * 2006-06-26 2008-01-01 Ememory Technology Inc Silicon-on-insulator (SOI) memory device
US8941167B2 (en) * 2012-03-08 2015-01-27 Ememory Technology Inc. Erasable programmable single-ploy nonvolatile memory

Also Published As

Publication number Publication date
US9786340B2 (en) 2017-10-10
TWI613659B (zh) 2018-02-01
CN108206186B (zh) 2020-10-13
US20180190357A1 (en) 2018-07-05
CN106981309A (zh) 2017-07-25
EP3410440A1 (en) 2018-12-05
TW201824520A (zh) 2018-07-01
CN108154898B (zh) 2021-02-02
EP3196886B1 (en) 2021-03-31
US20170206968A1 (en) 2017-07-20
EP3410440B1 (en) 2020-05-13
JP6566975B2 (ja) 2019-08-28
CN107017023A (zh) 2017-08-04
US9792993B2 (en) 2017-10-17
US20170207230A1 (en) 2017-07-20
CN106981304B (zh) 2020-02-07
TWI641115B (zh) 2018-11-11
TW201740374A (zh) 2017-11-16
EP3196886A1 (en) 2017-07-26
JP2017130646A (ja) 2017-07-27
JP2017139045A (ja) 2017-08-10
EP3196884A1 (en) 2017-07-26
EP3196883B1 (en) 2019-09-04
US9520196B1 (en) 2016-12-13
JP2017130247A (ja) 2017-07-27
JP6122531B1 (ja) 2017-04-26
EP3196883A1 (en) 2017-07-26
EP3196884B1 (en) 2021-08-04
CN106981311B (zh) 2019-08-30
TWI630615B (zh) 2018-07-21
CN106981299B (zh) 2019-10-18
EP3197051A1 (en) 2017-07-26
TWI613654B (zh) 2018-02-01
TW201801084A (zh) 2018-01-01
US10262746B2 (en) 2019-04-16
TW201727838A (zh) 2017-08-01
US20180261294A1 (en) 2018-09-13
TW201828302A (zh) 2018-08-01
JP2018101767A (ja) 2018-06-28
CN108320772A (zh) 2018-07-24
JP6392379B2 (ja) 2018-09-19
TWI618072B (zh) 2018-03-11
US20170206975A1 (en) 2017-07-20
US10121550B2 (en) 2018-11-06
TW201727651A (zh) 2017-08-01
TWI621123B (zh) 2018-04-11
CN108206186A (zh) 2018-06-26
EP3197051B1 (en) 2020-01-15
US9847133B2 (en) 2017-12-19
US20170206976A1 (en) 2017-07-20
CN106981492B (zh) 2020-10-20
CN108320772B (zh) 2020-07-10
US20170206969A1 (en) 2017-07-20
TW201727632A (zh) 2017-08-01
US20170206970A1 (en) 2017-07-20
US9653173B1 (en) 2017-05-16
US9941011B2 (en) 2018-04-10
TW201830665A (zh) 2018-08-16
US10038003B2 (en) 2018-07-31
TWI587455B (zh) 2017-06-11
TW201727649A (zh) 2017-08-01
US9812212B2 (en) 2017-11-07
CN106981311A (zh) 2017-07-25
JP6285001B2 (ja) 2018-02-28
EP3196885B1 (en) 2019-03-27
US9805776B2 (en) 2017-10-31
TWI614763B (zh) 2018-02-11
US20170206941A1 (en) 2017-07-20
TWI613672B (zh) 2018-02-01
CN107017023B (zh) 2020-05-05
US10096368B2 (en) 2018-10-09
EP3196885A1 (en) 2017-07-26
CN106981309B (zh) 2020-02-14
TW201822212A (zh) 2018-06-16
CN106981307B (zh) 2020-04-07
US20170206945A1 (en) 2017-07-20
TW201737256A (zh) 2017-10-16
CN108154898A (zh) 2018-06-12
US20170207228A1 (en) 2017-07-20
CN106981307A (zh) 2017-07-25
CN106981492A (zh) 2017-07-25
CN106981304A (zh) 2017-07-25
CN106981299A (zh) 2017-07-25
TWI578322B (zh) 2017-04-11
US10255980B2 (en) 2019-04-09

Similar Documents

Publication Publication Date Title
TWI646665B (zh) 具有抹除元件的單層多晶矽非揮發性記憶胞結構
TWI582959B (zh) 具有輔助閘極之非揮發性記憶胞結構及其記憶體陣列
TWI517413B (zh) 非揮發性記憶體結構
TWI514518B (zh) 非揮發性記憶體結構及其製法
US7544569B2 (en) Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
TWI681510B (zh) 單位元多記憶胞之非揮發性記憶體單元
US20130113030A1 (en) Semiconductor device
US10026742B2 (en) Nonvolatile memory devices having single-layered gates
JPH11163303A (ja) 不揮発性半導体記憶装置
US9312014B2 (en) Single-layer gate EEPROM cell, cell array including the same, and method of operating the cell array
US9368506B2 (en) Integrated circuits and methods for operating integrated circuits with non-volatile memory
US10032852B2 (en) Single poly nonvolatile memory cells
KR20030003675A (ko) 비휘발성 반도체 기억장치 및 반도체 집적회로 장치
US9935117B2 (en) Single poly nonvolatile memory cells, arrays thereof, and methods of operating the same
US20080179656A1 (en) Semiconductor device, nonvolatile semiconductor memory device and manufacturing method of semiconductor device
US20120069651A1 (en) EEPROM-based, data-oriented combo NVM design
TWI601272B (zh) 半導體裝置
JPH11238814A (ja) 半導体記憶装置およびその制御方法
US20160197153A1 (en) Nonvolatile memory devices having single-layered floating gates
US10395742B2 (en) Semiconductor device
US7639536B2 (en) Storage unit of single-conductor non-volatile memory cell and method of erasing the same