TWI643242B - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- TWI643242B TWI643242B TW106103788A TW106103788A TWI643242B TW I643242 B TWI643242 B TW I643242B TW 106103788 A TW106103788 A TW 106103788A TW 106103788 A TW106103788 A TW 106103788A TW I643242 B TWI643242 B TW I643242B
- Authority
- TW
- Taiwan
- Prior art keywords
- peeling
- support substrate
- manufacturing
- wafer
- semiconductor device
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
本發明之實施形態之半導體裝置之製造方法係於將經薄膜化之半導體晶圓自支持基板剝離時,降低對半導體晶圓之損傷。 實施形態之半導體裝置之製造方法係於線剝離結束位置E2,藉由將爪6A之前端插入至支持基板1與接著層2之間而於支持基板1設置剝離面H1,且於線剝離開始位置E1,藉由將爪6B之前端插入至支持基板1與接著層2之間而於支持基板1設置剝離面H2,使剝離線LH沿剝離方向DH移動,而將支持基板1自半導體晶圓W剝離。The method for manufacturing a semiconductor device according to the embodiment of the present invention is to reduce the damage to the semiconductor wafer when the thinned semiconductor wafer is peeled from the supporting substrate. The manufacturing method of the semiconductor device according to the embodiment is at the wire stripping end position E2. The front end of the claw 6A is inserted between the supporting substrate 1 and the bonding layer 2 to provide a peeling surface H1 on the supporting substrate 1. E1, by inserting the front end of the claw 6B between the supporting substrate 1 and the bonding layer 2 to provide a peeling surface H2 on the supporting substrate 1 so that the peeling line LH moves in the peeling direction DH, and the supporting substrate 1 is removed from the semiconductor wafer W Peel off.
Description
本發明之實施形態係關於一種半導體裝置之製造方法。An embodiment of the present invention relates to a method for manufacturing a semiconductor device.
於半導體裝置之製造製程中,有時於將半導體晶圓薄膜化之前將半導體晶圓貼附於支持基板。貼附於支持基板之半導體晶圓於將半導體晶圓薄膜化之後,自支持基板剝離。In the manufacturing process of a semiconductor device, a semiconductor wafer may be attached to a support substrate before the semiconductor wafer is thinned. After the semiconductor wafer attached to the support substrate is thinned, the semiconductor wafer is peeled from the support substrate.
本發明之一實施形態提供一種半導體裝置之製造方法,該半導體裝置之製造方法於將經薄膜化之半導體晶圓自支持基板剝離時,可使半導體晶圓所受之損壞減少。 實施形態之半導體裝置之製造方法係於已接著晶圓之支持基板之外周之至少一部分形成剝離面,上述晶圓於其表面形成有半導體元件,且將上述表面朝向上述支持基板側而接著;且,從上述剝離面來看隔著上述支持基板之幾何學重心朝向上述剝離面之方向,將上述晶圓與上述支持基板剝離。An embodiment of the present invention provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device can reduce damage to a semiconductor wafer when peeling a thin-filmed semiconductor wafer from a supporting substrate. A method of manufacturing a semiconductor device according to an embodiment is to form a peeling surface on at least a part of the outer periphery of a support substrate that has been bonded to a wafer, the semiconductor element is formed on the surface of the wafer, and the surface is directed toward the support substrate side; From the perspective of the peeling surface, the wafer is separated from the supporting substrate through the geometric center of gravity of the supporting substrate toward the peeling surface.
以下,參照隨附圖式,對實施形態之半導體裝置之製造方法進行詳細說明。再者,本發明並非由該等實施形態限定。 (第1實施形態) 圖1(a)~圖1(d)及圖2(a)~圖2(b)係表示第1實施形態之半導體裝置之製造方法之剖視圖,圖3(a)~圖3(c)係表示第1實施形態之半導體裝置之製造方法之俯視圖。 於圖1(a)中,於半導體晶圓W之正面側形成器件層DV。此時,半導體晶圓W之厚度可以能夠以半導體晶圓W單體穩定地操作之方式設定。例如,半導體晶圓W之厚度可設定為100 μm以上。半導體晶圓W之材料例如可使用Si、Ge、SiGe、GaAs、GaAlAs、InP、GaP、GaN、SiC或InGaAsP等。器件層DV中可包含形成於半導體晶圓W之作用區域及形成於半導體晶圓W上之配線層等。可於作用區域中設置通道區域、源極層及汲極層。可於配線層設置閘極電極及配線等。形成於器件層DV之器件可為記憶體元件,亦可為電晶體元件。亦可形成邏輯電路、處理器或NAND(Not AND,反及)快閃記憶體等積體電路。 然後,介隔接著層2將半導體晶圓W之正面側固定於支持基板1。又,支持基板1之形狀可與半導體晶圓W之形狀對應。此時,支持基板1之外形亦可大於半導體晶圓W。又,支持基板1之材料可為Si,亦可為玻璃。接著層2之材料可使用能夠藉由加熱等剝離且剝離後不具有黏著性之材料。例如,接著層2之材料可使用熱固性樹脂。 繼而,如圖1(b)所示,利用CMP(Chemical Mechanical Polishing,化學機械研磨)等方法對半導體晶圓W之背面側進行研磨,藉此將半導體晶圓W薄膜化。此時,半導體晶圓W之厚度可設定為50 μm以下。再者,亦可於將半導體晶圓W薄膜化之後,包括於半導體晶圓W形成貫通電極之步驟、或於半導體晶圓W形成背面電極之步驟等。 繼而,如圖1(c)所示,將半導體晶圓W之背面側貼附於支撐帶3。此時,支撐帶3可利用環4支持。支撐帶3之材料可使用具有黏著性之樹脂膜等。此時,亦可使用切割帶作為支撐帶3。環4之材料例如可使用不鏽鋼等。此處,藉由將半導體晶圓W貼附於支撐帶3,即便於半導體晶圓W薄膜化後將支持基板1自半導體晶圓W剝離之情形時,亦可防止半導體晶圓W折損。 繼而,如圖1(d)所示,將貼附有半導體晶圓W之支撐帶3固定於台5。此時,可藉由將支持支撐帶3之環4嵌入至台5而將支撐帶3固定於台5。為了使支撐帶3之固定之穩定性提昇,亦可對台5採用多孔吸盤等。 繼而,如圖2(a)及圖3(a)所示,於線剝離結束位置E2,藉由將爪6A之前端插入至支持基板1與接著層2之間而於支持基板1設置剝離面H1。 繼而,如圖2(b)及圖3(b)所示,於線剝離開始位置E1,藉由將爪6B之前端插入至支持基板1與接著層2之間而於支持基板1設置剝離面H2。此時,線剝離結束位置E2可隔著支持基板1之中心(幾何學重心)而設置於與線剝離開始位置E1為相反側之支持基板1之外周。可將各爪6A、6B以能夠插入至支持基板1與接著層2之間之方式使前端變尖。各爪6A、6B可為鏟狀,亦可為楔狀。又,可分別對應於線剝離結束位置E2及線剝離開始位置E1而個別地設置爪6A、6B,亦可於線剝離結束位置E2及線剝離開始位置E1共用1個爪。此時,可構成為能夠將爪移動至線剝離結束位置E2及線剝離開始位置E1之位置。 繼而,如圖3(c)所示,藉由使剝離線LH沿剝離方向DH移動,而將支持基板1自半導體晶圓W剝離。剝離方向DH可設定為自線剝離開始位置E1朝向線剝離結束位置E2。此時,為了使剝離線LH沿剝離方向DH移動,可於較剝離線LH更靠線剝離開始位置E1側吸附支持基板1,並且於較剝離線LH更靠線剝離結束位置E2側對支持基板1加壓。然後,藉由使剝離線LH沿剝離方向DH移動直至到達至剝離面H1,可將支持基板1自半導體晶圓W剝離。該剝離線LH可呈直線狀設置於支持基板1與半導體晶圓W之密接面與剝離面之交界。線剝離係指藉由使剝離線LH沿剝離方向DH移動而將支持基板1自半導體晶圓W剝離。 此處,若線剝離推進,則支持基板1與半導體晶圓W之密接面變小。此時,若於線剝離結束位置E2不存在剝離面H1,則難以確保盡可能對抗支持基板1之剛性之密接面之面積。因此,有可能於剝離之最終階段,不能克服支持基板1之剛性因而剩餘之密接面一下子剝離(面剝離),而對器件層DV造成損壞。 相對於此,藉由在線剝離開始前於線剝離結束位置E2形成剝離面H1,可於維持線剝離之狀態下到達至剝離面H1。因此,可防止於剝離之最終階段剩餘之密接面一下子剝離,而可減少對器件層DV施加之負載。 (第2實施形態) 圖4(a)~圖4(c)係表示第2實施形態之半導體裝置之製造方法之俯視圖。 於圖4(a)之線剝離開始位置E1,藉由將爪6A之前端插入至支持基板1與接著層2之間而於支持基板1設置剝離面H1。 繼而,如圖4(b)所示,於將爪6A之前端插入至支持基板1與接著層2之間之狀態下,使爪6A沿著支持基板1之外周旋轉1周,藉此,遍及支持基板1之全周設置剝離面H3。 繼而,如圖4(c)所示,藉由使剝離線LH沿剝離方向DH移動,而將支持基板1自半導體晶圓W剝離。剝離方向DH可設定為自線剝離開始位置E1朝向線剝離結束位置E2。 此處,藉由遍及支持基板1之全周設置剝離面H3之後進行線剝離,可縮短剝離線LH之長度,而可降低剝離線時之支持基板1之剛性,並且可防止於剝離之最終階段剩餘之密接面一下子剝離,從而可減少對器件層DV施加之負載。 已對本發明之若干實施形態進行了說明,但該等實施形態係作為示例而提出,並不意圖限定發明之範圍。該等新穎之實施形態能夠以其他多種形態實施,可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。該等實施形態及其變化皆包含於發明之範圍或主旨中,並且包含於申請專利範圍所記載之發明及其均等之範圍內。 [相關申請案] 本申請案主張日本專利申請案2016-46605號(申請日:2016年3月10日)之優先權。該案之全部內容以引用的方式併入本文中。Hereinafter, a method for manufacturing a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings. The present invention is not limited by these embodiments. (First Embodiment) FIGS. 1 (a) to 1 (d) and FIGS. 2 (a) to 2 (b) are cross-sectional views showing a method for manufacturing a semiconductor device according to a first embodiment, and FIGS. 3 (a) to Fig. 3 (c) is a plan view showing a method for manufacturing a semiconductor device according to the first embodiment. In FIG. 1 (a), a device layer DV is formed on the front side of the semiconductor wafer W. At this time, the thickness of the semiconductor wafer W can be set in such a manner that the semiconductor wafer W alone can be stably operated. For example, the thickness of the semiconductor wafer W can be set to 100 μm or more. As a material of the semiconductor wafer W, for example, Si, Ge, SiGe, GaAs, GaAlAs, InP, GaP, GaN, SiC, or InGaAsP can be used. The device layer DV may include an active region formed on the semiconductor wafer W, a wiring layer formed on the semiconductor wafer W, and the like. A channel region, a source layer, and a drain layer can be set in the active region. Gate electrodes and wiring can be provided on the wiring layer. The device formed on the device layer DV may be a memory element or a transistor element. It can also form integrated circuits such as logic circuits, processors, or NAND (Not AND) flash memories. Then, the front surface side of the semiconductor wafer W is fixed to the support substrate 1 by the interposing adhesive layer 2. The shape of the support substrate 1 may correspond to the shape of the semiconductor wafer W. At this time, the shape of the support substrate 1 may be larger than the semiconductor wafer W. The material of the support substrate 1 may be Si or glass. As the material of the subsequent layer 2, a material that can be peeled off by heating or the like and has no adhesiveness after peeling can be used. For example, a thermosetting resin can be used as the material of the second layer. Next, as shown in FIG. 1 (b), the semiconductor wafer W is thinned by polishing the rear surface side of the semiconductor wafer W by a method such as CMP (Chemical Mechanical Polishing). At this time, the thickness of the semiconductor wafer W can be set to 50 μm or less. Furthermore, after the semiconductor wafer W is formed into a thin film, a step of forming a through electrode on the semiconductor wafer W or a step of forming a back electrode on the semiconductor wafer W may be included. Then, as shown in FIG. 1 (c), the back surface side of the semiconductor wafer W is attached to the support tape 3. At this time, the support band 3 can be supported by the ring 4. As the material of the support tape 3, an adhesive resin film or the like can be used. In this case, a dicing tape may be used as the support tape 3. The material of the ring 4 can be, for example, stainless steel. Here, by attaching the semiconductor wafer W to the support tape 3, the semiconductor wafer W can be prevented from being broken even when the support substrate 1 is peeled from the semiconductor wafer W after the semiconductor wafer W is thinned. Then, as shown in FIG. 1 (d), the support tape 3 to which the semiconductor wafer W is attached is fixed to the stage 5. At this time, the support band 3 can be fixed to the table 5 by inserting the ring 4 of the support band 3 into the table 5. In order to improve the stability of the support band 3, a porous suction cup or the like may be used for the table 5. Then, as shown in FIG. 2 (a) and FIG. 3 (a), at the end of the wire stripping position E2, the front end of the claw 6A is inserted between the support substrate 1 and the bonding layer 2 to provide a peeling surface on the support substrate 1. H1. Next, as shown in FIG. 2 (b) and FIG. 3 (b), at the line peeling start position E1, the front end of the claw 6B is inserted between the supporting substrate 1 and the bonding layer 2 to provide a peeling surface on the supporting substrate 1. H2. At this time, the line peeling end position E2 may be provided on the outer periphery of the support substrate 1 on the side opposite to the line peeling start position E1 via the center (geometric center of gravity) of the support substrate 1. Each of the claws 6A and 6B can be sharpened so that the tip can be inserted between the support substrate 1 and the bonding layer 2. Each of the claws 6A and 6B may be shovel-shaped or wedge-shaped. Further, the claws 6A and 6B may be provided individually corresponding to the line peeling end position E2 and the line peeling start position E1, respectively, and one claw may be shared at the line peeling end position E2 and the line peeling start position E1. At this time, it can be comprised so that a claw can be moved to the position of the thread peeling end position E2, and the thread peeling start position E1. Next, as shown in FIG. 3 (c), the support substrate 1 is separated from the semiconductor wafer W by moving the separation line LH in the separation direction DH. The peeling direction DH can be set from the wire peeling start position E1 to the wire peeling end position E2. At this time, in order to move the peeling line LH in the peeling direction DH, the supporting substrate 1 may be adsorbed on the line peeling start position E1 side than the peeling line LH, and the supporting substrate 1 may be positioned closer to the wire peeling end position E2 side than the peeling line LH. 1 Pressurize. Then, by moving the peeling line LH in the peeling direction DH until reaching the peeling surface H1, the support substrate 1 can be peeled from the semiconductor wafer W. The peeling line LH may be provided in a straight line at the boundary between the adhesion surface and the peeling surface of the support substrate 1 and the semiconductor wafer W. The line peeling means that the support substrate 1 is peeled from the semiconductor wafer W by moving the peeling line LH in the peeling direction DH. Here, if the wire peeling advances, the contact surface between the support substrate 1 and the semiconductor wafer W becomes smaller. At this time, if the peeling surface H1 does not exist at the line peeling end position E2, it is difficult to ensure the area of the close contact surface that resists the rigidity of the support substrate 1 as much as possible. Therefore, in the final stage of peeling, it is possible that the rigidity of the supporting substrate 1 cannot be overcome and the remaining close contact surfaces are suddenly peeled off (surface peeling), which may damage the device layer DV. In contrast, by forming the peeling surface H1 at the linear peeling end position E2 before the start of the linear peeling, it is possible to reach the peeling surface H1 while maintaining the linear peeling. Therefore, it is possible to prevent the close contact surface remaining in the final stage of the peeling from peeling off at once, and to reduce the load applied to the device layer DV. (Second Embodiment) Figs. 4 (a) to 4 (c) are plan views showing a method for manufacturing a semiconductor device according to a second embodiment. At the peeling start position E1 on the line in FIG. 4 (a), a peeling surface H1 is provided on the support substrate 1 by inserting the front end of the claw 6A between the support substrate 1 and the adhesive layer 2. Next, as shown in FIG. 4 (b), in a state where the front end of the claw 6A is inserted between the support substrate 1 and the bonding layer 2, the claw 6A is rotated along the outer periphery of the support substrate 1 for one cycle, thereby spreading A peeling surface H3 is provided on the entire periphery of the support substrate 1. Then, as shown in FIG. 4 (c), the support substrate 1 is separated from the semiconductor wafer W by moving the separation line LH in the separation direction DH. The peeling direction DH can be set from the wire peeling start position E1 to the wire peeling end position E2. Here, by setting the peeling surface H3 over the entire periphery of the support substrate 1 and performing line peeling, the length of the peeling line LH can be shortened, the rigidity of the support substrate 1 when the peeling line is reduced, and the final stage of peeling can be prevented. The remaining tight contact surfaces are peeled off at once, thereby reducing the load applied to the device layer DV. A number of embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and variations are included in the scope or gist of the invention, and are included in the invention described in the scope of patent application and its equivalent scope. [Related Applications] This application claims the priority of Japanese Patent Application No. 2016-46605 (application date: March 10, 2016). The entire contents of the case are incorporated herein by reference.
1‧‧‧支持基板 1‧‧‧ support substrate
2‧‧‧接著層 2‧‧‧ Adjacent layer
3‧‧‧支撐帶 3‧‧‧ support belt
4‧‧‧環 4‧‧‧circle
5‧‧‧台 5th floor
6A、6B‧‧‧爪 6A, 6B‧‧‧Jaw
DH DH
DV‧‧‧器件層 DV‧‧‧device layer
E1‧‧‧線剝離開始位置 E1‧‧‧line stripping start position
E2‧‧‧線剝離結束位置 E2‧‧‧ line stripping end position
H1‧‧‧剝離面 H1‧‧‧ peeling surface
H2‧‧‧剝離面 H2‧‧‧ peeling surface
H3‧‧‧剝離面 H3‧‧‧ peeling surface
LH‧‧‧剝離線 LH‧‧‧ Stripping Line
W‧‧‧半導體晶圓 W‧‧‧Semiconductor wafer
圖1(a)~圖1(d)係表示第1實施形態之半導體裝置之製造方法之剖視圖。 圖2(a)~圖2(b)係表示第1實施形態之半導體裝置之製造方法之剖視圖。 圖3(a)~圖3(c)係表示第1實施形態之半導體裝置之製造方法之俯視圖。 圖4(a)~圖4(c)係表示第2實施形態之半導體裝置之製造方法之俯視圖。1 (a) to 1 (d) are sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. 2 (a) to 2 (b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. 3 (a) to 3 (c) are plan views showing a method for manufacturing a semiconductor device according to the first embodiment. 4 (a) to 4 (c) are plan views showing a method for manufacturing a semiconductor device according to a second embodiment.
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP??2016-046605 | 2016-03-10 | ||
JP2016046605A JP2017163009A (en) | 2016-03-10 | 2016-03-10 | Method of manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201802865A TW201802865A (en) | 2018-01-16 |
TWI643242B true TWI643242B (en) | 2018-12-01 |
Family
ID=59830594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW106103788A TWI643242B (en) | 2016-03-10 | 2017-02-06 | Manufacturing method of semiconductor device |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2017163009A (en) |
CN (1) | CN107180781B (en) |
TW (1) | TWI643242B (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201529328A (en) * | 2013-11-28 | 2015-08-01 | Nitto Denko Corp | Method of separating plates |
TW201545888A (en) * | 2014-02-27 | 2015-12-16 | Tokyo Electron Ltd | Peeling method, computer storage medium, peeling device, and peeling system |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5268065A (en) * | 1992-12-21 | 1993-12-07 | Motorola, Inc. | Method for thinning a semiconductor wafer |
JP2007109927A (en) * | 2005-10-14 | 2007-04-26 | Tokyo Seimitsu Co Ltd | Method and device for peeling surface protection film |
JP4353975B2 (en) * | 2006-11-29 | 2009-10-28 | 日東電工株式会社 | Adhesive sheet sticking / peeling method, adhesive sheet sticking device, and adhesive sheet peeling device |
US8950459B2 (en) * | 2009-04-16 | 2015-02-10 | Suss Microtec Lithography Gmbh | Debonding temporarily bonded semiconductor wafers |
EP2706562A3 (en) * | 2009-09-01 | 2014-09-03 | EV Group GmbH | Device and method for releasing a semiconductor wafer from a carrier substrate by tilting a film frame |
CN102844843A (en) * | 2010-02-12 | 2012-12-26 | 积水化学工业株式会社 | Dicing/die-bonding tape and method for manufacturing semiconductor chip provided with adhesive layer |
DE102012112989A1 (en) * | 2012-12-21 | 2014-06-26 | Ev Group E. Thallner Gmbh | Method for applying a temporary boundary layer |
US9613845B2 (en) * | 2014-01-17 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Immersion de-taping |
JP6446290B2 (en) * | 2014-04-22 | 2018-12-26 | 東京応化工業株式会社 | Adhesive composition, laminate and peeling method |
JP6366996B2 (en) * | 2014-05-19 | 2018-08-01 | 株式会社ディスコ | Lift-off method |
-
2016
- 2016-03-10 JP JP2016046605A patent/JP2017163009A/en not_active Abandoned
-
2017
- 2017-02-06 TW TW106103788A patent/TWI643242B/en not_active IP Right Cessation
- 2017-03-08 CN CN201710133211.6A patent/CN107180781B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201529328A (en) * | 2013-11-28 | 2015-08-01 | Nitto Denko Corp | Method of separating plates |
TW201545888A (en) * | 2014-02-27 | 2015-12-16 | Tokyo Electron Ltd | Peeling method, computer storage medium, peeling device, and peeling system |
Also Published As
Publication number | Publication date |
---|---|
CN107180781A (en) | 2017-09-19 |
TW201802865A (en) | 2018-01-16 |
CN107180781B (en) | 2020-10-20 |
JP2017163009A (en) | 2017-09-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10186447B2 (en) | Method for bonding thin semiconductor chips to a substrate | |
US8975160B2 (en) | Manufacturing method for semiconductor device | |
WO2014188879A1 (en) | Method for manufacturing semiconductor device | |
CN105990208A (en) | A manufacturing method of a lamination device | |
JP2016174145A5 (en) | ||
TWI256112B (en) | Dicing film having shrinkage release film and method of manufacturing semiconductor package using the same | |
US20140054748A1 (en) | Edge trimming method for semiconductor wafer and semiconductor wafer having trimmed edge | |
JP6502874B2 (en) | Semiconductor device manufacturing method | |
TWI643242B (en) | Manufacturing method of semiconductor device | |
TWI623995B (en) | Manufacturing method of semiconductor device | |
US20150340264A1 (en) | Method of application of a carrier to a device wafer | |
JP6209097B2 (en) | Wafer processing method | |
JP2011054648A (en) | Method of manufacturing semiconductor device | |
US8173245B2 (en) | Peelable tape carrier | |
JP4342340B2 (en) | Manufacturing method of semiconductor device | |
JP2007036074A (en) | Method for manufacturing semiconductor device | |
US10043701B2 (en) | Substrate removal from a carrier | |
US10818501B2 (en) | Method for manufacturing semiconductor device | |
US11094684B2 (en) | Edge cut debond using a temporary filler material with no adhesive properties and edge cut debond using an engineered carrier to enable topography | |
JP2024088265A (en) | Method for grinding workpiece, and method for grinding package substrate | |
JP2019186291A (en) | Wafer processing method | |
JP2013258228A (en) | Semiconductor device manufacturing method | |
JP2021048306A5 (en) | ||
KR20210018047A (en) | Method for peeling resin sheet | |
JP2014207256A (en) | Semiconductor device and method of manufacturing semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |