TWI641082B - Semiconductor device and method for forming the same - Google Patents

Abstract

The present disclosure relates to a semiconductor device including an insulating layer upper semiconductor substrate, wherein the insulating layer upper semiconductor substrate includes a bottom plate, a buried oxide layer provided on the bottom plate, and a semiconductor layer disposed on the buried oxide layer. The semiconductor device further includes a first dielectric layer disposed on the semiconductor layer, a first contact structure extending from the upper surface of the first dielectric layer into the semiconductor layer, passing through the buried oxide layer and connecting the bottom plate, and extending into the semiconductor The first groove of the layer. Wherein the width of the first trench is smaller than the width of the first contact structure, and the first dielectric layer seals the first trench near the top of the first trench to form a vacuum gap.

Description

 Semiconductor device and method of forming same  

The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a semiconductor substrate on insulator (SOI).

Semiconductor devices have been widely used in various electronic products such as, for example, personal computers, mobile phones, and digital cameras. The semiconductor device is usually fabricated by sequentially depositing an insulating layer or a dielectric layer material, a conductive layer material, and a semiconductor layer material on a semiconductor substrate, and then patterning the various material layers formed by using a lithography process, whereby the semiconductor substrate is formed thereon. Circuit parts and components are formed on top.

Among them, the semiconductor element on the insulating layer is expected in the semiconductor industry because of its potential advantages such as fast operation, low power consumption, latch-up immunity, process simplification, and small size.

When a semiconductor element on an insulating layer is used, it is sometimes necessary to apply a voltage to the substrate, and thus it is necessary to form an associated conductive structure and isolation structure. However, there are still many room for improvement in the current technology.

The present invention provides a semiconductor device comprising: a semiconductor substrate on an insulating layer, wherein the semiconductor substrate on the insulating layer comprises a bottom plate, a buried oxide layer provided on the bottom plate, and a semiconductor layer provided on the buried oxide layer. The first dielectric layer is disposed on the semiconductor layer. The first contact structure extends from the upper surface of the first dielectric layer into the semiconductor layer and through the buried oxide layer and connects to the bottom plate. The first trench extends into the semiconductor layer, wherein the width of the first trench is less than the width of the first contact structure, wherein the first dielectric layer seals the first trench near the top of the first trench to form a vacuum gap.

The present disclosure also provides a method of forming a semiconductor device, comprising: providing a semiconductor substrate on an insulating layer, wherein the semiconductor substrate on the insulating layer comprises a bottom plate, a buried oxide layer disposed on the bottom plate, and a semiconductor layer disposed on the buried oxide layer. Forming a first trench and a second trench, the first trench and the second trench extending into the semiconductor layer and exposing a surface of the buried oxide layer, wherein the width of the first trench is smaller than the width of the second trench. A first dielectric layer is formed over the semiconductor layer, wherein the first dielectric layer does not fill the first trench and seals the first trench near the top of the first trench to form a vacuum gap. An etching step is performed to remove a portion of the first dielectric layer and remove a portion of the buried oxide layer under the second trench to expose the substrate, wherein the first dielectric layer still seals the first trench after the etching step. A conductive material is filled in the second trench to form a first contact structure, wherein the first contact structure is connected to the bottom plate.

100‧‧‧Substrate

102‧‧‧floor

104‧‧‧ buried oxide layer

106‧‧‧Semiconductor layer

202‧‧‧hard mask layer

202a, 202b‧‧‧ openings

402‧‧‧First groove

404‧‧‧Second trench

502‧‧‧First dielectric layer

504, 506‧‧ ‧ vacuum gap

602‧‧‧ third trench

702‧‧‧First contact structure

802‧‧‧Interlayer dielectric layer

804‧‧‧Second contact structure

60‧‧‧ etching process

T‧‧‧thickness

W ₁ , W ₂ ‧ ‧ width

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It is noted that the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the components may be enlarged or reduced to clearly show the technical features of the present disclosure.

Figures 1-4, 5A, 5B, and 6-8 are a series of cross-sectional views for explaining the manufacturing process of the semiconductor device of the disclosed embodiment.

The following disclosure provides many different embodiments or examples to implement various features of the present invention. The following disclosure sets forth specific examples of various components and their arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the disclosure describes a first feature formed on or above a second feature, that is, it may include an embodiment in which the first feature is in direct contact with the second feature, and may also include additional Features are formed between the first feature and the second feature described above, such that the first feature and the second feature may not be in direct contact with each other. In addition, different examples of the following disclosure may reuse the same reference symbols and/or labels. These repetitions are not intended to limit the specific relationship between the various embodiments and/or structures discussed.

Various variations of the embodiments are described below. For ease of explanation, similar component numbers may be used to identify similar components. It will be appreciated that additional operational steps may be performed before, during or after the method, and that in other embodiments of the method, portions of the operational steps may be substituted or omitted.

The method for forming the semiconductor device of the present disclosure can be directly defined by forming a dielectric layer with poor step coverage on the trenches having different widths, and by stacking the dielectric layers on different width trenches. The location of the subsequently formed isolation structure and conductive structure is eliminated without the use of an additional etching mask.

Figure 1 depicts the initial steps of some embodiments of the present disclosure. First, a semiconductor-on-insulator (SOI) 100 is provided, which includes a bottom plate 102 having two opposite first sides (or front sides) and a second side (or back side), and is disposed on the bottom plate. A buried oxide layer 104 on the first side of the 102, and a semiconductor layer 106 disposed on the buried oxide layer 104. For example, the backplane 102 and the semiconductor layer 106 can each comprise a germanium, and the buried oxide layer 104 can comprise germanium dioxide. In some other embodiments, the semiconductor layer 106 may be an elemental semiconductor other than germanium, such as germanium; a compound semiconductor such as silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide. (indium arsenide, InAs) or indium phosphide (InP); alloy semiconductors such as: Silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide , GaAsP) or gallium indium phosphide (GaInP).

Various semiconductor elements can be formed over the semiconductor layer 106. The above semiconductor elements may be various active elements, passive elements, other suitable semiconductor elements, or a combination thereof. For example, the active elements may be various types of transistors (eg, metal oxide semiconductor field effect transistors, complementary metal oxide semiconductor transistors, bipolar interface transistors, high voltage transistors, high frequency transistors, or The horizontally diffused gold oxide half field effect transistor), or the diode, the passive component described above may be a resistor or a capacitor. Various processes (eg, deposition, etching, implantation, photolithography, annealing, and/or other suitable processes) can be performed to form semiconductor components. This part of the process is omitted here because it is not a feature of the case.

Next, as shown in FIG. 2, a hard mask layer 202 is formed over the semiconductor layer 106. For example, the hard mask layer 202 can be tantalum nitride, tantalum oxide, other suitable materials, or a combination thereof. In some embodiments, the hard mask layer 202 can be formed by low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), other suitable methods, or a combination thereof.

Next, as shown in FIG. 3, the hard mask 202 is patterned to form openings 202a, 202b. The openings 202a and 202b respectively correspond to patterns of the isolation structure and the contact structure to be formed later. The above patterning process may include a lithography process and an etch process. The above lithography process may include photoresist coating (eg, spin coating), soft baking, mask aligning, exposure, and post-exposure baking (post- Exposure), developing photoresist, rising, drying (eg, hard baking); etching process can be dry etching (eg, anisotropic plasma etching), wet etching, Or a combination thereof.

Next, as shown in FIG. 4, an etching process is performed by using the patterned mask 202 as an etching mask to remove a portion of the semiconductor layer 106, and the first trench 402 and the second trench are formed in the semiconductor layer 106. 404 and exposes a portion of the upper surface of the buried oxide layer 104. In a subsequent step, the first trench 402 is sealed to form an isolation structure, and a conductive material is filled in the second trench 404 to form a conductive structure. The opening of the first trench 402 has a first width W ₁ and the opening of the second trench 404 has a second width W ₂ . In some embodiments, the first width W _{1 is} less than the second width W ₂ . For example, the first width W ₁ may be 1:1.2 to 1:5 than the second width W ₂ (W ₁ :W ₂ ). The depth of the first trench 402 and the second trench 404 may be 2 μm to 80 μm. In addition, each of the first trench 402 and the second trench 404 may be annular, circular, rectangular, or other suitable shape in the upper view.

The etching process may be dry etching (eg, anisotropic plasma etching), wet etching, or a combination thereof, in some embodiments using dry etching, It is advantageous to form the first trench 402 and the second trench 404 with a high aspect ratio. It should be noted that although the hard mask 202 is used as an embodiment of the etching mask, in some other embodiments, the patterned photoresist may be directly used as an etching mask to etch the semiconductor layer 106. The first trench 402 and the second trench 404.

Next, as shown in FIGS. 5A-5B, a first dielectric layer 502 is formed over the hard mask 202, over the sidewalls of the first trench 402 and the second trench 404, and the first trench 402 and The trench 404 is exposed above the upper surface of the buried oxide layer 104.

In some embodiments, the first dielectric layer 502 seals the first trench 402 and the second trench 404 is not sealed (as shown in FIG. 5A). For example, the first dielectric layer 502 can be formed in a vacuum environment by plasma chemical vapor deposition or other deposition process with poor step coverage, such that the first dielectric layer 502 has not filled the first trench. At 402 and the second trench 404, the first trench 402 has been sealed near the top of the opening of the first trench 402 to form a high vacuum vacuum gap 504. For example, vacuum gap 504 can provide good isolation. In addition, since the width W _{2 of the} second trench is larger than the width W _{1 of the} first trench, the first dielectric layer 502 has not sealed the second trench 404 when the vacuum gap 504 is formed. In some embodiments, the top of the vacuum gap 504 tapers toward the upper surface of the first dielectric layer 502 to form a taper.

In some other embodiments, the first dielectric layer 502 can continue to be deposited to further seal the second trench 404 (as shown in FIG. 5B) to form a high vacuum vacuum gap 506. It should be noted that the first dielectric The thickness t of layer 502 over vacuum gap 506 is less than the thickness on vacuum gap 504 to facilitate subsequent etching processes.

For example, the first dielectric layer 502 may include yttrium oxide, tantalum nitride, hafnium oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or other suitable materials or Combination of the above. In some embodiments, the material of the first dielectric layer 502 is a silane-based oxide, a Tetraethyl orthosilicate (TEOS-based oxide) or the like. combination.

Next, as shown in FIG. 6, an etching process 60 is performed to remove a portion of the first dielectric layer 502, and remove a portion of the buried oxide layer 104 under the second trench 404 or vacuum gap 506 to form an exposed portion. A third trench 602 on the upper surface of the bottom plate 102. For example, the etching process described above can be dry etching (eg, anisotropic plasma etching), wet etching, or a combination thereof. In some embodiments, after the etching process 60 is performed, a portion of the first dielectric layer 502 remains on the sidewalls of the third trench, and in other embodiments, the first dielectric layer on the sidewalls of the third trench. 502 was completely removed.

It should be noted that while forming the third trench 602, the first dielectric layer 502 still seals the first trench 402 while leaving the vacuum gap 504 substantially intact, thus providing good isolation. Additionally, at least in part due to the second trench 504 not being sealed by the first dielectric layer 502 (as shown in FIG. 5A), or the first dielectric layer 502 having a thickness on the vacuum gap 506 that is less than the vacuum gap 504 The thickness (as shown in FIG. 5B), in the embodiment of the present disclosure, after forming the first dielectric layer 502 and before performing the etching process 60, it is not necessary to form patterned light on the first dielectric layer 502. The etching mask of the resist layer defines the position of the third trench 602, thereby avoiding the problem that the photoresist cannot be developed completely when the trench is deep (for example, greater than 3 μm), and the cost of the mask and the yellow light process can be reduced. And reducing the thickness of the dielectric layer.

Next, as shown in FIG. 7, a conductive material is filled in the third trench 602 to form a first contact structure 702 electrically connected to the bottom plate 102. For example, the first contact structure 702 can be formed of a metallic material (eg, tungsten, aluminum, or copper), a metal alloy, a polysilicon or other suitable material. In some embodiments, the conductive material may be filled in by chemical vapor deposition, physical vapor deposition (eg, evaporation or sputtering), atomic layer deposition (ALD), electroplating, or a combination thereof, or other suitable method. The third trench 602 is formed to form a first contact structure 702. In addition, after depositing the conductive material, a chemical mechanical polishing process or an etch back process may be performed as needed to remove excess conductive material.

In some embodiments, the first contact structure 702 is electrically connected to a voltage source, and the voltage source can provide or adjust the voltage of the bottom plate 102 from the first side of the bottom plate 102 via the first contact structure 702 without having to be the second from the bottom plate 102. The side provides or adjusts the voltage of the bottom plate 102, eliminating the additional process required to increase the contact resistance of the bottom plate, reducing the cost, and improving the convenience of the circuit layout.

In some embodiments, an adhesion layer may be formed on the sidewall of the third trench 602 (not shown) as needed before filling the conductive material in the third trench 602. For example, the adhesion layer can be TiN, Ti, Ta, TaN, or other suitable electrically conductive material. The adhesion layer may be formed by physical vapor deposition, atomic layer deposition, electroplating, or a combination thereof, or other suitable method. The adhesion layer can be used to improve the adhesion between the conductive material and the sidewall of the trench, and to reduce the adverse effects on the semiconductor device due to the diffusion behavior of the conductive material.

Next, as shown in FIG. 8, an inter-layer dielectric (ILD) layer 802 is formed over the first dielectric layer 502 as appropriate. For example, the interlayer dielectric layer 802 can comprise a single or multiple dielectric materials. Single or multi-layer structure, such as cerium oxide, cerium nitride, cerium oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass; BPSG), low dielectric constant materials, or other suitable dielectric materials. For example, the interlayer dielectric layer 802 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable process. After depositing the interlayer dielectric layer, a chemical mechanical polishing process or an etch back process may be performed as needed to remove excess dielectric material.

Next, a second contact structure 804 is formed in the interlayer dielectric layer 802. For example, the second contact structure 804 can be formed from a metallic material (eg, tungsten, aluminum, or copper), a metal alloy, a polysilicon, or other suitable material. In some embodiments, the second contact structure can be formed by chemical vapor deposition, physical vapor deposition (eg, evaporation or sputtering), atomic layer deposition (ALD), electroplating, or a combination thereof, or other suitable method. 804. In addition, after depositing the conductive material, a chemical mechanical polishing process or an etch back process may be performed as needed to remove excess conductive material.

In some embodiments, the first contact structure 702 is electrically connected to a voltage source via the second contact structure 804, and the voltage source may be provided from the first side of the bottom plate 102 via the second contact structure 804 and the first contact structure 702 or The voltage of the backplane 102 is adjusted without having to provide or adjust the voltage of the backplane 102 from the second side of the backplane 102.

In summary, the method for forming a semiconductor device according to the present disclosure is to form a dielectric layer having a poor step coverage on a trench having a different width, by using a dielectric layer. The difference in stacking conditions on trenches of different widths can define the position of the contact structure and the isolation structure without separately forming an etching mask such as a patterned photoresist, thereby reducing process steps and material cost. Avoid the problem that the dielectric layer is too thick and the photoresist cannot be completely developed and remains in the trench.

The foregoing summary of the invention is inferred by the claims It will be understood by those of ordinary skill in the art, and other processes and structures may be readily designed or modified on the basis of the present disclosure, and thus achieve the same objectives and/or achieve the same embodiments as those described herein. The advantages. Those of ordinary skill in the art should also understand that such equivalent structures are not departing from the spirit and scope of the invention. Various changes, permutations, or alterations may be made in the present disclosure without departing from the spirit and scope of the invention.

In addition, the present invention has been described above in terms of several preferred embodiments, which are not intended to limit the invention, and not all of the advantages thereof. The scope of the present invention is defined by the scope of the appended claims, unless otherwise claimed.

Claims (15)

A semiconductor device comprising: an insulating layer upper semiconductor substrate, comprising a bottom plate, a buried oxide layer disposed on the bottom plate, and a semiconductor layer disposed on the buried oxide layer; a first dielectric layer disposed on a first contact structure extending from an upper surface of the first dielectric layer into the semiconductor layer and passing through the buried oxide layer and connecting the substrate; a first trench extending into the semiconductor a layer, wherein a width of the first trench is smaller than a width of the first contact structure, wherein the first dielectric layer seals the first trench to form a vacuum gap near the top of the first trench; and A hard mask layer is disposed between the semiconductor layer and the first dielectric layer, and the first trench and the first contact structure extend through the hard mask layer. The semiconductor device of claim 1, wherein the width of the first trench is from 1:1.2 to 1:5 than the width of the first contact structure. The semiconductor device according to claim 1, wherein the first dielectric layer comprises a silane-based oxide or a tetraethoxy decane-based oxide (Tetraethyl orthosilicate, TEOS- Based oxide), or a combination of the above. The semiconductor device of claim 1, further comprising: an interlayer dielectric layer disposed on the first dielectric layer; and a second contact structure formed in the interlayer dielectric layer The first contact structure is electrically connected. The semiconductor device of claim 4, wherein the second contact structure is electrically connected to a voltage source to provide the substrate voltage. The semiconductor device according to claim 1, wherein the first trench has a depth of 2 μm to 80 μm. The semiconductor device of claim 1, wherein the first contact structure has a ring structure in a top view. A method for forming a semiconductor device, comprising: providing an insulating layer upper semiconductor substrate, comprising a bottom plate, a buried oxide layer disposed on the bottom plate, and a semiconductor layer disposed on the buried oxide layer; forming a first trench a trench and a second trench, the first trench and the second trench extending into the semiconductor layer and exposing an upper surface of the buried oxide layer, wherein the width of the first trench is smaller than the second trench a width, wherein the forming the first trench and the second trench comprises: forming a hard mask layer over the semiconductor layer; patterning the hard mask layer; and patterning the hard mask layer Etching the semiconductor layer as an etch mask; forming a first dielectric layer on the semiconductor layer, wherein the first dielectric layer does not fill the first trench and is located near the top of the first trench a trench is sealed to form a vacuum gap; an etching step is performed to remove a portion of the first dielectric layer and remove a portion of the buried oxide layer under the second trench to expose the substrate, wherein the etching The first dielectric layer after the step The first sealing groove; and a conductive material is filled in the second trench to form a first contact structure to which the first contact structure connected to the base plate. The method of forming a semiconductor device according to claim 8, wherein the step of forming the first dielectric layer and the etching step does not include forming a photoresist on the first dielectric layer. The method for forming a semiconductor device according to claim 8, further comprising: forming an interlayer dielectric layer over the first dielectric layer; and forming a second conductive contact structure on the interlayer dielectric layer And electrically connecting the first contact structure. The method of forming a semiconductor device according to claim 8, wherein the step of forming the first dielectric layer comprises depositing a silane-based oxide by plasma chemical vapor deposition (PECVD). ), a tetraethoxy oxime-based oxide (TEOS-based oxide), or a combination thereof as described above. The method of forming a semiconductor device according to claim 8, wherein the first trench and the second trench have a depth of 2 μm to 80 μm. The method of forming a semiconductor device according to claim 8, wherein the top of the vacuum gap is tapered toward the upper surface of the first dielectric layer to have a taper shape. The method of forming a semiconductor device according to claim 8, wherein the step of forming the first dielectric layer does not fill the second trench and the second trench is not sealed near the top of the second trench. groove. The method of forming a semiconductor device according to claim 8, wherein after the etching step, a portion of the first dielectric layer remains in a sidewall of the second trench.