TWI531164B - Output buffer - Google Patents

Description

Output buffer

This invention relates to an output buffer, and more particularly to a rail-to-rail output buffer.

With the advancement of optoelectronic and semiconductor components, flat panel displays such as liquid crystal displays (LCDs) have flourished in recent years. Liquid crystal displays have gradually become the mainstream of the market due to their many advantages, such as low power consumption, no radiation, and high space utilization. The source driver is a relatively important component in the liquid crystal display, which can convert the digital data signal of the display image into an analog signal, and output such a specific signal to each pixel of the display panel.

In general, the source driver includes a plurality of driving channels for transmitting analog signals to pixels on each data line, and it also includes a plurality of output buffers to enhance the signal transmission intensity to charge and discharge the display panel. Therefore, the output buffer greatly affects the entire source driver, and as the function of portable electronic products increases, the output buffer is bound to move toward low power consumption and small area specifications.

The present invention provides an output buffer that can quickly adjust an output voltage in response to a change in an input voltage when the input voltage and the output voltage are different.

The invention provides an output buffer comprising a first P-type transistor, a first N-type transistor, a first comparison unit and a second comparison unit. The first P-type transistor has a first source, a first gate and a first drain, the first source receives the system voltage, and the first drain outputs an output voltage. The first N-type transistor has a second drain, a second gate and a second source, the second drain is coupled to the first drain, and the second source receives the ground voltage. The first comparing unit receives an input voltage and an output voltage, compares the input voltage and the output voltage, and outputs a high voltage or a low voltage to the first gate according to the comparison result, and correspondingly adjusts the first tail current flowing into the first comparing unit. The second comparing unit receives the input voltage and the output voltage, compares the input voltage and the output voltage, and outputs a high voltage or a low voltage to the second gate according to the comparison result, and correspondingly adjusts the second tail current flowing out of the second comparing unit.

In an embodiment of the invention, when the input voltage is greater than the output voltage, the first comparison unit outputs a low voltage to the first gate, and the second comparison unit outputs a low voltage to the second gate. When the input voltage is less than the output voltage, the first comparison unit outputs a high voltage to the first gate, and the second comparison unit outputs a high voltage to the second gate.

In an embodiment of the invention, when the input voltage is greater than the output voltage, the first comparison unit is in a closed state to reduce a first tail current received by the first comparison unit from the system voltage, and the second comparison unit is in an on state to increase the second The comparison unit outputs a second tail current to the ground voltage. When the input voltage is less than the output voltage, the first comparison unit is in an on state to increase a first tail current received by the first comparison unit from the system voltage, and the second comparison unit is in an off state to reduce a second comparison unit output to a second ground voltage Tail current.

In an embodiment of the invention, the first comparison unit includes a second P-type transistor, a P-type differential circuit, and a first current source. The second P-type transistor has a third source, a third gate, and a third drain, and the third source receives the system voltage to receive the first tail current. The P-type differential circuit has a first input end, a second input end, a first output end, a first power supply end and a second power supply end, the first input end receives the output voltage, the second input end receives the input voltage, and the first output The end is coupled to the first gate, the first power terminal is coupled to the third drain, and the second power terminal is coupled to the third gate. The first current source is coupled between the second power terminal and the ground voltage.

In an embodiment of the invention, the P-type differential circuit includes a third P-type transistor and a fourth P-type transistor. The third P-type transistor has a fourth source, a fourth gate and a fourth drain, the fourth source is coupled to the first power terminal, the fourth drain is coupled to the second power terminal, and the fourth gate is coupled The first input. The fourth P-type transistor has a fifth source, a fifth gate and a fifth drain, the fifth source is coupled to the first power terminal, the fifth drain is coupled to the first output terminal, and the fifth gate is coupled The second input.

In an embodiment of the invention, the second comparison unit includes a second N-type transistor and an N-type differential circuit and a second current source. The second N-type transistor has a sixth drain, a sixth gate, and a sixth source, and the sixth source receives the ground voltage to output a second tail current. The N-type differential circuit has a third input end, a fourth input end, a second output end, a third power supply end and a fourth power supply end, the third input end receives the output voltage, the fourth input end receives the input voltage, and the second output The terminal is coupled to the second gate, the third power terminal is coupled to the sixth gate, and the fourth power terminal is coupled to the sixth drain. The second current source is coupled between the system voltage and the third power terminal.

In an embodiment of the invention, the N-type differential circuit includes a third N-type transistor and a fourth N-type transistor. The third N-type transistor has a seventh drain, a seventh gate and a seventh source, the seventh drain is coupled to the third power terminal, the seventh source is coupled to the fourth power terminal, and the seventh gate is coupled The third input. The fourth N-type transistor has an eighth drain, an eighth gate and an eighth source, the eighth drain is coupled to the second output end, the eighth source is coupled to the fourth power terminal, and the eighth gate is coupled The fourth input.

In an embodiment of the invention, the output buffer further includes a biasing unit coupled to the first gate and the second gate for providing a bias voltage.

In an embodiment of the invention, the biasing unit includes a fifth P-type transistor and a fifth N-type transistor. The fifth P-type transistor has a ninth source, a ninth gate and a ninth drain, the ninth source is coupled to the first gate, the ninth drain is coupled to the second gate, and the ninth gate is received A reference voltage. The fifth N-type transistor has a tenth drain, a tenth gate and a tenth source, the tenth drain is coupled to the first gate, the tenth source is coupled to the second gate, and the tenth gate receives the first Two reference voltages.

In an embodiment of the invention, the high voltage is a system voltage.

In an embodiment of the invention, the low voltage is a ground voltage.

Based on the above, in the output buffer of the embodiment of the present invention, the first comparison unit and the second comparison unit compare the input voltage and the output voltage, and accordingly control the P-type transistor and the N-type transistor to be turned on or off, and synchronously adjust. The first tail current and the second tail current of the first comparison unit and the second comparison unit, thereby achieving the ability to quickly respond to the voltage difference of the input voltage and the output voltage.

The above described features and advantages of the present invention will be more apparent from the following description.

The embodiments described below will be described in detail with reference to the drawings of the embodiments. The same or similar reference numerals are used in the drawings to describe the same or similar parts.

1 is a system diagram of an output buffer in accordance with an embodiment of the present invention. Referring to FIG. 1 , in the embodiment, the output buffer 100 includes a first P-type transistor PM1 , a first N-type transistor NM1 , a first comparison unit 110 , a second comparison unit 120 , and a bias unit 130 . The first P-type transistor PM1 and the first N-type transistor NM1 can be regarded as an output stage of the output buffer 100. The first P-type transistor PM1 has a first source S1, a first gate G1, and a first drain D1. The first source S1 receives the system voltage VDDA, and the first drain D1 outputs an output voltage Vout. The first N-type transistor NM1 has a second drain D2, a second gate G2, and a second source S2. The second drain D2 is coupled to the first drain D1, and the second source S2 receives the ground voltage GND.

The biasing unit 130 is coupled to the first gate G1 and the second gate G2 for providing a bias voltage VGG to the first gate G1 and the second gate G2. The first comparison unit 110 receives the input voltage Vin and the output voltage Vout according to the comparison input voltage Vin and the output voltage Vout, and outputs a high voltage VH or a low voltage VL to the first gate G1 according to the comparison result, and correspondingly adjusts the self-system voltage. VDDA flows into the first tail current i _{t1 of the} first comparison unit 110. The second comparison unit 120 receives the input voltage Vin and the output voltage Vout according to the comparison input voltage Vin and the output voltage Vout, and outputs a high voltage VH or a low voltage VL to the second gate G2 according to the comparison result, and adjusts the second comparison unit 120. The second tail current i _t2 flowing out to the ground voltage GND.

When the input voltage Vin is greater than the output voltage Vout, the first comparison unit 110 outputs the low voltage VL to the first gate G1 to turn on the first P-type transistor PM1, by the system voltage VDDA to the output terminal (ie, corresponding to the output voltage Vout) The terminal is charged, and the second comparison unit outputs a low voltage VL to the second gate to turn off the first N-type transistor NM1, thereby preventing the output from being discharged through the first N-type transistor NM1. At this time, the first comparison unit 110 is in a off state to reduce the first tail current i _t1 received by the first comparison unit 110 from the system voltage VDDA, and the second comparison unit is in an on state to increase the output of the second comparison unit 120 to the ground. The second tail current i _{t2 of the} voltage GND.

When the input voltage Vin is smaller than the output voltage Vout, the first comparison unit 110 outputs the high voltage VH to the first gate G1 to turn off the first P-type transistor PM1, so as to prevent the output terminal from being charged through the first P-type transistor PM1. And the second comparison unit 120 outputs the high voltage VH to the second gate G2 to turn on the first N-type transistor NM1, and discharges the output terminal by the ground voltage GND. At this time, the first comparison unit 110 is in an on state to increase the first tail current i _t1 received by the first comparison unit 110 from the system voltage VDDA, and the second comparison unit is in the off state to lower the output of the second comparison unit 120 to the ground. The second tail current i _{t2 of the} voltage GND.

According to the above, when the voltage range of the input voltage Vin is the system voltage VDDA to the ground voltage GND, the output voltage Vout voltage range is also the system voltage VDDA to the ground voltage GND. Therefore, in the embodiment of the present invention, the output buffer 100 may be a rail-to-rail output buffer. In addition, the first comparison unit 110 adjusts the first tail current i _t1 flowing from the system voltage VDDA to the first comparison unit 110 according to the comparison result of the input voltage Vin and the output voltage Vout, and the second comparison unit 120 compares the input voltage according to the comparison. The comparison result of Vin and the output voltage Vout adjusts the second tail current i _{t2 of the} second comparison unit 120 flowing to the ground voltage GND, so that the output buffer 100 can accelerate the reaction of the voltage difference between the input voltage Vin and the output voltage Vout, that is, The transient time of the output voltage Vout can be reduced.

2 is a circuit diagram of an output buffer in accordance with an embodiment of the present invention. Referring to FIG. 1 and FIG. 2, in the present embodiment, the first comparison unit 110' in the output buffer 100' includes a second P-type transistor PM2, a P-type differential circuit 111, and a first current source CS1. The second P-type transistor PM2 has a third source S3, a third gate G3, and a third drain D3. The third source S3 receives the system voltage VDDA to receive the first tail current i _t1 . The P-type differential circuit 111 has a first input terminal IP1, a second input terminal IP2, a first output terminal OP1, a first power terminal PT1, and a second power terminal PT2. The first input terminal IP1 receives the output voltage Vout, the second input terminal IP2 receives the input voltage Vin, the first output terminal OP1 is coupled to the first gate G1, the first power terminal PT1 is coupled to the third drain D3, and the second power terminal The PT2 is coupled to the third gate G3. The first current source CS1 is coupled between the second power terminal PT2 and the ground voltage GND.

Further, the P-type differential circuit 111 includes a third P-type transistor PM3 and a fourth P-type transistor PM4. The third P-type transistor PM3 has a fourth source S4, a fourth gate G4, and a fourth drain D4. The fourth source S4 is coupled to the first power terminal PT1, the fourth gate D4 is coupled to the second power terminal PT2, and the fourth gate G4 is coupled to the first input terminal IP1. The fourth P-type transistor PM4 has a fifth source S5, a fifth gate G5, and a fifth drain D5. The fifth source S5 is coupled to the first power terminal PT1, the fifth gate D5 is coupled to the first output terminal OP1, and the fifth gate G5 is coupled to the second input terminal IP2.

In the present example, the second comparison unit 120' in the output buffer 100' includes a second N-type transistor NM2, an N-type differential circuit 121, and a second current source CS2. The second N-type transistor NM2 has a sixth drain D6, a sixth gate G6, and a sixth source S6. The sixth source S6 receives the ground voltage GND to output a second tail current i _t2 . The N-type differential circuit 121 has a third input terminal IP3, a fourth input terminal IP4, a second output terminal OP2, a third power terminal PT3, and a fourth power terminal PT4. The third input terminal IP3 receives the output voltage Vout, the fourth input terminal IP4 receives the input voltage Vin, the second output terminal OP2 is coupled to the second gate G2, and the third power terminal PT3 is coupled to the sixth gate G6, and the fourth power terminal The PT4 is coupled to the sixth drain D6. The second current source CS2 is coupled between the system voltage VDDA and the third power terminal PT3.

Further, the N-type differential circuit 121 includes a third N-type transistor NM3 and a fourth N-type transistor NM4. The third N-type transistor NM3 has a seventh drain D7, a seventh gate G7, and a seventh source S7. The seventh drain D7 is coupled to the third power terminal PT3, the seventh source S7 is coupled to the fourth power terminal PT4, and the seventh gate G7 is coupled to the third input terminal IP3. The fourth N-type transistor NM4 has an eighth drain D8, an eighth gate G8, and an eighth source S8. The eighth drain D8 is coupled to the second output terminal OP2, the eighth source S8 is coupled to the fourth power terminal PT4, and the eighth gate G8 is coupled to the fourth input terminal IP4.

In the present example, the bias unit 130' includes a fifth P-type transistor PM5 and a fifth N-type transistor NM5. The fifth P-type transistor PM5 has a ninth source S9, a ninth gate G9, and a ninth drain D9. The ninth source S9 is coupled to the first gate G1, the ninth gate D9 is coupled to the second gate G2, and the ninth gate G9 receives the first reference voltage VR1, wherein the fifth P-type transistor PM5 is controlled by the first A reference voltage VR1 is turned on or off. The fifth N-type transistor NM5 has a tenth drain D10, a tenth gate G10, and a tenth source S10. The tenth drain D10 is coupled to the first gate G1, the ninth source S9 is coupled to the second gate G2, and the tenth gate G10 receives the second reference voltage VR2, wherein the fifth N-type transistor NM5 is controlled by the first The second reference voltage VR2 is turned on or off.

FIG. 3 is a schematic diagram of driving waveforms when the input voltage of FIG. 2 rises according to an embodiment of the invention. Referring to FIG. 2 and FIG. 3, in the embodiment, when the input voltage Vin rises (as shown in the rising edge of the input voltage Vin as shown in FIG. 3), the input voltage Vin will be greater than the output voltage Vout, representing the output buffer 100'. The output (not shown) is charged to raise the output voltage Vout. At this time, when the input voltage Vin rises, the channel of the fourth P-type transistor PM4 becomes smaller, so the current flowing to the third P-type transistor PM3 increases, and the voltage V _{PT2 of the} second power supply terminal PT2 rises. When the voltage V _{PT2 of the} second power terminal PT2 rises, the channel of the second P-type transistor PM2 becomes smaller, so that the first tail current i _t1 becomes smaller, and the voltage V _{PT1 of the} first power terminal PT1 decreases. . When the voltage V _{PT1 of the} first power terminal PT1 falls, the closing speed of the channel of the fourth P-type transistor PM4 is increased. Thereby, the first comparison unit 110' is in a closed state, so that the charging ability of the first comparison unit 110' to the first gate G1 and the second gate G2 is greatly weakened or even disappeared (ie, no charging capability).

When the input voltage Vin rises, the channel of the fourth N-type transistor NM4 becomes larger, and the current of the third N-type transistor NM3 flowing to the second N-type transistor NM2 decreases, and thus the voltage V of the third power terminal PT3 _PT3 will rise. When the voltage V _{PT3 of the} third power terminal PT3 rises, the channel of the second N-type transistor NM2 becomes larger, so that the second tail current i _t2 becomes larger, and the voltage V _{PT4 of the} fourth power terminal PT4 decreases. . When the voltage V _{PT4 of the} fourth power terminal PT4 falls, the opening speed of the channel of the fourth N-type transistor NM4 is accelerated. Thereby, the second comparison unit 120' is in an on state, so that the discharge capability of the second comparison unit 120' to the first gate G1 and the second gate G2 is greatly increased.

According to the above, when the input voltage Vin rises, the first comparison unit 110' is in the off state to make its charging ability weak or disappear, and the second comparison unit 120' is in the on state to increase its discharge capacity. At this time, the voltages V _G1 and V _{G2 of the} first gate G1 and the second gate G2 rapidly drop to be close to or equal to the ground voltage GND, that is, the output of the first comparison unit 110' and the second comparison unit 120' is low. The voltage VL is close to or equal to the ground voltage GND, so that the channel of the first P-type transistor PM1 is quickly turned on to increase its charging capability, and the channel of the first N-type transistor NM1 is quickly turned off to lower its discharge capability. When the channel of the first P-type transistor PM1 is quickly turned on and the channel of the first N-type transistor NM1 is quickly turned off, the charging speed of the output terminal is accelerated, that is, the rising speed of the output voltage Vout is increased, so The transient time at which the output voltage Vout rises is drastically reduced.

4 is a schematic diagram of driving waveforms when the input voltage of FIG. 2 is decreased, in accordance with an embodiment of the present invention. Referring to FIG. 2 and FIG. 4, in the embodiment, when the input voltage Vin falls (as shown in FIG. 4, the falling edge of the input voltage Vin), the input voltage Vin will be smaller than the output voltage Vout, representing the output buffer 100'. The output (not shown) discharges to reduce the output voltage Vout. At this time, when the input voltage Vin decreases, the channel of the fourth P-type transistor PM4 becomes large, so the current flowing to the third P-type transistor PM3 decreases, and the voltage V _{PT2 of the} second power supply terminal PT2 decreases. When the voltage V _{PT2 of the} second power terminal PT2 falls, the channel of the second P-type transistor PM2 becomes larger, so that the first tail current i _t1 becomes larger, and the voltage V _{PT1 of the} first power terminal PT1 rises. . When the voltage V _{PT1 of the} first power terminal PT1 rises, the opening speed of the channel of the fourth P-type transistor PM4 is increased. Thereby, the first comparison unit 110' is in an on state, so that the charging ability of the first comparison unit 110' to the first gate G1 and the second gate G2 is greatly increased.

When the input voltage Vin decreases, the channel of the fourth N-type transistor NM4 becomes smaller, and the current of the third N-type transistor NM3 flowing to the second N-type transistor NM2 increases, and thus the voltage V of the third power terminal PT3 _PT3 will drop. When the voltage V _{PT3 of the} third power terminal PT3 falls, the channel of the second N-type transistor NM2 becomes smaller, so that the second tail current i _t2 becomes smaller, and the voltage V _{PT4 of the} fourth power terminal PT4 rises. . When the voltage V _{PT4 of the} fourth power supply terminal PT4 rises, the closing speed of the channel of the fourth N-type transistor NM4 is increased. Thereby, the second comparison unit 120' is in a closed state, so that the discharge capability of the second comparison unit 120' to the first gate G1 and the second gate G2 is greatly reduced or even disappeared (ie, no discharge capability).

According to the above, when the input voltage Vin falls, the first comparison unit 110' is in an on state to increase its charging ability, and the second comparison unit 120' is in an on state to make its discharge capability weak or disappear. At this time, the voltages V _G1 and V _{G2 of the} first gate G1 and the second gate G2 rapidly rise to be close to or equal to the system voltage VDDA, that is, the output of the first comparison unit 110' and the second comparison unit 120'. The voltage VH will be close to or equal to the system voltage VDDA, so that the channel of the first P-type transistor PM1 will be quickly turned off to lower its charging capability, and the channel of the first N-type transistor NM1 will be quickly turned on to increase its discharge capability. When the channel of the first P-type transistor PM1 is quickly turned off and the channel of the first N-type transistor NM1 is quickly turned on, the discharge speed of the output terminal is accelerated, that is, the falling speed of the output voltage Vout is increased, so The transient time at which the output voltage Vout drops is drastically reduced.

In accordance with the above, in the present embodiment, the output buffer 100' can be implemented by a simple circuit, so that the output buffer 100' can operate at an extremely low quiescent current. Moreover, the output buffer 100' of the present embodiment has a smaller number of transistors than the conventional rail-to-rail output buffer, so that the wafer area of the source driver can be greatly reduced.

In summary, in the output buffer of the embodiment of the present invention, the first comparing unit and the second comparing unit control the P-type transistor and the N-type transistor to be turned on or off according to the comparison result of the input voltage and the output voltage, and are synchronized. The first tail current and the second tail current of the first comparison unit and the second comparison unit are adjusted, thereby achieving the ability to quickly respond to the differential pressure of the input voltage and the output voltage. Moreover, the output buffer can be implemented through a simple circuit, so the output buffer can operate at very low quiescent current and can greatly reduce the wafer area of the source driver.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 100’. . . Output buffer

110, 110’. . . First comparison unit

111. . . P type differential circuit

120, 120’. . . Second comparison unit

121. . . N type differential circuit

130, 130’. . . Bias unit

CS1, CS2. . . Battery

D1~D10. . . Bungee

G1~G10‧‧‧ gate

GND‧‧‧ Grounding voltage

IP1~IP4‧‧‧ input

i _t1 , i _t2 ‧‧‧ tail current

NM1~NM5‧‧‧N type transistor

OP1, OP2‧‧‧ output

PM1~PM5‧‧‧P type transistor

PT1~PT4‧‧‧ power terminal

S1~S10‧‧‧ source

VDDA‧‧‧ system voltage

VGG‧‧‧ bias

VH‧‧‧High voltage

Vin‧‧‧Input voltage

VL‧‧‧low voltage

Vout‧‧‧ output voltage

V _PT1 ~V _PT4 , V _G1 , V _G2 ‧‧‧ voltage

VR1, VR2‧‧‧ reference voltage

1 is a system diagram of an output buffer in accordance with an embodiment of the present invention.

2 is a circuit diagram of an output buffer in accordance with an embodiment of the present invention.

FIG. 3 is a schematic diagram of driving waveforms when the input voltage of FIG. 2 rises according to an embodiment of the invention.

4 is a schematic diagram of driving waveforms when the input voltage of FIG. 2 is decreased, in accordance with an embodiment of the present invention.

100. . . Output buffer

110. . . First comparison unit

120. . . Second comparison unit

130. . . Bias unit

D1, D2. . . Bungee

G1, G2. . . Gate

GND. . . Ground voltage

i _t1 , i _t2 . . . Tail current

NM1. . . N type transistor

PM1. . . P-type transistor

S1, S2. . . Source

VDDA. . . System voltage

VH. . . high voltage

Vin. . . Input voltage

VL. . . low voltage

Vout. . . The output voltage

Claims (10)

An output buffer includes: a first P-type transistor having a first source, a first gate, and a first drain, wherein the first source receives a system voltage, the first drain Outputting an output voltage; a first N-type transistor having a second drain, a second gate, and a second source, wherein the second drain is coupled to the first drain, the second source Receiving a ground voltage; the first comparing unit is configured to receive an input voltage and the output voltage, compare the input voltage and the output voltage, and output a high voltage or a low voltage to the first gate according to the comparison result, and Correspondingly adjusting a first tail current flowing into the first comparing unit, wherein the first comparing unit comprises: a second P-type transistor having a third source, a third gate, and a third drain The third source receives the system voltage to receive the first tail current; a P-type differential circuit has a first input end, a second input end, a first output end, and a first power supply end And a second power terminal, wherein the first input receives the output voltage, The second input terminal is coupled to the first gate, the first power terminal is coupled to the third drain, and the second power terminal is coupled to the third gate; a first current source coupled between the second power terminal and the ground voltage; and a second comparing unit configured to receive the input voltage and the output voltage, compare the input voltage and the output voltage, according to the comparison result Output the high voltage Pressing or lowering the voltage to the second gate, and correspondingly adjusting a second tail current flowing from the second comparison unit. The output buffer of claim 1, wherein the first comparison unit outputs the low voltage to the first gate when the input voltage is greater than the output voltage, and the second comparison unit outputs the low voltage To the second gate; when the input voltage is less than the output voltage, the first comparison unit outputs the high voltage to the first gate, and the second comparison unit outputs the high voltage to the second gate. The output buffer of claim 2, wherein when the input voltage is greater than the output voltage, the first comparing unit is in a closed state to reduce the first tail received by the first comparing unit from the system voltage Current, the second comparison unit is in an on state to increase the second tail current output by the second comparison unit to the ground voltage; when the input voltage is less than the output voltage, the first comparison unit is in the on state to increase The first comparison unit receives the first tail current from the system voltage, and the second comparison unit is in the off state to reduce the second tail current output by the second comparison unit to the ground voltage. The output buffer of claim 1, wherein the P-type differential circuit comprises: a third P-type transistor having a fourth source, a fourth gate, and a fourth drain. The fourth source is coupled to the first power terminal, the fourth drain is coupled to the second power terminal, the fourth gate is coupled to the first input terminal, and a fourth P-type transistor has a fifth source, a fifth gate, and a fifth drain, wherein the fifth source is coupled to the first power terminal, the fifth drain is coupled to the first output terminal, and the fifth gate is coupled to the second input terminal. The output buffer of claim 1, wherein the second comparison unit comprises: a second N-type transistor having a sixth drain, a sixth gate, and a sixth source, wherein The sixth source receives the ground voltage to output the second tail current; an N-type differential circuit has a third input terminal, a fourth input terminal, a second output terminal, a third power terminal, and a a fourth power terminal, wherein the third input terminal receives the output voltage, the fourth input terminal receives the input voltage, the second output terminal is coupled to the second gate, and the third power terminal is coupled to the sixth gate The fourth power source is coupled to the sixth drain; a second current source is coupled between the system voltage and the third power terminal. The output buffer of claim 5, wherein the N-type differential circuit comprises: a third N-type transistor having a seventh drain, a seventh gate, and a seventh source, The seventh source is coupled to the third power terminal, the seventh source is coupled to the fourth power terminal, the seventh gate is coupled to the third input terminal, and a fourth N-type transistor has An eighth drain, an eighth gate, and an eighth source, wherein the eighth drain is coupled to the second output, the eighth source is coupled to the fourth power terminal, the eighth gate The fourth input end is coupled. The output buffer as described in claim 1 of the patent scope further includes: A biasing unit coupled to the first gate and the second gate for providing a bias voltage. The output buffer of claim 1, wherein the biasing unit comprises: a fifth P-type transistor having a ninth source, a ninth gate, and a ninth drain, wherein the The ninth source is coupled to the first gate, the ninth drain is coupled to the second gate, the ninth gate receives a first reference voltage, and a fifth N-type transistor has a tenth a drain gate, a tenth gate, and a tenth source, wherein the tenth drain is coupled to the first gate, the tenth source is coupled to the second gate, and the tenth gate receives a first Two reference voltages. The output buffer of claim 1, wherein the high voltage is the system voltage. The output buffer of claim 1, wherein the low voltage is the ground voltage.