CN110047451A - Source electrode driver, array substrate and liquid crystal display panel - Google Patents
Source electrode driver, array substrate and liquid crystal display panel Download PDFInfo
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- CN110047451A CN110047451A CN201910278240.0A CN201910278240A CN110047451A CN 110047451 A CN110047451 A CN 110047451A CN 201910278240 A CN201910278240 A CN 201910278240A CN 110047451 A CN110047451 A CN 110047451A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 title claims abstract description 28
- 239000000872 buffer Substances 0.000 claims description 35
- 239000010409 thin film Substances 0.000 claims description 16
- 230000003321 amplification Effects 0.000 claims description 13
- 230000002708 enhancing effect Effects 0.000 claims description 13
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 13
- 238000002834 transmittance Methods 0.000 abstract description 12
- 230000004907 flux Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 13
- 230000035515 penetration Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 230000001965 increasing effect Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 230000003068 static effect Effects 0.000 description 6
- 239000010408 film Substances 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 206010047571 Visual impairment Diseases 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention provides a kind of source electrode driver, array substrate and liquid crystal display panel, the driving channel of its source electrode driver includes operational amplifier and driving current amplifying circuit, for amplifying the driving current of the operational amplifier so that the driving current is greater than the bias current of the operational amplifier, to enhance the slew rate of the operational amplifier；On this basis, improve the slew rate of pixel voltage, accelerate the speed of liquid crystal rotation, shorten the display panel time bright by blackout, increase the luminous flux that display panel is passed through in the unit time, and then the light transmittance of display panel is enhanced, improve the lower technical problem of light transmittance existing for existing display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a source driver, an array substrate and a liquid crystal display panel.
Background
The power consumption of the display panel is inversely related to the light transmittance, and the improvement of the light transmittance of the panel is helpful for reducing the power consumption, so that the liquid crystal panel with high light transmittance is a development trend.
In the prior art, the improvement of the light transmittance of the panel is realized by improving the process surface, for example, changing the shape of the mask of the alignment terminal in the panel, increasing the slit angle of the electrode (such as ITO slit angle), and the like. However, the improvement of the process surface is limited, and new problems may be caused, such as the increase of ITO slit angle may cause the viewing angle of the display panel to be deteriorated.
Therefore, the conventional method for improving light transmittance of the display panel introduces new defects, and it is therefore desirable to provide a new method for improving light transmittance.
Disclosure of Invention
The invention provides a source driver, an array substrate and a liquid crystal display panel, aiming at solving the technical problem of low light penetration rate of the existing display panel.
In order to solve the above problems, the technical solution provided by the present invention is as follows:
an embodiment of the present invention provides a source driver, which includes a plurality of driving channels, each of the driving channels providing a pixel voltage to a plurality of pixel driving transistors in a same column of an array panel, and each of the driving channels includes:
the buffer is used for latching the pixel data input by the input end of the driving channel;
the digital-to-analog converter is used for converting the pixel data in the digital signal format into an analog signal;
an operational amplifier for supplying a pixel voltage;
and the driving current amplifying circuit is used for amplifying the driving current of the operational amplifier so as to enable the driving current to be larger than the bias current of the operational amplifier, thereby enhancing the slew rate of the operational amplifier.
In the source driver provided by the present invention, the operational amplifier includes: the circuit comprises a bias circuit, a first-stage circuit and a second-stage circuit; wherein,
the bias circuit is used for providing a bias current;
the first-stage circuit is connected with the bias circuit and used for comparing and first-stage amplifying the two paths of input voltages when the two paths of input voltages are accessed so as to output a first-stage amplified voltage;
the second-stage circuit is connected with the first-stage circuit and used for carrying out second-stage amplification on the first-stage amplified voltage so as to output second-stage amplified voltage for the operational amplifier to provide pixel voltage;
the driving current amplifying circuit is respectively connected with the bias circuit, the first-stage circuit and the second-stage circuit and is used for adjusting the driving current of the operational amplifier according to the first-stage amplifying voltage so that the driving current is larger than the bias current, and therefore the slew rate of the operational amplifier is enhanced.
In the source driver provided by the present invention, the drive current amplification circuit includes:
the voltage output circuit is used for outputting a control voltage according to the magnitude of the first-stage amplification voltage;
and the slew rate enhancing device is connected with the voltage output circuit and used for controlling the self turn-off or turn-on according to the control voltage so as to adjust the driving current of the operational amplifier, so that the driving current of the operational amplifier is larger than the bias current, and the slew rate of the operational amplifier is enhanced.
In the source driver provided by the present invention, the voltage output circuit includes: the source electrode of the NMOS transistor is grounded, the grid electrode of the NMOS transistor is connected with the bias circuit, the drain electrode of the NMOS transistor is connected with the drain electrode of the PMOS transistor, the source electrode of the PMOS transistor is connected with power supply voltage, and the grid electrode of the PMOS transistor is connected with the first-stage amplification voltage; and the drain electrode of the PMOS transistor is used as the output end of the voltage output circuit to output a control voltage.
In the source driver provided by the invention, the slew rate enhancement device is a PMOS transistor or an NMOS transistor.
In the source driver provided by the present invention, the operational amplifier further includes:
and the frequency compensation circuit is respectively connected with the first-stage circuit and the second-stage circuit and is used for eliminating self-oscillation so as to synchronize the input and output frequencies of the operational amplifier.
In the source driver provided by the present invention, each driving channel further includes a plurality of first selection switches and a plurality of second selection switches, and the buffer includes a plurality of first buffers and a second buffer, wherein:
the input ends of the plurality of first selection switches are commonly connected to the input end of the driving channel;
each first buffer is connected between the output end of a first selection switch and the input end of a second selection switch;
the output ends of the plurality of second selection switches are commonly connected to the input end of the second buffer;
the output end of the second buffer is connected to the input end of the digital-to-analog converter.
In the source driver provided by the invention, among the pixel voltages supplied to the plurality of pixel units in the same column, the pixel voltages of the adjacent pixel units have opposite polarities.
An embodiment of the present invention also provides an array substrate, which includes: a thin film transistor array arranged in rows and columns; a gate driver for scanning gate scan lines to turn on the thin film transistors of each row; the source driver provided by the embodiment of the invention is also provided.
The embodiment of the invention also provides a liquid crystal display panel which is characterized by comprising an array substrate and a color film substrate which are arranged in a box-to-box mode, and liquid crystal arranged between the array substrate and the color film substrate, wherein the array substrate comprises the source driver provided by the embodiment of the invention.
The invention has the beneficial effects that: the invention provides a source electrode driver, an array substrate and a liquid crystal display panel.A driving channel of the source electrode driver comprises an operational amplifier and a driving current amplifying circuit, and the driving current amplifying circuit is used for amplifying the driving current of the operational amplifier so as to enable the driving current to be larger than the bias current of the operational amplifier, thereby enhancing the slew rate of the operational amplifier; on the basis, the slew rate of the pixel voltage is improved, the rotation speed of the liquid crystal is accelerated, the time of the display panel changing from dark to bright is shortened, the luminous flux passing through the display panel in unit time is increased, the light penetration rate of the display panel is further enhanced, and the technical problem of low light penetration rate of the existing display panel is solved; meanwhile, the method does not need to change the processing surface of the display panel and can be compatible with the existing display panel.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a first circuit diagram of a source driver according to an embodiment of the invention;
fig. 3 is a second circuit diagram of a source driver according to an embodiment of the invention;
FIG. 4 is a third circuit diagram of a source driver according to an embodiment of the invention;
FIG. 5 is a fourth circuit diagram of a source driver according to an embodiment of the invention;
fig. 6 is a fifth circuit diagram of a source driver according to an embodiment of the invention;
FIG. 7a is a timing diagram illustrating pixel data processing according to an embodiment of the present invention;
FIG. 7b is a waveform diagram of a driving signal provided by an embodiment of the present invention;
FIG. 7c is a schematic diagram of a pixel output according to an embodiment of the present invention;
fig. 8 is a sixth circuit diagram of a source driver according to an embodiment of the invention.
Detailed Description
While the embodiments and/or examples of the present invention will be described in detail and fully with reference to the specific embodiments thereof, it should be understood that the embodiments and/or examples described below are only a part of the embodiments and/or examples of the present invention and are not intended to limit the scope of the invention. All other embodiments and/or examples, which can be obtained by a person skilled in the art without making any inventive step, based on the embodiments and/or examples of the present invention, belong to the scope of protection of the present invention.
Directional terms used in the present invention, such as [ upper ], [ lower ], [ left ], [ right ], [ front ], [ rear ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terminology is used for the purpose of describing and understanding the invention and is in no way limiting. The terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature.
Aiming at the technical problem of low light penetration rate of the existing display panel, the embodiment of the invention can solve the problem.
The light transmittance is a ratio of a transmitted light flux to an incident light flux of a light source itself, and in a liquid crystal display panel, liquid crystal is rotated at a certain frequency in order to prevent polarization of the liquid crystal. The voltage value of the pixel voltage (output) of the Source driver (Source IC) determines the angle of the liquid crystal rotation, and the Slew Rate (Slew Rate) of the Source IC output determines the speed of the liquid crystal rotation. Since the optical measurement of the luminous flux is an average value, dark and bright caused by polarity conversion are accumulated, and the faster the skew rate is, the shorter the liquid crystal rotation time is, the shorter the dark and bright time is, and the overall brightness of the display panel is improved, thereby contributing to the improvement of the panel transmittance. The present invention is based on the idea to improve a source driver of a display panel.
Liquid crystal display devices have been widely used in mobile terminals such as mobile phones and large-sized display panels such as flat panel televisions. A Liquid crystal display device includes two glass substrates and a Liquid crystal layer (Liquid crystal layer) sandwiched therebetween. A pixel electrode and a common electrode are formed on a glass substrate, and rotation of liquid crystal molecules of a liquid crystal layer is controlled by applying a driving voltage therebetween, thereby changing light transmittance.
As shown in fig. 1, the liquid crystal display device includes a gate driver 110, a source driver 120, a plurality of gate scan lines G1 to Gm, source data lines S1 to Sn, and a transistor array composed of a plurality of Thin Film Transistors (TFTs) 1101 (i.e., driving transistors in the present invention) and a pixel array 130 of a plurality of pixel cells (pixels) 1102. The gate scan lines G1 to Gm connect the gates of the tfts 1101 in the same row to the gate driver 110 for receiving the gate voltages at which the tfts are turned on. The source data lines S1 to Sn connect the source (or drain) of the tfts 1101 in the same column to the source driver 120 for providing gray scale voltages to the pixel cells after the tfts are turned on. The drain (or source) of the tft 1101 is connected to the pixel unit 1102, and the pixel unit receives the gray scale voltage and then drives the liquid crystal molecules to rotate, thereby completing the display.
Based on the above analysis of the light transmittance and the operation principle of the liquid crystal display panel, the following embodiments are provided to illustrate the idea of the present invention.
As shown in fig. 2, the source driver 120 includes a plurality of driving channels 1201, each of which provides a pixel voltage Sout to a plurality of pixel driving transistors in the same column of the array panel, and each of the driving channels 120 includes:
the buffer 21, such as LATCH1 and LATCH2 shown in fig. 2, is used for latching the pixel data inputted from the input end Sin of the driving channel;
a digital-to-analog converter 22, such as the DAC shown in fig. 2, for converting the pixel data in the digital signal format into an analog signal;
an operational amplifier 23, such as the OPA shown in fig. 2, for supplying the pixel voltage;
a drive current amplifying circuit 24, such as IPA shown in fig. 2, for amplifying the drive current of the operational amplifier to make the drive current larger than the bias current of the operational amplifier, thereby enhancing the slew rate of the operational amplifier; and
an output SWITCH 25, such as SWITCH shown in fig. 2, is used to control the output of the pixel voltage.
The pixel data on the data bus is successively input into the drive channel 1201. When the source driver works, the input end Sin receives pixel data from a processor, the pixel data is latched by buffers LATCH1 and LATCH2 and then converted into an analog signal through a digital-to-analog converter DAC, IPA amplifies the driving current of an operational amplifier so that the driving current is larger than the bias current of the operational amplifier, thereby enhancing the slew rate of the operational amplifier, and the analog signal is buffered and amplified by the operational amplifier OPA and then applied to the pixel unit on the corresponding source data line through the output end Sout of an output SWITCH.
The driving channel of the source driver provided by this embodiment includes an operational amplifier and a driving current amplifying circuit, and is used for amplifying the driving current of the operational amplifier to make the driving current greater than the bias current of the operational amplifier, so as to enhance the slew rate of the operational amplifier; on the basis, the slew rate of the pixel voltage is improved, the rotation speed of the liquid crystal is accelerated, the time of the display panel changing from dark to bright is shortened, the luminous flux passing through the display panel in unit time is increased, the light penetration rate of the display panel is further enhanced, and the technical problem of low light penetration rate of the existing display panel is solved; meanwhile, the method does not need to change the processing surface of the display panel and can be compatible with the existing display panel.
In one embodiment, as shown in fig. 3, the operational amplifier 23 includes: a bias circuit 31, a first stage circuit 32, and a second stage circuit 33; wherein,
the bias circuit 31 is used for providing bias current;
the first stage circuit 32 is connected to the bias circuit 31, and is configured to compare and first amplify the two input voltages when the two input voltages are connected to output a first amplified voltage;
the second stage circuit 33 is connected to the first stage circuit 32, and is configured to perform a second stage amplification on the first stage amplified voltage to output a second stage amplified voltage, so that the operational amplifier provides a pixel voltage;
at this time, the driving current amplifying circuit 24 is respectively connected to the bias circuit 31 and the first stage circuit 32, and is configured to adjust the driving current of the operational amplifier according to the first stage amplified voltage, so that the driving current is greater than the bias current, thereby enhancing the slew rate of the operational amplifier.
In one embodiment, as shown in fig. 3, the operational amplifier 23 further includes:
and a frequency compensation circuit 34, respectively connected to the first stage circuit 32 and the second stage circuit 33, for eliminating self-oscillation to synchronize the input and output frequencies of the operational amplifier.
In one embodiment, as shown in fig. 3, the driving current amplifying circuit 24 includes:
a voltage output circuit 241 for outputting a control voltage according to the magnitude of the first-stage amplified voltage;
and a slew rate enhancement device 242, connected to the voltage output circuit 241, for controlling its own turn-off or turn-on according to the control voltage to adjust the driving current of the operational amplifier, so that the driving current of the operational amplifier is greater than the bias current, thereby enhancing the slew rate of the operational amplifier.
The operation principle of the operational amplifier and the driving current amplifying circuit will now be described.
As for the bias circuit 31, it is used to supply bias currents to the first stage circuit 32, the second stage circuit 33, and the drive current amplifying circuit 24, respectively.
The first stage circuit 32 is configured to compare and first amplify the two input voltages when the two input voltages are connected to output a first amplified voltage. The first stage circuit 32 has two input terminals, namely a non-inverting input terminal and an inverting input terminal of the operational amplifier of the present embodiment, and two input voltages are respectively input to the non-inverting input terminal and the inverting input terminal.
The second stage circuit 33 is configured to perform a second stage amplification on the first stage amplified voltage to output a second stage amplified voltage for the operational amplifier to drive the load. The second-stage amplified voltage is the output voltage of the operational amplifier of the present embodiment, i.e., the pixel voltage.
The driving current amplifying circuit 24 is configured to adjust the driving current of the operational amplifier according to the first-stage amplified voltage when the operational amplifier drives the load, so that the driving current of the operational amplifier is greater than the bias current, thereby enhancing the slew rate of the operational amplifier.
The voltage output circuit 241 outputs a control voltage according to the magnitude of the first-stage amplified voltage when the load is driven by the operational amplifier.
In one embodiment, the voltage output circuit at least comprises an NMOS transistor and a PMOS transistor, wherein the source electrode of the NMOS transistor is grounded, the grid electrode of the NMOS transistor is connected with the biasing circuit, the drain electrode of the NMOS transistor is connected with the drain electrode of the PMOS transistor, the source electrode of the PMOS transistor is connected with the power supply voltage, and the grid electrode of the PMOS transistor is connected with the first-stage amplification voltage; the drain of the PMOS transistor is used as the output end of the voltage output circuit to output the control voltage. In the drive current amplifying circuit, the width-to-length ratio of the NMOS transistor and the PMOS transistor is preset to equalize the currents flowing through the NMOS transistor and the PMOS transistor, and when the input voltage at the non-inverting input terminal is equal to or higher than the input voltage at the inverting input terminal, the operating state of the NMOS transistor is in the saturation region and the operating state of the PMOS transistor is in the linear region; when the input voltage of the non-inverting input end is less than the input voltage of the inverting input end, the working state of the NMOS transistor is in a linear region, and the working state of the PMOS transistor is in a saturation region.
The slew rate enhancement device 242 is configured to control its own turn-off or turn-on according to the control voltage to adjust the driving current of the operational amplifier so that the driving current of the operational amplifier is greater than the bias current, thereby enhancing the slew rate of the operational amplifier.
In one embodiment, the slew rate enhancement device is a PMOS transistor or an NMOS transistor.
The frequency compensation circuit 34 is used for compensating the frequency when the load is turned on or the load works in a changing state and the stabilized voltage power supply is not adjusted in time, so that the requirement of the load is met, and the adjustment of the stabilized voltage power supply can be assisted; which essentially acts as a low pass filter to filter out the self-oscillating signal generated by the operational amplifier.
In one embodiment, the frequency compensation circuit may employ an RC network structure.
In the operational amplifier of the present embodiment, the driving current amplifying circuit 24 is added, so that when the operational amplifier 23 drives a load, the driving current of the operational amplifier can be adjusted to be larger than the bias current, thereby enhancing the slew rate of the operational amplifier; the magnitude of the driving current is not determined by the bias current of the output stage, and the driving current can be far larger than the bias current without increasing the bias current of the output stage; the slew rate enhancement device adopted by the operational amplifier of the embodiment is in a cut-off state in a static state, has no static current consumption, does not increase static power consumption, and can meet the design requirement of low power consumption in an integrated circuit.
For the above operational amplifier and driving current amplifying circuit, 2 implementation manners are now given.
In one embodiment, as shown in FIG. 4:
the bias circuit 31 includes at least: a first NMOS transistor M1; the drain of the first NMOS transistor M1 is connected to the bias reference current Ibias, the drain of the first NMOS transistor M1 is connected to the gate thereof, and the source of the first NMOS transistor M1 is grounded;
the first stage circuit 32 includes at least: a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a first PMOS transistor M5, and a second PMOS transistor M6; the gate of the second NMOS transistor M2 is connected to the gate of the first NMOS transistor M1, the source of the second NMOS transistor M2 is grounded, the drain of the second NMOS transistor M2 is connected to the sources of the third NMOS transistor M3 and the fourth NMOS transistor M4, respectively, the drain of the third NMOS transistor M3 is connected to the drain of the first PMOS transistor M5, the drain of the fourth NMOS transistor M4 is connected to the drain of the second PMOS transistor M6, the drain of the first PMOS transistor M5 is also connected to the gate thereof, the gate of the first PMOS transistor M5 is also connected to the gate of the second PMOS transistor M6, and the sources of the first PMOS transistor M5 and the second PMOS transistor M6 are both connected to the power supply voltage VCC; the gate of the third NMOS transistor M3 and the gate of the fourth NMOS transistor M4 are respectively used as the inverting input terminal VN and the non-inverting input terminal VP of the operational amplifier of the present embodiment, so as to access two input voltages;
the second stage circuit 33 includes at least: a fifth NMOS transistor M7, and a third PMOS transistor M8; the gate of the fifth NMOS transistor M7 is connected to the gate of the first NMOS transistor M1, the source of the fifth NMOS transistor M7 is grounded, the drain of the fifth NMOS transistor M7 is connected to the drain of the third PMOS transistor M8, the gate of the third PMOS transistor M8 is connected to the drain of the second PMOS transistor M6, and the source of the third PMOS transistor M8 is connected to the power supply voltage VCC; the drain of the third PMOS transistor M8 is used as the output terminal of the second stage circuit to output the second stage amplified voltage for the operational amplifier to drive the load CL (i.e. the capacitance formed by the upper and lower plates of the liquid crystal display panel, the same applies hereinafter); that is, the output terminal of the second stage circuit is the output terminal VOUT of the operational amplifier of the present embodiment, and the load CL is a capacitive load;
the drive current amplification circuit 24 includes at least: a voltage output circuit 241 mainly composed of a sixth NMOS transistor M9 and a fourth PMOS transistor M10, and a slew rate enhancement device 242 mainly composed of a fifth PMOS transistor M11; the gate of the sixth NMOS transistor M9 is connected to the gate of the first NMOS transistor M1, the source of the sixth NMOS transistor M9 is grounded, the drain of the sixth NMOS transistor M9 is connected to the drain of the fourth PMOS transistor M10, the gate of the fourth PMOS transistor M10 is connected to the drain of the second PMOS transistor M6, the source of the fourth PMOS transistor M10 is connected to the supply voltage, the gate of the fifth PMOS transistor M11 is connected to the drain of the fourth PMOS transistor M10, the drain of the fifth PMOS transistor M11 is grounded, and the source of the fifth PMOS transistor M11 is connected to the drain of the third PMOS transistor M8.
In the drive current amplifier circuit 24, by setting the aspect ratio of the sixth NMOS transistor M9 and the fourth PMOS transistor M10 in advance, the currents flowing through the sixth NMOS transistor and the fourth PMOS transistor are made equal; when the input voltage of the non-inverting input terminal VP is greater than or equal to the input voltage of the inverting input terminal VN, the operating state of the sixth NMOS transistor M9 is in a saturation region, and the operating state of the fourth PMOS transistor M10 is in a linear region; when the input voltage of the non-inverting input terminal VP is less than the input voltage of the inverting input terminal VN, the operation state of the sixth NMOS transistor M9 is in the linear region, and the operation state of the fourth PMOS transistor M10 is in the saturation region.
Moreover, the width-to-length ratio of the first PMOS transistor M5 is equal to the width-to-length ratio of the second PMOS transistor M6, the width-to-length ratio of the third NMOS transistor M3 is equal to the width-to-length ratio of the fourth NMOS transistor M4, the width-to-length ratio of the sixth NMOS transistor M9 is less than half of the width-to-length ratio of the second NMOS transistor M2, and the width-to-length ratio of the fourth PMOS transistor M10 is greater than the width-to-length ratio of the second PMOS transistor M6;
the frequency compensation circuit 34 includes at least: and the RC network structure consists of a compensation resistor RC and a compensation capacitor CC. The compensation resistor RC and the compensation capacitor CC perform a frequency compensation function.
In the present embodiment, the first NMOS transistor M1, the second NMOS transistor M2, and the fifth NMOS transistor M7 constitute a current mirror circuit for providing the bias current Ibias to the operational amplifier of the present embodiment. As can be seen from fig. 4, the first NMOS transistor M1 mirrors the bias current Ibias to the first stage circuit where the second NMOS transistor M2 is located and the second stage circuit where the fifth NMOS transistor M7 is located, respectively. In addition, the fifth PMOS transistor M11 is a slew rate enhancement device, and its gate is connected to the drains of the sixth NMOS transistor M9 and the fourth PMOS transistor M10.
Referring to fig. 4, the operational amplifier of the present embodiment has the following operation principle:
(1) the case where the input voltages at the two input terminals are equal (VP ═ VN): the current flowing through the first PMOS transistor M5 and the second PMOS transistor M6 at this time is equal to half of the current flowing through the second NMOS transistor M2; for the sixth NMOS transistor M9 and the fourth PMOS transistor M10, the currents flowing through both should be equal, i.e.: i9 ═ I10; if the two transistors are in the saturation region or the sixth NMOS transistor M9 is in the linear region, and the fourth PMOS transistor M10 is in the saturation region, both contradict the relationship of I9 ═ I10 according to the relationship of the current mirror, so the sixth NMOS transistor M9 is necessarily in the saturation region, and the condition is satisfied only if the fourth PMOS transistor M10 is in the linear region, because the fourth PMOS transistor M10 is in the linear region, the B-point potential is pulled up to be close to the power supply voltage VCC, and the fifth PMOS transistor M11 is in the cut-off state, and the Vout output terminal is not discharged.
(2) Case where the input voltage at the non-inverting input is greater than the input voltage at the inverting input (VP > VN): at this time, the current flowing through the branch of the fourth NMOS transistor M4 and the second PMOS transistor M6 is greater than the current flowing through the branch of the third NMOS transistor M3 and the first PMOS transistor M5, so that the potential at the point a decreases, the fourth PMOS transistor M10 further deviates from the saturation region and is in a deep linear state, so that the potential at the point B still approaches the power supply voltage VCC, and the fifth PMOS transistor M11 is in an off state, but the current flowing through the third PMOS transistor M8 increases due to the decrease in the potential at the point a, the capacitor load CL is charged, and the charging current may be greater than the bias current Ibias flowing through the fifth NMOS transistor M7, so that the circuit has a high forward slew rate.
(3) Case of non-inverting input smaller than inverting input (VP < VN): at this time, the current flowing through the branch of the fourth NMOS transistor M4 and the second PMOS transistor M6 is smaller than the current flowing through the branch of the third NMOS transistor M3 and the first PMOS transistor M5, so that: this raises the potential at point a, and since the aspect ratio of the sixth NMOS transistor M9 and the fourth PMOS transistor M10 is reasonably set in advance, the fourth PMOS transistor M10 enters the saturation region and the sixth NMOS transistor M9 enters the linear region in this state, at which point B is pulled close to ground, the fifth PMOS transistor M11 is turned on, a large discharge current is supplied to the output terminal Vout, and thus the circuit has a high negative slew rate.
In the cases (1) and (2), the fifth PMOS transistor M11 is in an off state in a static state, and thus, no static current is consumed, static power consumption is not increased, and design requirements for low power consumption in an integrated circuit can be satisfied.
In one embodiment, as shown in FIG. 5:
the bias circuit 31 includes at least: a first PMOS transistor M1'; the drain of the first PMOS transistor M1' is connected to the bias reference current Ibias, the drain of the first PMOS transistor M1' is connected to the gate thereof, and the source of the first PMOS transistor M1' is connected to the power supply voltage VCC.
The first stage circuit 32 includes at least: a second PMOS transistor M2', a third PMOS transistor M3', a fourth PMOS transistor M4', a first NMOS transistor M5' and a second NMOS transistor M6 '; the gate of the second PMOS transistor M2' is connected to the gate of the first PMOS transistor M1', the source of the second PMOS transistor M2' is connected to the power supply voltage VCC, the drain of the second PMOS transistor M2' is connected to the sources of the third PMOS transistor M3' and the fourth PMOS transistor M4', respectively, the drain of the third PMOS transistor M3' is connected to the drain of the first NMOS transistor M5', the drain of the fourth PMOS transistor M4' is connected to the drain of the second NMOS transistor M6', the drain of the first NMOS transistor M5' is further connected to the gate thereof, the gate of the first NMOS transistor M5' is further connected to the gate of the second NMOS transistor M6', and the sources of the first NMOS transistor M5' and the second NMOS transistor M6' are both grounded; the grid electrode of the third PMOS transistor M3 'and the grid electrode of the fourth PMOS transistor M4' are respectively used as an inverting input end VN and a non-inverting input end VP of the operational amplifier so as to be connected with two paths of input voltages;
the second stage circuit 33 includes at least: a fifth PMOS transistor M7', and a third NMOS transistor M8'; the gate of the fifth PMOS transistor M7 'is connected to the gate of the first PMOS transistor M1', the source of the fifth PMOS transistor M7 'is connected to the supply voltage, the drain of the fifth PMOS transistor M7' is connected to the drain of the third NMOS transistor M8', the gate of the third NMOS transistor M8' is connected to the drain of the second NMOS transistor M6', and the source of the third NMOS transistor M8' is grounded; the drain of the third NMOS transistor M8' is used as the output terminal of the second stage circuit to output the second stage amplified voltage for the operational amplifier to drive the load CL; that is, the output terminal of the second stage circuit is the output terminal Vout of the operational amplifier of the present embodiment, and the load CL is a capacitive load;
the drive current amplification circuit 24 includes at least: a voltage output circuit 241 mainly composed of a sixth PMOS transistor M9' and a fourth NMOS transistor M10', and a slew rate enhancement device 242 mainly composed of a fifth NMOS transistor M11 '; the gate of the sixth PMOS transistor M9' is connected to the gate of the first PMOS transistor M1', the source of the sixth PMOS transistor M9' is connected to the power supply voltage VCC, the drain of the sixth PMOS transistor M9' is connected to the drain of the fourth NMOS transistor M10', the gate of the fourth NMOS transistor M10' is connected to the drain of the second NMOS transistor M6', the source of the fourth NMOS transistor M10' is grounded, the gate of the fifth NMOS transistor M11' is connected to the drain of the fourth NMOS transistor M10', the drain of the fifth NMOS transistor M11' is connected to the power supply voltage VCC, and the source of the fifth NMOS transistor M11' is connected to the drain of the third NMOS transistor M8 '.
In the drive current amplifier circuit 24, by setting the width-to-length ratios of the sixth PMOS transistor M9 'and the fourth NMOS transistor M10' in advance, the currents flowing through the sixth PMOS transistor M9 'and the fourth NMOS transistor M10' are made equal; when the input voltage of the non-inverting input terminal VP is greater than or equal to the input voltage of the inverting input terminal VN, the operating state of the sixth PMOS transistor M9 'is in a saturation region, and the operating state of the fourth NMOS transistor M10' is in a linear region; when the input voltage of the non-inverting input terminal VP is less than the input voltage of the inverting input terminal VN, the operation state of the sixth PMOS transistor M9 'is in the linear region, and the operation state of the fourth NMOS transistor M10' is in the saturation region. Moreover, the width-to-length ratio of the first NMOS transistor M5 'is equal to the width-to-length ratio of the second NMOS transistor M6', the width-to-length ratio of the third PMOS transistor M3 'is equal to the width-to-length ratio of the fourth PMOS transistor M4', the width-to-length ratio of the sixth PMOS transistor M9 'is less than half of the width-to-length ratio of the second PMOS transistor M2', and the width-to-length ratio of the fourth NMOS transistor M10 'is greater than the width-to-length ratio of the second NMOS transistor M6';
the specific operation principle of the circuit shown in fig. 5 is similar to that of the circuit shown in fig. 4 of the present invention, and is not repeated herein.
In a driving system of a liquid crystal display device, it is necessary to periodically reverse the polarity of gray scale voltages transmitted to pixel cells to prevent the afterimage phenomenon caused by liquid crystal polarization. The polarity inversion method adopted by the display device mainly has three methods: frame inversion (frame inversion), column inversion (column inversion), and dot inversion (dot inversion). In the case of single-dot inversion, the pixel voltages of the adjacent pixel units have opposite polarities in one frame period, and the polarity inversion of the pixel units in the same row generates a large power consumption, but the display effect of the liquid crystal display device is better as the number of times of the polarity inversion is larger. The display effect and power consumption are thus a trade-off relationship at design time.
In one embodiment, each drive channel 1201 includes: a plurality of first selection switches and a plurality of second selection switches, the buffer includes a plurality of first buffers and second buffers, wherein:
the input ends of the plurality of first selection switches are commonly connected to the input end of the driving channel;
each first buffer is connected between the output end of a first selection switch and the input end of a second selection switch;
the output ends of the plurality of second selection switches are commonly connected to the input end of the second buffer;
the output end of the second buffer is connected to the input end of the digital-to-analog converter;
in each driving channel, the plurality of first buffers receive pixel data according to a row sequence by controlling the on and off of the plurality of first selection switches, and the sequence of outputting the pixel data by the plurality of first buffers is adjusted by controlling the on and off of the plurality of second selection switches, so that the number of times that the pixel voltage corresponding to the pixel data needs to be inverted when being output is reduced.
In one embodiment, the adjusting the order in which the plurality of first buffers output the pixel data by controlling the plurality of second selection switches to be turned on and off includes: the pixel data of two adjacent pixel units in the same column are used as one group, and the output sequence of the pixel data of two pixel units in an even group is reversed by controlling the opening and closing of the plurality of second selection switches.
In one embodiment, the adjusting the order in which the plurality of first buffers output the pixel data by controlling the plurality of second selection switches to be turned on and off includes: and taking the pixel data of two adjacent pixel units in the same column as a group, and reversing the output sequence of the pixel data of the two pixel units in the odd group by controlling the on and off of the plurality of second selection switches.
In one embodiment, the adjusting the order in which the plurality of first buffers output the pixel data by controlling the plurality of second selection switches to be turned on and off includes: by controlling the on and off of the plurality of second selection switches, the pixel data of the pixel unit at the odd position in the same column is output first, and then the pixel data of the pixel unit at the even position in the same column is output, or
By controlling the on and off of the plurality of second selection switches, the pixel data of the pixel unit at the even position in the same column is output first, and then the pixel data of the pixel unit at the odd position in the same column is output.
In one embodiment, among the pixel voltages supplied to the plurality of pixel units in the same column, the pixel voltages of adjacent pixel units have opposite polarities.
The invention will now be described with reference to specific embodiments.
In one embodiment, as shown in FIG. 6, each drive channel 1201 includes:
a first-stage buffer LATCH11, LATCH12, a second-stage buffer LATCH2, a digital-to-analog converter DAC, an operational amplifier OPA, a drive current amplifying circuit IPA, and an output SWITCH. The source driver further includes selection switches SW1, SW3, SW2 and SW4 connected to the first-stage buffers LATCH11, LATCH12, respectively. The input terminal Sin of the source driver receives a digital signal representing pixel data from the data bus, and controls on and off of the selection SW1, SW3, SW2 and SW4 according to a control signal, respectively, thereby controlling data LATCH and release of the first-stage buffers LATCH11 and LATCH12, and finally controlling the polarity of the pixel voltage output from the output terminal Sout. The structures and functions of the digital-to-analog converter DAC, the operational amplifier OPA, the driving current amplifying circuit IPA, and the output SWITCH have been described above and will not be described again.
Unlike the source driver 120 shown in fig. 2, when the source driver 120 shown in fig. 6 operates, the gate driver does not turn on the tfts row by row, but turns on the tfts in a certain row sequence, for example, the tfts are turned on in a row sequence of 1, 2 rows first and then 4,3 rows. Accordingly, the source driver 220 discharges the pixel voltages of the corresponding pixel units according to the sequence.
Fig. 7a is a timing diagram illustrating a pixel data processing process of the source driver shown in fig. 6 according to the embodiment of the invention, fig. 7b is a waveform diagram illustrating driving signals provided by the gate driver corresponding to the source driver shown in fig. 6 according to the embodiment of the invention, and fig. 7c is a schematic diagram illustrating a pixel output corresponding to the pixel data of the source driver shown in fig. 6 according to the embodiment of the invention.
In fig. 7a, the pixel DATA of the nth frame is converted into pixel voltages of a +, B-, C +, D-, E +, F-, G +, H-, I +, J-, CLK denotes a clock signal, and numerals 1 to 10 denote first to tenth clock periods, and in fig. 7B, CNTs 1 to CNT8 denote driving signals applied to gate scan lines G1 to G8, respectively.
With reference to fig. 6 and fig. 7a-7b, the pixel data processing process provided by the present invention specifically includes the following steps.
Step 1: in the first clock cycle, SW1 is turned on, and the pixel voltage a + is latched by LATCH 11;
step 2: in the second clock cycle, SW2 is turned on and the pixel voltage B-is latched by LATCH 12;
and step 3: in the third clock period, the gate driver generates a driving signal to be sent to the gate scanning line G1 to turn on the thin film transistor on G1, at which time SW3 is turned on, a + in LATCH11 is latched by LATCH2 and driven to the corresponding pixel unit (corresponding to the first row in fig. 7C), and at the same time SW1 is turned on, C + is latched by LATCH 11;
and 4, step 4: in the fourth clock period, the gate driver generates a driving signal to be sent to the gate scanning line G2 to turn on the thin film transistor on G2, meanwhile SW4 is turned on, B-in LATCH12 is latched by LATCH2 and driven to the corresponding pixel unit (corresponding to the second row in FIG. 7 c), meanwhile SW2 is turned on, and D-is latched by LATCH 12;
and 5: in the fifth clock period, the gate driver generates a driving signal to be sent to the gate scanning line G4 to turn on the thin film transistor on G4, while SW4 is turned on, D-in LATCH12 is latched by LATCH2 and driven to the corresponding pixel unit (corresponding to the fourth row in fig. 7 c), while SW2 is turned on, E + is latched by LATCH 12;
step 6: in the sixth clock period, the gate driver generates a driving signal to be sent to the gate scanning line G3 to turn on the thin film transistor on G3, and SW3 is turned on, C + in LATCH11 is latched by LATCH2 and driven to the corresponding pixel unit (corresponding to the third row in fig. 7C), and SW1 is turned on, and F-is latched by LATCH 11;
and 7: in the seventh clock period, the gate driver generates a driving signal to be sent to the gate scanning line G5 to turn on the thin film transistor on G5, and SW4 is turned on, E + in LATCH12 is latched by LATCH2 and driven to the corresponding pixel unit (corresponding to the fifth row in fig. 7 c), and SW2 is turned on, and G + is latched by LATCH 12;
and 8: in the eighth clock period, the gate driver generates a driving signal to be sent to the gate scanning line G6 to turn on the thin film transistor on G6, and SW3 is turned on, and F-in LATCH11 is latched by LATCH2 and driven to the corresponding pixel unit (corresponding to the sixth row in fig. 7 c), and SW1 is turned on, and H-is latched by LATCH 11;
and step 9: in the ninth clock period, the gate driver generates a driving signal to be sent to the gate scanning line G8 to turn on the thin film transistor on G8, and SW3 is turned on, H-in LATCH11 is latched by LATCH2 and driven to the corresponding pixel unit (corresponding to the eighth row in fig. 7 c), and SW1 is turned on, and I + is latched by LATCH 11;
step 10: in the tenth clock cycle, the gate driver generates the driving signal to the gate scan line G7 to turn on the thin film transistor on G7, while G7 is turned on, SW4 is turned on, G + in LATCH12 is latched by LATCH2 and driven to the corresponding pixel cell (corresponding to the seventh row in fig. 7 c), while SW2 is turned on, and J-is latched by LATCH 12. And so on.
As shown in fig. 7c, in the display of the nth frame data, during the third clock period, the pixel voltage of the pixel unit of the first row and the first column is a +, during the fourth clock cycle, the pixel voltage of the pixel cell of the second row and the first column is B-, during the fifth clock cycle, the pixel voltage of the pixel cell of the first column in the fourth row is D-, during the sixth clock cycle, the pixel voltage of the pixel unit of the third row and the first column is C +, during the seventh clock cycle, the pixel voltage of the pixel unit of the first column of the fifth row is E +, during the eighth clock cycle, the pixel voltage of the pixel cell in the sixth row and the first column is F-, during the ninth clock cycle, the pixel voltage of the pixel cell of the eighth row and first column is H-, and during the tenth clock cycle, the pixel voltage of the pixel cell of the seventh row and first column is G +. Therefore, although each pixel unit only has pixel voltage in one clock period, due to the visual pause effect of human eyes and exceeding a certain refresh rate, the human eyes can see a display picture of the whole frame of data.
In this embodiment, the gate driver sequentially turns on the tfts on the gate scan lines in the row sequence of G1, G2, G4, G3, G5, G6, G8, and G7, and accordingly, the pixel voltages of the source driver are supplied in the order of a +, B-, D-, C +, E +, F-, H-, and G +. It can be known through calculation that the pixel voltage of the source driver is inverted 4 times in the process, while the pixel voltage of the source driver shown in fig. 2 needs to be inverted 7 times under the same condition, that is, the driving method of the source driver applying the embodiment of the present invention can reduce the inversion 3 times, thereby reducing the power consumption, but also achieving the display effect of the driving method of single-dot inversion.
In one embodiment, the selection switch can be implemented by various types of MOS transistors and combinations thereof.
In one embodiment, as shown in FIG. 8, each drive channel 1201 includes a first stage buffer LATCH 11-LATCH 14, a second stage buffer LATCH2, a digital-to-analog converter DAC, an operational amplifier OPA, a drive current amplifier circuit IPA, and an output SWITCH SWITCH. The source driver further includes selection switches SW11 to SW14, SW21 to SW24 connected to the first-stage buffers LATCH11 to LATCH14, respectively. The input terminal Sin of the source driver receives digital signals representing pixel data from the data bus, and controls the on and off of the selection switches SW11 to SW14, SW21 to SW24, respectively, according to driving signals, thereby controlling the data LATCH and release of the first-stage buffers LATCH11 to LATCH14, LATCH2, and finally controlling the polarity of the pixel voltage output from the output terminal Sout.
With the circuit shown in fig. 8, the gate driver can turn on the thin film transistors on the gate scan lines sequentially according to the row sequence of G1, G3, G5, G7, G2, G4, G6, and G8, and accordingly, the pixel voltage of the source driver is transmitted in the sequence of a +, C +, E +, G +, B-, D-, F-, and H-, which is calculated to indicate that the pixel voltage of the source driver is inverted 1 time in the process, while the pixel voltage of the source driver shown in fig. 2 needs to be inverted 7 times under the same condition, that is, the source driver applying this embodiment can reduce 6 times of inversion, thereby reducing power consumption, but also achieving the display effect of the single-dot inversion driving method.
According to the embodiment of the invention, the number of the parallel latches is expanded and the opening sequence of the corresponding gate drive signals is modified, so that the inversion times of the pixel voltage can be reduced, and the power effect is reduced under the condition of not influencing the display effect.
Meanwhile, in an embodiment, an embodiment of the present invention also provides an array substrate, including: a thin film transistor array arranged in rows and columns; a gate driver for scanning gate scan lines to turn on the thin film transistors of each row; the source driver provided by the embodiment of the invention is also provided.
Meanwhile, in an embodiment, the embodiment of the present invention also provides a liquid crystal display panel, which is characterized by including an array substrate and a color film substrate that are arranged in a box-to-box manner, and a liquid crystal disposed between the array substrate and the color film substrate, where the array substrate includes the source driver provided in the embodiment of the present invention.
According to the above embodiments:
the invention provides a source electrode driver, an array substrate and a liquid crystal display panel.A driving channel of the source electrode driver comprises an operational amplifier and a driving current amplifying circuit, and the driving current amplifying circuit is used for amplifying the driving current of the operational amplifier so as to enable the driving current to be larger than the bias current of the operational amplifier, thereby enhancing the slew rate of the operational amplifier; on the basis, the slew rate of the pixel voltage is improved, the rotation speed of the liquid crystal is accelerated, the time of the display panel changing from dark to bright is shortened, the luminous flux passing through the display panel in unit time is increased, the light penetration rate of the display panel is further enhanced, and the technical problem of low light penetration rate of the existing display panel is solved; meanwhile, the method does not need to change the processing surface of the display panel and can be compatible with the existing display panel.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. A source driver comprising a plurality of drive channels, each drive channel providing a pixel voltage to a plurality of pixel drive transistors in a same column of an array panel, each drive channel comprising:
the buffer is used for latching the pixel data input by the input end of the driving channel;
the digital-to-analog converter is used for converting the pixel data in the digital signal format into an analog signal;
an operational amplifier for supplying a pixel voltage;
and the driving current amplifying circuit is used for amplifying the driving current of the operational amplifier so as to enable the driving current to be larger than the bias current of the operational amplifier, thereby enhancing the slew rate of the operational amplifier.
2. The source driver of claim 1, wherein the operational amplifier comprises: the circuit comprises a bias circuit, a first-stage circuit and a second-stage circuit; wherein,
the bias circuit is used for providing a bias current;
the first-stage circuit is connected with the bias circuit and used for comparing and first-stage amplifying the two paths of input voltages when the two paths of input voltages are accessed so as to output a first-stage amplified voltage;
the second-stage circuit is connected with the first-stage circuit and used for carrying out second-stage amplification on the first-stage amplified voltage so as to output second-stage amplified voltage for the operational amplifier to provide pixel voltage;
the driving current amplifying circuit is respectively connected with the bias circuit, the first-stage circuit and the second-stage circuit and is used for adjusting the driving current of the operational amplifier according to the first-stage amplifying voltage so that the driving current is larger than the bias current, and therefore the slew rate of the operational amplifier is enhanced.
3. The source driver of claim 2, wherein the driving current amplification circuit comprises:
the voltage output circuit is used for outputting a control voltage according to the magnitude of the first-stage amplification voltage;
and the slew rate enhancing device is connected with the voltage output circuit and used for controlling the self turn-off or turn-on according to the control voltage so as to adjust the driving current of the operational amplifier, so that the driving current of the operational amplifier is larger than the bias current, and the slew rate of the operational amplifier is enhanced.
4. The source driver of claim 3, wherein the voltage output circuit comprises: the source electrode of the NMOS transistor is grounded, the grid electrode of the NMOS transistor is connected with the bias circuit, the drain electrode of the NMOS transistor is connected with the drain electrode of the PMOS transistor, the source electrode of the PMOS transistor is connected with power supply voltage, and the grid electrode of the PMOS transistor is connected with the first-stage amplification voltage; and the drain electrode of the PMOS transistor is used as the output end of the voltage output circuit to output a control voltage.
5. The source driver of claim 3, wherein the slew rate enhancement device is a PMOS transistor or an NMOS transistor.
6. The source driver of claim 2, wherein the operational amplifier further comprises:
and the frequency compensation circuit is respectively connected with the first-stage circuit and the second-stage circuit and is used for eliminating self-oscillation so as to synchronize the input and output frequencies of the operational amplifier.
7. The source driver of any of claims 1 to 6, wherein each of the driving channels further comprises a plurality of first selection switches and a plurality of second selection switches, the buffer comprises a plurality of first buffers and a second buffer, wherein:
the input ends of the plurality of first selection switches are commonly connected to the input end of the driving channel;
each first buffer is connected between the output end of a first selection switch and the input end of a second selection switch;
the output ends of the plurality of second selection switches are commonly connected to the input end of the second buffer;
the output end of the second buffer is connected to the input end of the digital-to-analog converter.
8. The source driver of claim 7, wherein, among the pixel voltages supplied to the plurality of pixel cells of the same column, the pixel voltages of adjacent pixel cells are opposite in polarity.
9. An array substrate, comprising: a thin film transistor array arranged in rows and columns; a gate driver for scanning gate scan lines to turn on the thin film transistors of each row; and a source driver as claimed in any one of claims 1 to 8.
10. A liquid crystal display panel, comprising an array substrate and a color filter substrate which are arranged in a box-to-box manner, and liquid crystal arranged between the array substrate and the color filter substrate, wherein the array substrate comprises the source driver as claimed in any one of claims 1 to 8.
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| CN116882355B (en) * | 2023-09-05 | 2023-11-07 | 吉林大学 | OPA drive circuit based on multidimensional driver array and electronic equipment |
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Application publication date: 20190723 |