[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

TWI521666B - Multi-component chip package structure - Google Patents

Multi-component chip package structure Download PDF

Info

Publication number
TWI521666B
TWI521666B TW102136208A TW102136208A TWI521666B TW I521666 B TWI521666 B TW I521666B TW 102136208 A TW102136208 A TW 102136208A TW 102136208 A TW102136208 A TW 102136208A TW I521666 B TWI521666 B TW I521666B
Authority
TW
Taiwan
Prior art keywords
component
package structure
chip package
wafer
epitaxial
Prior art date
Application number
TW102136208A
Other languages
English (en)
Other versions
TW201426948A (zh
Inventor
xiao-chun Tan
Original Assignee
Silergy Semiconductor Technology Hangzhou Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silergy Semiconductor Technology Hangzhou Ltd filed Critical Silergy Semiconductor Technology Hangzhou Ltd
Publication of TW201426948A publication Critical patent/TW201426948A/zh
Application granted granted Critical
Publication of TWI521666B publication Critical patent/TWI521666B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dc-Dc Converters (AREA)

Description

多組件的晶片封裝結構
本發明涉及半導體封裝，尤其涉及一種包括多個組件的晶片封裝結構。
隨著電子元件的小型化，輕量化以及多功能化的需求的增加，對半導體封裝密度的要求越來越高，以來達到縮小封裝體積的效果。因此，多晶片封裝結構已經成為一新的熱點。然而，在多晶片半導體封裝結構中，晶片間的連接方法對半導體封裝的尺寸和性能具有至關重要的影響。
圖1所示為採用現有技術的一種多晶片封裝結構的剖面圖。在該實現方式中，下層晶片3和上層晶片5堆疊設置在印刷電路板1上。下層晶片3的一表面透過黏合劑7連接至印刷電路板1的上表面；上層晶片5的一表面透過黏合劑9連接至下層晶片3的另一表面。採用這種實現方式，為了暴露底層晶片3邊緣上的焊墊，上層晶片5的寬度需要小於下層晶片3的寬度。
底層晶片3上的焊墊和上層晶片5上的焊墊分別透過第一組接合引線11和第二組接合引線15電性連接至印刷 電路板1。因此，第二組接合引線15的高度要大於上層晶片5。這樣，用於封裝第一組接合引線11和第二組接合引線15以及上層晶片5和下層晶片3的塑封殼的厚度會較大。另外，數目較多的接合引線之間的干擾也會影響晶片的高頻性能。
有鑒於此，本發明的目的在於提供一種多組件的晶片封裝結構，以解決現有技術中封裝厚度過大，以及封裝結構對晶片性能的不利影響。
依據本發明一實施例的多組件的晶片封裝結構，包括，位於底層的第一組件；位於所述第一組件之上的至少一個第二組件；每一所述第二組件透過一組突起結構電性連接至所述第一組件；層疊在所述第二組件之上的至少一個第三組件；位於所述第三組件的至少一側邊的至少一外延結構，所述外延結構的厚度小於所述第三組件的厚度；所述外延結構將所述第三組件的電極性引出；一組接合引線將所述外延結構連接至所述第一組件。
較佳的，所述外延結構的厚度小於所述第三組件的厚度。
進一步的，所述第一組件包括一印刷電路板或者一引線框架。
進一步的，所述第二組件包括一晶片。
進一步的，所述第三組件包括一晶片或者一磁性元件。
較佳的，所述第二組件之間相互間隔排列，並且互相不接觸。
較佳的，所述晶片封裝結構還包括位於所述第二組件和所述第三組件之間，以及所述第三組件之間的黏合層。
較佳的，所述突起結構包括凸塊或者焊錫球。
較佳的，所述第三組件的電極性透過所述接合引線在所述晶片封裝結構內直接與第二組件的電極性連接。
依據本發明實施例的多組件的晶片封裝結構，可以進一步的減小封裝結構的厚度，從而使晶片封裝結構的體積更小；另一方面，位於上層的組件的面積在封裝尺寸範圍內，可以設置為最大。
1‧‧‧印刷電路板
3‧‧‧下層晶片
5‧‧‧上層晶片
7‧‧‧黏合劑
9‧‧‧黏合劑
11‧‧‧第一組接合引線
15‧‧‧第二組接合引線
200‧‧‧晶片封裝結構
201‧‧‧印刷電路板
202‧‧‧焊錫球
203‧‧‧晶片
204‧‧‧黏合層
205‧‧‧接合引線
206‧‧‧外延結構
207‧‧‧焊墊
208‧‧‧電感
300‧‧‧晶片封裝結構
301‧‧‧引線框架
301-1‧‧‧引腳
302‧‧‧焊錫球
303‧‧‧晶片
304‧‧‧黏合層
305‧‧‧接合引線
306‧‧‧外延結構
307‧‧‧焊墊
308‧‧‧電感
圖1所示為採用現有技術的一種多晶片封裝結構的剖面圖；圖2A所示為依據本發明實施例1的多組件的晶片封裝結構的剖面圖；圖2B所示為圖2A所示的晶片封裝結構中位於頂層的第三組件的俯視圖；圖3A所示為依據本發明實施例2的多組件的晶片封裝結構的剖面圖； 圖3B所示為圖3A所示的晶片封裝結構中位於頂層的第三組件的俯視圖。
以下結合圖式對本發明的幾個較佳實施例進行詳細描述，但本發明並不僅僅限於這些實施例。本發明涵蓋任何在本發明的精髓和範圍上做的替代、修改、等效方法以及方案。為了使公眾對本發明有徹底的瞭解，在以下本發明較佳實施例中詳細說明了具體的細節，而對本領域具有通常知識者來說沒有這些細節的描述也可以完全理解本發明。
參考圖2A，所示為依據本發明實施例1的多組件的晶片封裝結構的剖面圖。在該實施例中，多組件的晶片封裝結構200包括位於底層的印刷電路板201(第一組件)；位於印刷電路板之上的晶片203(第二組件)；晶片203透過焊錫球202(突起結構)電性連接至晶片203；位於晶片203之上的電感208(第三組件)；位於電感208的相對的兩個側邊的外延結構206；位於外延結構206上的焊墊207透過接合引線205連接至印刷電路板201。
參考圖2B，所示為圖2A所示的晶片封裝結構中位於上層的電感208和外延結構206的俯視圖。兩個外延結構206位於電感208的相對的兩個側邊，以將電感的兩個電極性(例如電感的輸入端和輸出端)透過外延結構206向 外引出。
進一步的，晶片封裝結構200還包括位於晶片203和電感208之間的黏合層204，以實現晶片203和電感208之間的電氣隔離，防止相互之間的干擾，增強系統的穩定性；以及增加晶片封裝結構200的穩定性。
在該實施例中，外延結構206的厚度小於電感208的厚度。採用這種實現方式，可以給接合引線205提供預留的安裝空間。當外延結構的厚度等於或者大於第三組件的厚度時，則接合引線205的高度勢必會佔用一定的空間高度。因此，圖2A所示的晶片封裝結構的實施例降低了晶片封裝結構的厚度，減小了晶片封裝結構的體積。
透過對依據本發明實施例的多組件的晶片封裝結構200的詳細說明，本領域具有通常知識者可以得知，位於第一組件(印刷電路板201)之上的第二組件(晶片203)的數目可以不限於一個，可以為多個，多個第二組件之間相互間隔，互不接觸，依次排列於第一組件之上。第三組件覆蓋所有第二組件區域，位於所有第二組件的上方。位於底層的第一組件也可以替換為包括多個引腳的引線框架，第二組件透過焊錫球或者凸塊連接至引線框架的相應引腳，位於上層的第三組件透過接合引線連接至引線框架的引腳，從而使引腳具有相應的電極性。
採用圖2所示的多組件的晶片封裝結構，晶片封裝結構的體積大大減小，並且具有很好的機械穩定性，同時也具有很好的電氣穩定性。
另外，對磁性元件而言，如電感等，其體積一般都較大，當採用圖2所示的多組件的晶片封裝結構時，採用層疊式的封裝結構，將電感和晶片封裝於一單一的封裝結構中，可以容納更大體積，電感值更大的電感，更有利於系統的高集成化和小體積化。
參考圖3A，所示為依據本發明實施例2的多組件的晶片封裝結構的剖面圖。在該實施例中，多組件的晶片封裝結構300包括位於底層的具有多個引腳的引線框架301；位於引線框架301之上的晶片303(第二組件)；晶片303透過焊錫球302(突起結構)電性連接至晶片303；位於晶片303之上的電感308(第三組件)；位於電感308的一個側邊的外延結構306；位於外延結構306上的焊墊307透過接合引線305連接至引線框架的相應引腳301-1。
參考圖3B，所示為圖3A所示的晶片封裝結構中位於上層的電感308和外延結構306的俯視圖。兩個外延結構306位於電感308的一個側邊，以將電感的兩個電極性(例如電感的輸入端和輸出端)透過外延結構306向外引出。
進一步的，晶片封裝結構300還包括位於晶片303和電感308之間的黏合層304，以實現晶片303和電感308之間的電氣隔離，防止相互之間的干擾，增強系統的穩定性；以及增加晶片封裝結構300的穩定性。
另外，在該實施例中，電感308的一個電極性透過一 外延結構306連接至引線框架的一引腳301-1，同時晶片303上的一個電極性透過焊錫球302同樣連接至引腳301-1，從而在封裝結構內部就將電感的電極性與晶片上的電極性直接進行電性連接。這樣的連接方式，相比透過封裝結構的引腳在封裝結構外部進行電性連接的實現方式，不僅節省了引腳的數目，也避免了透過引腳之間的外部連接方式所帶來的干擾以及功耗等缺陷。
採用圖3所示的多組件的晶片封裝結構，晶片封裝結構的體積大大減小，並且具有很好的機械穩定性，同時也具有很好的電氣穩定性。另外，對磁性元件而言，如電感等，其體積一般都較大，當採用圖3所示的多組件的晶片封裝結構時，將電感和晶片封裝於一單一的封裝結構中，可以容納更大體積，電感值更大的電感，更有利於系統的高集成化和小體積化。
需要說明的是，在本文中，諸如第一和第二等之類的關係術語僅僅用來將一個實體或者操作與另一個實體或操作區分開來，而不一定要求或者暗示這些實體或操作之間存在任何這種實際的關係或者順序。而且，術語“包括”、“包含”或者其任何其他變體意在涵蓋非排他性的包含，從而使得包括一系列要素的過程、方法、物品或者設備不僅包括那些要素，而且還包括沒有明確列出的其他要素，或者是還包括為這種過程、方法、物品或者設備所固有的要素。在沒有更多限制的情況下，由語句“包括一個……”限定的要素，並不排除在包括所述要素的過程、 方法、物品或者設備中還存在另外的相同要素。
依照本發明的實施例如上文所述，這些實施例並沒有詳盡敍述所有的細節，也不限制該發明僅為所述的實施例。顯然，根據以上描述，可作很多的修改和變化。本說明書選取並具體描述這些實施例，是為了更好地解釋本發明的原理和實際應用，從而使所屬技術領域具有通常知識者能很好地利用本發明以及在本發明基礎上的修改使用。本發明僅受申請專利範圍及其全部範圍和等效物的限制。
200‧‧‧晶片封裝結構
201‧‧‧印刷電路板
202‧‧‧焊錫球
203‧‧‧電感
204‧‧‧黏合層
205‧‧‧接合引線
206‧‧‧外延結構
207‧‧‧焊墊
208‧‧‧電感

Claims (10)

  1. 一種多組件的晶片封裝結構，包括：位於底層的第一組件；位於該第一組件之上的至少一個第二組件，該第二組件透過一組突起結構電性連接至該第一組件；在該第二組件上的至少一個第三組件；位於該第三組件的至少一側邊的至少一個外延結構，該外延結構將該第三組件的電極性引出，其中，該第三組件及該外延結構係在該晶片封裝結構的上層中；以及一組接合引線，該組接合引線將該外延結構電性連接至該第一組件。
  2. 根據申請專利範圍第1項所述的晶片封裝結構，其中，該外延結構的厚度小於該第三組件的厚度。
  3. 根據申請專利範圍第1項所述的晶片封裝結構，其中，該第一組件包括一印刷電路板。
  4. 根據申請專利範圍第1項所述的晶片封裝結構，其中，該第一組件包括一引線框架。
  5. 根據申請專利範圍第1項所述的晶片封裝結構，其中，該第二組件包括一晶片。
  6. 根據申請專利範圍第1項所述的晶片封裝結構，其中，該第三組件包括一晶片。
  7. 根據申請專利範圍第1項所述的晶片封裝結構，其中，該第三組件包括一磁性元件。
  8. 根據申請專利範圍第1項所述的晶片封裝結構，其 中，還包括位於該第二組件和該第三組件之間的黏合層。
  9. 根據申請專利範圍第1項所述的晶片封裝結構，其中，該組突起結構包括凸塊或者焊錫球。
  10. 根據申請專利範圍第1項所述的晶片封裝結構，其中，該第三組件的電極性透過該組接合引線電性連接至該第一組件之對應的電極性。
TW102136208A 2012-12-11 2013-10-07 Multi-component chip package structure TWI521666B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210538747.3A CN103021989B (zh) 2012-12-11 2012-12-11 一种多组件的芯片封装结构

Publications (2)

Publication Number Publication Date
TW201426948A TW201426948A (zh) 2014-07-01
TWI521666B true TWI521666B (zh) 2016-02-11

Family

ID=47970421

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102136208A TWI521666B (zh) 2012-12-11 2013-10-07 Multi-component chip package structure

Country Status (3)

Country Link
US (1) US9054088B2 (zh)
CN (1) CN103021989B (zh)
TW (1) TWI521666B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103545297A (zh) 2013-10-25 2014-01-29 矽力杰半导体技术(杭州)有限公司 多芯片叠合封装结构及其制作方法
CN103531560A (zh) 2013-10-31 2014-01-22 矽力杰半导体技术(杭州)有限公司 芯片的封装结构及其制造方法
CN103633056B (zh) 2013-12-06 2017-09-01 矽力杰半导体技术(杭州)有限公司 引线框、封装组件及其制造方法
CN106057778B (zh) 2016-05-27 2018-11-30 矽力杰半导体技术(杭州)有限公司 封装结构及其制造方法
US20170373011A1 (en) * 2016-06-28 2017-12-28 General Electric Company Semiconductor die backside devices and methods of fabrication thereof
CN108449835B (zh) * 2018-04-03 2024-01-05 矽力杰半导体技术(杭州)有限公司 封装结构以及led照明模组

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6741494B2 (en) * 1995-04-21 2004-05-25 Mark B. Johnson Magnetoelectronic memory element with inductively coupled write wires
KR0179834B1 (ko) * 1995-07-28 1999-03-20 문정환 컬럼형 패키지
US7646029B2 (en) * 2004-07-08 2010-01-12 Philips Solid-State Lighting Solutions, Inc. LED package methods and systems
KR20070095504A (ko) * 2005-10-14 2007-10-01 인티그런트 테크놀로지즈(주) 적층형 집적회로 칩 및 패키지.
CN101371353B (zh) * 2006-01-25 2011-06-22 日本电气株式会社 电子装置封装体、模块以及电子装置
CN101183673A (zh) * 2006-11-13 2008-05-21 中芯国际集成电路制造(上海)有限公司 堆叠式多芯片半导体封装结构及封装方法
US7960997B2 (en) * 2007-08-08 2011-06-14 Advanced Analogic Technologies, Inc. Cascode current sensor for discrete power semiconductor devices
KR101715761B1 (ko) * 2010-12-31 2017-03-14 삼성전자주식회사 반도체 패키지 및 그 제조방법
CN103283019A (zh) * 2011-02-10 2013-09-04 松下电器产业株式会社 半导体装置
CN103620771B (zh) * 2011-11-10 2016-11-16 松下电器产业株式会社 半导体装置

Also Published As

Publication number Publication date
CN103021989B (zh) 2014-07-30
US20140159219A1 (en) 2014-06-12
US9054088B2 (en) 2015-06-09
TW201426948A (zh) 2014-07-01
CN103021989A (zh) 2013-04-03

Similar Documents

Publication Publication Date Title
TWI570877B (zh) Multi-component chip package structure
TWI521666B (zh) Multi-component chip package structure
KR100992344B1 (ko) 반도체 멀티칩 패키지
US20200152607A1 (en) Method of fabricating electronic package structure with multiple electronic components
US20090146285A1 (en) Fabrication method of semiconductor package
KR101943460B1 (ko) 반도체 패키지
US20120168936A1 (en) Multi-chip stack package structure and fabrication method thereof
US20050200003A1 (en) Multi-chip package
KR101219484B1 (ko) 반도체 칩 모듈 및 이를 갖는 반도체 패키지 및 패키지 모듈
KR101450761B1 (ko) 반도체 패키지, 적층형 반도체 패키지 및 반도체 패키지의 제조방법
CN105374805A (zh) 一种多芯片封装结构
KR100808582B1 (ko) 칩 적층 패키지
KR101219086B1 (ko) 패키지 모듈
KR20120126365A (ko) 유닛 패키지 및 이를 갖는 스택 패키지
KR20080067891A (ko) 멀티 칩 패키지
US20120286426A1 (en) Semiconductor device
KR101332873B1 (ko) 캐패시턴스 제공용 인터포져 및 이를 이용한 리드 프레임 타입 반도체 패키지
TWI781863B (zh) 平面式多晶片裝置
KR101236483B1 (ko) 적층형 반도체 패키지 및 이의 제조 방법
KR20120033848A (ko) 적층 반도체 패키지
KR20110067510A (ko) 패키지 기판 및 그의 제조방법
KR20070078953A (ko) 적층형 패키지
US8624365B1 (en) Interposer based capacitors for semiconductor packaging
KR101096457B1 (ko) 멀티 패키지
KR20120004877A (ko) 반도체 패키지