TWI519878B - Display panel and method of making the same - Google Patents

Description

Display panel and its making method

The invention relates to a display panel and a manufacturing method thereof, in particular to a display panel capable of realizing a narrow frame design and a manufacturing method thereof.

Please refer to Figure 1. FIG. 1 is a schematic view of a conventional display panel. As shown in FIG. 1, the conventional display panel 1 includes an array substrate 10 having an active area 10A for display and a peripheral area 10P on the outer side of the active area 10A. A pixel array 12 is disposed in the active area 10A for providing a display screen, and a peripheral trace 10 is provided in the peripheral area 10P. Generally, the gate traces 14 are disposed on the left and right peripheral regions 10P of the active region 10A, wherein one end of the gate traces 14 is electrically connected to the pixel array 12, and the gate traces 14 are The other end extends to the peripheral region 10P on the lower side of the active region 10A to be electrically connected to the driving wafer 16, whereby the driving wafer 16 can provide the gate driving signal to the pixel array 12 via the gate wiring 14. As can be seen from the above, it is known that the peripheral region 10P of the display panel 1 must have a sufficient area to accommodate the arrangement of the gate traces 14, especially for the high-resolution display panel 1, because the number of gate traces 14 is larger. Therefore, the peripheral zone 10P located on both sides of the active zone 10A requires a larger area to accommodate the arrangement of the gate traces 14. Therefore, the conventional display panel 1 cannot realize a narrow bezel design.

One of the objects of the present invention is to provide a display panel and a method of fabricating the same to reduce the area of the peripheral region and avoid light leakage in the active region.

An embodiment of the present invention provides a display panel including an array substrate and a pixel. The array, the plurality of first signal lines, the plurality of second signal lines, the plurality of connection lines, the pair of substrates, a patterned light shielding layer, the plurality of signal routing wires, a transparent conductive shielding layer, and a display medium Floor. The array substrate has an active area and a peripheral area. The pixel array is disposed on the array substrate and located in the active region, wherein the pixel array includes a plurality of sub-pixels, and each pixel includes at least one thin film transistor element. The first signal line is disposed on the array substrate and located in the active region, wherein the first signal line extends along a first direction and is electrically connected to the thin film transistor element. The second signal line is disposed on the array substrate and located in the active region, wherein the second signal line extends along a second direction and is electrically connected to the thin film transistor element. The connection traces are disposed on the array substrate and located in the peripheral region. The opposite substrate is disposed opposite to the array substrate. The patterned light shielding layer is disposed on the opposite substrate. The signal-switching wires are disposed on the opposite substrate, wherein the signal-switching wires are electrically connected to the first signal wires and respectively connected to the connection wires. The transparent conductive shielding layer is disposed on the opposite substrate corresponding to the active region of the array substrate. The display medium layer is disposed between the array substrate and the opposite substrate.

Another embodiment of the present invention provides a method of fabricating a display panel comprising the following steps. An array substrate is provided, the array substrate having an active region and a peripheral region. A pixel array is formed in the active region on the array substrate, wherein the pixel array includes a plurality of sub-pixels, and each pixel includes at least one thin film transistor element. A plurality of first signal lines and a plurality of second signal lines are formed in the active area on the array substrate, wherein the first signal line and the second signal line are electrically connected to the thin film transistor element. A plurality of connection traces are formed in the peripheral region of the array substrate. A pair of substrates is provided. A patterned light shielding layer is formed on the opposite substrate. Forming a plurality of signal routing wires on the opposite substrate. Forming a transparent conductive shielding layer on the opposite substrate. The opposite substrate and the array substrate are bonded, and the signal switching wires are electrically connected to the first signal lines and electrically connected to the connection lines. A display medium layer is formed between the array substrate and the opposite substrate.

The display panel of the present invention can use the signal transfer wire disposed on the opposite substrate as the connection medium between the signal line in the active area of the array substrate and the driving chip of the peripheral area, which can be greatly The number of connecting lines in the peripheral area is reduced, so that the area of the surrounding area can be reduced to achieve a narrow bezel design. In addition, the display panel of the present invention can effectively shield the electric field generated when the signal transmission wire disposed on the opposite substrate transmits the signal by using the transparent conductive shielding layer disposed on the opposite substrate, thereby avoiding the light leakage problem.

1‧‧‧ display panel

10‧‧‧Array substrate

10A‧‧‧Active Area

10P‧‧‧ surrounding area

12‧‧‧ pixel array

14‧‧‧ gate trace

16‧‧‧Drive chip

30‧‧‧Array substrate

30A‧‧‧Active Area

30P‧‧‧ surrounding area

32‧‧‧ pixel array

SL1‧‧‧first signal line

SL2‧‧‧second signal line

SP‧‧‧ pixels

T‧‧‧thin film transistor components

GL‧‧‧ gate line

DL‧‧‧ data line

L1‧‧‧ first direction

L2‧‧‧ second direction

G‧‧‧ gate

GI‧‧‧ gate insulation

SE‧‧‧Semiconductor layer

S‧‧‧ source

D‧‧‧汲

34‧‧‧Protective layer

Z‧‧‧Vertical projection direction

PE‧‧‧ pixel electrode

CE‧‧‧Common electrode

Clc‧‧ liquid crystal capacitor

36‧‧‧Dielectric layer

TH‧‧‧Contact hole

BE‧‧‧ branch electrode

ST‧‧‧slit

30P1‧‧‧First contact area

30P2‧‧‧Second Contact Area

30P3‧‧‧ third contact area

X1‧‧‧ connection

381‧‧‧First layer conductor

382‧‧‧Second layer conductor

383‧‧‧third layer conductor

40‧‧‧Connecting the wiring

40X1‧‧‧ first connection

40X2‧‧‧second connection

401‧‧‧First layer conductor

402‧‧‧Second layer conductor

403‧‧‧third layer conductor

50‧‧‧ opposite substrate

52‧‧‧ patterned blackout layer

54‧‧‧Signal wire

54X1‧‧‧ first connection

54X2‧‧‧second connection

56‧‧‧flat layer

56H‧‧‧ openings

581‧‧‧First spacer

582‧‧‧Second spacer

583‧‧‧ third spacer

60‧‧‧Transparent conductive shield

60G‧‧‧ gap

62‧‧‧First transparent connection pad

64‧‧‧Second transparent connection pad

66‧‧‧Display media layer

68‧‧‧Drive chip

100‧‧‧ display panel

A‧‧‧ curve

B‧‧‧ Curve

FIG. 1 is a schematic view of a conventional display panel.

2 to 10 are schematic views showing a method of manufacturing a display panel according to an embodiment of the present invention.

Fig. 11 is a simulation result of the transmittance of the display panel of the present embodiment and the display panel of the comparative embodiment in a dark state.

The present invention will be further understood by the following detailed description of the preferred embodiments of the invention, . In the following description, the description of the directionality of the upper and lower sides, the front and rear, and the like is for the convenience of the detailed description of the embodiments, and is not intended to limit the present invention.

Please refer to Figures 2 to 10. 2 to 10 are schematic views showing a method of manufacturing a display panel according to an embodiment of the present invention, wherein FIGS. 2 and 7 illustrate a top view of the display panel of the embodiment, and FIG. 3 illustrates A schematic diagram of the pixel array of the embodiment, FIG. 4 and FIG. 8 are schematic cross-sectional views of the sub-pixel of the embodiment, and FIGS. 5 and 9 illustrate the periphery of the peripheral region of the embodiment. A schematic cross-sectional view of a contact region, and FIGS. 6 and 10 illustrate cross-sectional views of a second contact region and a third contact region of the peripheral region of the present embodiment. As shown in FIGS. 2 to 6, the array substrate 30 is first provided. The array substrate 30 may include a light-transmitting substrate such as a glass substrate, a quartz substrate, or a plastic substrate, but is not limited thereto. In addition, the array substrate 30 can be a hard substrate or a flexible substrate. The array substrate 30 has an active area 30A and a peripheral area 30P. The surrounding area 30P is set to take the initiative At least one side of the zone 30A, such as one side, two sides, three sides, or four sides. In the present embodiment, the peripheral area 30P substantially surrounds the active area 30A, but is not limited thereto. Then, a pixel array 32 is formed in the active region 30A on the array substrate 30, and a plurality of first signal lines SL1 and second signal lines SL2 are formed on the array substrate 30, and are electrically connected to the pixel array 32, respectively. As shown in FIG. 3 and FIG. 4, the pixel array 32 includes a plurality of sub-pixels SP, wherein each pixel SP includes at least one thin film transistor element T disposed on the array substrate 30 and located in the active region 30A. The first signal line SL1 and the second signal line SL2 are electrically connected to the thin film transistor element T. In this embodiment, the first signal line SL1 may include a plurality of gate lines GL extending along the first direction L1 and substantially parallel to each other, and the second signal line SL2 may include a plurality of data lines DL along the second direction. L2 extends and is substantially parallel to each other, wherein the gate line GL and the data line DL are staggered with each other. In a variant embodiment, the first signal line SL1 may include the data line DL or other signal lines of the pixel array 32, and the second signal line SL2 may include the gate line GL or other signal lines of the pixel array 32. Each of the thin film transistor elements T includes a gate G, a gate insulating layer GI, a semiconductor layer SE, a source S, a drain D, and a protective layer 34. The gate G is disposed on the array substrate 30 and connected to the corresponding first signal line SL1 (gate line GL). The gate G and the gate line GL may be formed of the same patterned conductive layer, for example, the first patterned metal layer, but not limited thereto. The semiconductor layer SE is disposed on the gate G and at least partially overlaps the gate G in the vertical projection direction Z. The material of the semiconductor layer SE may include various semiconductor materials such as germanium-based materials (for example, amorphous germanium, polycrystalline germanium, single crystal germanium, microcrystalline germanium or nanocrystalline germanium), and oxide semiconductor materials (such as indium gallium indium gallium). Zinc oxide, IGZO) or indium gallium oxide (IGO) or other suitable semiconductor materials. The gate insulating layer GI is disposed between the gate G and the semiconductor layer SE to electrically isolate the gate G from the semiconductor layer SE. The material of the gate insulating layer GI may include an inorganic insulating material, an organic insulating material, or an organic/inorganic hybrid insulating material, respectively. The source S is disposed on the semiconductor layer SE and corresponds to one side of the gate G, and is connected to the corresponding second signal line SL2 (data line DL). The drain D is disposed on the semiconductor layer SE and corresponds to the other side of the gate G. The source S, the drain D and the data line DL may be formed by the same patterned conductive layer, for example, the second patterned metal layer, but not limited thereto. The protective layer 34 is disposed on the gate insulating layer GI and covers the semiconductor layer SE, Source S and drain D. In the present embodiment, the thin film transistor element T is selected from a bottom gate thin film transistor element, but is not limited thereto. In a variant embodiment, the thin film transistor element T can also be selected from a top gate thin film transistor element or other type of thin film transistor element. In addition, each pixel SP may further include a pixel electrode PE disposed on the array substrate 30, and the common electrode CE disposed on the array substrate 30 and electrically isolated from the pixel electrode PE, wherein the pixel electrode PE and the common electrode CE A liquid crystal capacitor Clc is formed as shown in FIG. For example, the sub-pixel SP may further include a dielectric layer 36 disposed between the protective layer 34 and the gate insulating layer GI, wherein the dielectric layer 36 covers the semiconductor layer SE, the source S and the drain D. The common electrode CE may be disposed between the dielectric layer 36 and the protective layer 34. The protective layer 34 and the dielectric layer 36 have a contact hole TH to expose a part of the drain D, and the pixel electrode PE can be disposed on the protective layer 34, and is electrically isolated from the common electrode CE by the protective layer 34, and is drawn. The element electrode PE can be in contact with and electrically connected to the drain D through the contact hole TH of the protective layer 34 and the dielectric layer 36. In this embodiment, the common electrode CE of each pixel SP may be substantially a full-surface electrode, and the pixel electrode PE of each pixel SP may be a patterned electrode, which may include a plurality of branch electrodes BE, and There is a slit ST between adjacent branch electrodes BE. In a variant embodiment, the pixel electrode PE can be substantially a full-surface electrode and the common electrode CE can be a patterned electrode. In another variant embodiment, both the pixel electrode PE and the common electrode CE can be patterned electrodes. The material of the pixel electrode PE and the common electrode CE may include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or other transparent conductive material or opaque conductive material having good electrical conductivity. The material of the dielectric layer 36 and the protective layer 34 may include an inorganic dielectric material, an organic dielectric material, or an organic/inorganic hybrid dielectric material, respectively. In a variant embodiment, the dielectric layer 36 may not be disposed between the gate insulating layer GI and the protective layer 34, and the common electrode CE may be disposed between the gate insulating layer GI and the protective layer 34, that is, the common electrode CE may be The source S and the drain D are substantially in the same plane, and the pixel electrode PE is located on the protective layer 34. In another variation, the pixel electrode PE may be disposed between the dielectric layer 36 and the protective layer 34 and contacted with the drain D through the contact hole of the dielectric layer 36 and electrically connected, and the common electrode CE may be disposed. On the protective layer 34. In a variant embodiment, the pixel electrode PE and the common electrode CE may be disposed on the same horizontal plane (eg, on the protective layer 34 or the dielectric layer 36). Above, and the foregoing two are staggered.

As shown in FIG. 2, FIG. 5 and FIG. 6, the peripheral region 30P of the array substrate 30 may include the first contact region 30P1 on at least one side of the active region 30A, and the second contact region 30P2 in the active region 30A. The side, and the third contact region 30P3 are located between the active region 30A and the second contact region 30P2. For example, in this embodiment, the first contact area 30P1 may be located on the left and right sides of the active area 30A, the second contact area 30P2 may be located on the lower side of the active area 30A, and the third contact area 30P3 is located in the active area 30A and Between the second contact regions 30P2. Each of the first signal lines SL1 has a connection end X1 extending into the first contact area 30P1. In this embodiment, each connection end X1 may be a multi-layer stacked wire structure, which may include a first layer of wires 381, a second layer of wires 382 and a third layer of wires 383 stacked on each other, wherein the first layer of wires 381 may be The first signal line SL1 (gate line GL) is composed of the same layer of patterned conductive layer, for example, the first layer of patterned metal layer, and the second layer of wire 382 and the second signal line SL2 are patterned by the same layer of conductive layer, for example. The second layer of the patterned metal layer is formed, and the third layer of the wire 383 can be formed by the same layer of the patterned conductive layer as the pixel electrode PE or the common electrode CE, but is not limited thereto.

The method for manufacturing the display panel of the embodiment further includes forming a plurality of connection traces 40 in the peripheral region 30P of the array substrate 30. The connection traces 40 may be disposed in the peripheral region 30P, wherein each of the connection traces 40 has a first connection end 40X1 located in the second contact area 30P2, and a second connection end 40X2 is located in the third contact area 30P3. In this embodiment, each of the connection traces 40 can be a multi-layer stacked conductor structure, which can include a first layer of conductors 401, a second layer of conductors 402, and a third layer of conductors 403 stacked on each other. The first layer of wires 401 can be formed by the same layer of patterned conductive layer, such as a first layer of patterned metal layer, with the first signal line SL1 (gate line GL), and the second layer of wires 402 can be identical to the second signal line SL2. a layer of patterned conductive layer, for example, a second layer of patterned metal layer, and the third layer of wire 403 can be formed of the same layer of patterned conductive layer as the pixel electrode PE or the common electrode CE, as a connection pad, but not This is limited to this. For example, each connection trace 40 can also It is a single layer wire structure.

As shown in FIGS. 7 to 10, the counter substrate 50 is next provided. The opposite substrate 50 may include a light transmissive substrate, and the material thereof may be the same material or different material as the array substrate 30. Next, a patterned light shielding layer 52 is formed on the opposite substrate 50. The patterned light shielding layer 52 is, for example, a black matrix (BM) that substantially overlaps the first signal line SL1 and the second signal line SL2 in the vertical projection direction Z. In addition, if a color display effect is to be provided, a color filter pattern (not shown) may be selectively formed on the opposite substrate 50. Next, a plurality of signal routing wires 54 are formed on the opposite substrate 50, wherein the signal routing wires 54 overlap the patterned light shielding layer 52 in the vertical projection direction Z, whereby the signal switching wires 54 do not affect the aperture ratio. The material of the signal-switching wires 54 may be various opaque conductive materials such as metals or alloys, or transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), but not limited thereto. In addition, each of the signal-switching wires 54 has a first connecting end 54X1 and a second connecting end 54X2, wherein the first connecting end 54X1 corresponds to the first contact area 30P1, and the second connecting end 54X2 corresponds to the third contact area. 30P3. Subsequently, a planarization layer 56 is formed on the opposite substrate 50 to cover the patterned light shielding layer 52 and the signal switching wires 54. The material of the flat layer 56 may include an inorganic insulating material, an organic insulating material, or an organic/inorganic hybrid insulating material. A plurality of first spacers 581, a plurality of second spacers 582, and a plurality of third spacers 583 are formed on the opposite substrate 50. Precisely, the first spacer 581, the second spacer 582, and the third spacer 583 may be disposed on the planar layer 56 of the opposite substrate 50. The material of the first spacer 581, the second spacer 582, and the third spacer 58 is preferably a photosensitive insulating material, and can be fabricated by an exposure and development process, but is not limited thereto. In addition, the first spacer 581, the second spacer 582, and the third spacer 583 may have substantially the same height, but are not limited thereto. The first spacer 581 corresponds to the active region 30A of the array substrate 30 for maintaining a fixed gap between the array substrate 30 and the opposite substrate 50. The second spacer 582 corresponds to the first contact region 30P1 of the peripheral region 30P of the array substrate 30, and the third spacer 583 corresponds to the third contact region 30P3 of the peripheral region 30P of the array substrate 30. Subsequently, a transparent conductive shielding layer 60 is formed on the opposite substrate 50. Precisely, the transparent conductive shielding layer 60 The surface is formed on the surface of the flat layer 56 and corresponds to the active region 30A of the array substrate 30, and the transparent conductive shielding layer 60 has a plurality of notches 60G exposing the first spacers 581, respectively. That is, the transparent conductive shielding layer 60 does not cover the first spacer 581, whereby the transparent conductive shielding layer 60 does not come into contact with the conductive film layer such as the drain D or the pixel electrode PE on the array substrate 30. In addition to the notch 60G, the transparent conductive shielding layer 60 may be a full-surface film layer covering the area of all the sub-pixels SP, but not limited thereto. For example, the transparent conductive shielding layer 60 may include a plurality of patterns corresponding to the sub-pixels SP, respectively. In addition, the transparent conductive shielding layer 60 may also have an opening or slit design depending on the desired shielding effect. The transparent conductive shield layer 60 can have a substantially flat surface or an uneven surface such as a bump or groove design. In addition, a plurality of first transparent connection pads 62 and a plurality of second transparent connection pads 64 are formed on the opposite substrate 50, wherein the first transparent connection pads 62 respectively cover the surface of the second spacers 582 (including, for example, side and bottom surfaces) The first transparent connecting pads 62 are electrically connected to the first connecting ends 54X1 of the signal routing wires 54 respectively; the second transparent connecting pads 64 respectively cover the surface of the third spacers 583 (including, for example, the side and the bottom surface), and The two transparent connection pads 64 are electrically connected to the second connection ends 54X2 of the signal transmission wires 54 respectively. For example, the flat layer 56 has a plurality of openings 56H that partially expose the first connection end 54X1 and the second connection end 54X2 of the signal transmission lead 54 respectively, and the first transparent connection pad 62 is partially through the opening 56H and the first One of the connection ends 54X1 is in contact, and the second transparent connection pad 64 is in contact with the second connection end 54X2 via the opening 56H of the other portion. In this embodiment, the transparent conductive shielding layer 60, the first transparent connecting pad 62 and the second transparent connecting pad 64 may be the same layer of patterned transparent conductive layer, but not limited thereto, and the material thereof may include, for example, indium oxide. Tin (ITO), indium zinc oxide (IZO) or other transparent conductive material with good electrical conductivity. In a variant embodiment, the second spacer 582 and the third spacer 583 can be conductive spacers, such as metal spacers. That is, the second spacer 582 and the first transparent connection pad 62 may be in contact with each other and have conductive characteristics at the same time, and the third spacer 583 and the second transparent connection pad 64 may be in contact with each other and have conductive characteristics at the same time, thereby being Improve conductivity. In another variation, the first transparent connection pad 62 and the second transparent connection pad 64 may not be disposed, and the signal transmission wire 54 may be electrically connected to the first signal line SL1 through the second spacer 582, and Directly through the third room The spacer 583 is electrically connected to the connection trace 40.

Then, the opposite substrate 50 and the array substrate 30 are bonded, and the signal switching wires 54 are electrically connected to the first signal line SL1 and to the connection wires 40, respectively. To be precise, the first transparent connection pad 62 is simultaneously in contact with the first connection end 54X1 of the signal transmission lead 54 and the connection end X1 of the first signal line SL1, whereby the signal transfer lead 54 and the first signal line SL1 are Electrically connected via the first transparent connection pad 62. In addition, the second transparent connection pad 64 is simultaneously in contact with the second connection end 54X2 of the signal transmission lead 54 and the second connection end 40X2 of the connection trace 40, whereby the signal transfer lead 54 and the connection trace 40 can pass through the The two transparent connection pads 64 are electrically connected. Further, a display medium layer 66 is formed between the array substrate 30 and the opposite substrate 50. In this embodiment, the display medium layer 66 may include a liquid crystal layer, and the liquid crystal layer includes a positive liquid crystal layer or a negative liquid crystal layer, but is not limited thereto. Display medium layer 66 may also include an electrophoretic layer, an electronic ink layer, or other suitable display medium layer. In addition, as shown in FIG. 10, after the array substrate 30 and the opposite substrate 50 are assembled, the opposite substrate 50 is in contact with the active region 30A, the first contact region 30P1, and the third contact of the array substrate 30 in the vertical projection direction Z. The regions 30P3 overlap, but the second contact regions 30P2 are exposed to the opposite substrate 50, that is, the opposite substrate 50 does not overlap the second contact regions 30P2 in the vertical projection direction Z. Then, at least one driving wafer 68 is disposed in the second contact region 30P2 of the peripheral region 30P of the array substrate 30, wherein the driving wafer 68 is in contact with and electrically connected to the first connecting end 40X1 of the connecting trace 40 to form the implementation. For example, the display panel 100. As can be seen from the above, the driving signal provided by the driving chip 68 can be transmitted to the second connecting end 54X2 of the signal switching wire 54 on the opposite substrate 50 via the connecting wire 40 disposed on the second contact region 30P2 and the third contact region 30P3. The first connection end 51X1 of the signal switching wire 54 is further transmitted to the first signal line SL1 disposed on the active area 30A via the connection end X1 disposed at the first contact area 30P1. That is to say, the first contact region 30P1 of the peripheral region 30P of the array substrate 30 only needs to be provided with the connection end X1 and the second spacer 582 of the first signal line SL1, and it is not necessary to provide a plurality of connection traces, so that the connection area can be greatly reduced. The area of the peripheral area 30P effectively realizes a narrow bezel design. In addition, since the signal switching wire 54 is perpendicularly projected with the patterned light shielding layer 52 The direction Z overlaps, so the signal switching wire 54 can have a larger line width without affecting the aperture ratio to reduce resistance and energy consumption. For example, the signal switching wire 54 may have a line width of 5 micrometers to 6 micrometers, but is not limited thereto.

Please refer to Figure 8 again. Figure 8 is a cross-sectional view showing the sub-pixel of the embodiment. As shown in FIG. 8, the transparent conductive shielding layer 60 is located between the signal switching wire 54 and the display medium layer 66, and the transparent conductive shielding layer 60 may be floating or have a common voltage when displayed. The common voltage of the transparent conductive shielding layer 60 may be the same as or different from the common voltage of the common electrode CE. When the display is performed, the transparent conductive shielding layer 60 is disposed to shield the electric field generated by the driving voltage (for example, the gate electrode) transmitted from the signal switching wire 54. That is to say, if the transparent conductive shielding layer 60 is not provided, the electric field generated by the driving voltage transmitted by the signal switching wire 54 may affect the liquid crystal molecules in the display dielectric layer 66 to cause light leakage. The display panel 100 of the present embodiment shields the electric field generated by the signal switching wires 54 by the transparent conductive shielding layer 60, thereby avoiding the problem of light leakage.

Please refer to Figure 11 and refer to Figures 7 and 8. 11 is a simulation result of the transmittance of the display panel of the embodiment and the display panel of the comparative embodiment in combination with the negative liquid crystal in a dark state, wherein the vertical axis represents the transmittance, and the horizontal axis represents the sub-pixel. The position on one direction L1 (as shown in Figure 7). The curve A represents the display panel of the comparative embodiment (the signal-conducting wire is disposed on the opposite substrate but the transparent conductive shielding layer is not disposed), and the curve B represents the display panel of the embodiment (the signal-converting wire is disposed on the opposite substrate) A transparent conductive shielding layer in which the transparent conductive shielding layer has the same experimental result of a common voltage or a floating voltage). As shown in Fig. 11, in the dark state display, the display panel of the comparative embodiment has a significant light leakage problem, and the display panel of the present embodiment has no light leakage problem.

In summary, the display panel of the present invention utilizes the signal transfer wires disposed on the opposite substrate as the connection medium between the signal lines in the active area of the array substrate and the driving chips in the peripheral area. In this way, the number of connection traces in the peripheral area can be greatly reduced, so that the area of the peripheral area can be reduced to achieve a narrow bezel design. In addition, the display panel of the present invention can effectively shield the electric field generated when the signal transmission wire disposed on the opposite substrate transmits the signal by using the transparent conductive shielding layer disposed on the opposite substrate, thereby avoiding the light leakage problem.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧ display panel

30‧‧‧Array substrate

30A‧‧‧Active Area

T‧‧‧thin film transistor components

G‧‧‧ gate

GI‧‧‧ gate insulation

SE‧‧‧Semiconductor layer

S‧‧‧ source

D‧‧‧汲

34‧‧‧Protective layer

Z‧‧‧Vertical projection direction

PE‧‧‧ pixel electrode

CE‧‧‧Common electrode

36‧‧‧Dielectric layer

TH‧‧‧Contact hole

BE‧‧‧ branch electrode

ST‧‧‧slit

50‧‧‧ opposite substrate

52‧‧‧ patterned blackout layer

54‧‧‧Signal wire

56‧‧‧flat layer

581‧‧‧First spacer

60‧‧‧Transparent conductive shield

60G‧‧‧ gap

66‧‧‧Display media layer

Claims (22)

A display panel includes: an array substrate having an active area and a peripheral area; a pixel array disposed on the array substrate and located in the active area, wherein the pixel array includes a plurality of sub-pixels, and each The sub-pixel includes at least one thin film transistor element; a plurality of first signal lines are disposed on the array substrate and located in the active area, wherein the first signal lines extend along a first direction and The thin film transistor element is electrically connected; a plurality of second signal lines are disposed on the array substrate and located in the active area, wherein the second signal lines extend along a second direction and the thin film transistor elements Electrically connecting; a plurality of connecting wires are disposed on the array substrate and located in the peripheral region; a pair of substrates disposed opposite to the array substrate; a patterned light shielding layer disposed on the opposite substrate; The signal transmission wires are disposed on the opposite substrate, wherein the signal transmission wires are electrically connected to the first signal lines and electrically connected to the connection lines respectively; Conductive shield layer disposed on the pair corresponding to the active region of the array substrate onto the substrate; and a display medium layer disposed between the array substrate and the counter substrate. The display panel of claim 1, wherein the signal routing wires overlap the patterned light shielding layer in a vertical projection direction. The display panel of claim 1, wherein the first signal lines comprise a plurality of gate lines, and the second signal lines comprise a plurality of data lines. The display panel of claim 1, wherein the peripheral area comprises a first contact area on at least one side of the active area, a second contact area on the other side of the active area, and a third contact area Located between the active area and the second contact area, the opposite substrate overlaps the active area, the first contact area, and the third contact area of the array substrate in a vertical projection direction, and the opposite direction The substrate exposes the second contact region. The display panel of claim 4, wherein each of the first signal lines has a connection end extending into the first contact area. The display panel of claim 5, wherein each of the connection traces has a first connection end located in the second contact area, and a second connection end is located in the third contact area. The display panel of claim 6, further comprising at least one driving chip disposed on the array substrate and located in the second contact region of the peripheral region, wherein the at least one driving chip is connected to the connecting wires The first connecting ends are electrically connected. The display panel of claim 6, wherein each of the signal switching wires has a first connecting end corresponding to the first contact area, and a second connecting end corresponding to the third contact area. The display panel of claim 8, further comprising: a plurality of first spacers disposed on the opposite substrate and corresponding to the active region of the array substrate, wherein the transparent conductive shielding layer has a plurality of notches, respectively Exposing the first spacers; a plurality of second spacers disposed on the opposite substrate and corresponding to the first contact region of the peripheral region of the array substrate; and a plurality of third spacers disposed on The opposite substrate and corresponding to the third contact region of the peripheral region of the array substrate. The display panel of claim 9, further comprising: a plurality of first transparent connecting pads disposed on the opposite substrate and covering the surfaces of the second spacers, wherein the first transparent connecting pads are respectively connected to the first connecting ends of the signal routing wires And electrically connecting the connection ends of the first signal lines; and a plurality of second transparent connection pads disposed on the opposite substrate and respectively covering surfaces of the third spacers, wherein the second transparent connections The second connection ends of the pads and the signal connection wires are electrically connected to the second connection ends of the connection wires. The display panel of claim 10, wherein the transparent conductive shielding layer, the first transparent connecting pads and the second transparent connecting pads are the same layer of patterned transparent conductive layer. The display panel of claim 1, wherein each of the pixels further comprises: a pixel electrode disposed on the array substrate; and a common electrode disposed on the array substrate and electrically connected to the pixel electrode isolation. The display panel of claim 12, wherein each of the thin film transistor elements comprises: a gate disposed on the array substrate; a semiconductor layer disposed on the gate; and a gate insulating layer disposed on the gate Between the pole and the semiconductor layer; a source disposed on the semiconductor layer and corresponding to one side of the gate; a drain disposed on the semiconductor layer and corresponding to the other side of the gate; A protective layer is disposed on the gate insulating layer, the protective layer has a contact hole, and the pixel electrode contacts the drain through the contact hole. The display panel of claim 1, wherein the transparent conductive shielding layer is floating or has a common voltage. The display panel of claim 1, wherein the display medium layer comprises a liquid crystal layer, and the liquid crystal layer comprises a positive liquid crystal layer or a negative liquid crystal layer. A method for fabricating a display panel, comprising: providing an array substrate, the array substrate having an active region and a peripheral region; forming a pixel array in the active region on the array substrate, wherein the pixel array comprises a plurality of pixels a pixel, and each of the pixels includes at least one thin film transistor component; a plurality of first signal lines and a plurality of second signal lines are formed in the active region on the array substrate, wherein the first signal lines and The second signal lines are electrically connected to the thin film transistor elements; a plurality of connection traces are formed in the peripheral region of the array substrate; a pair of substrates are provided; and a pattern is formed on the opposite substrate a light shielding layer; forming a plurality of signal routing wires on the opposite substrate; forming a transparent conductive shielding layer on the opposite substrate; bonding the opposite substrate and the array substrate, and respectively connecting the signal routing wires The first signal lines are electrically connected to each other and electrically connected to the connection lines; and a display medium layer is formed between the array substrate and the opposite substrate. The method of fabricating a display panel of claim 16, wherein the signal routing wires overlap the patterned light shielding layer in a vertical projection direction. The method for fabricating a display panel according to claim 17, further comprising: setting a plurality of first spacers on the opposite substrate, corresponding to the active region of the array substrate, wherein the transparent conductive shielding layer has a plurality of gaps Exposing the first spacers separately; A plurality of second spacers and a plurality of third spacers are disposed on the opposite substrate, corresponding to the peripheral region of the array substrate. The method of manufacturing a display panel according to claim 18, further comprising: forming a plurality of first transparent connection pads on the opposite substrate, respectively covering surfaces of the second spacers, wherein the first transparent connection pads And electrically connecting the signal routing wires to the first signal lines; and forming a plurality of second transparent connection pads on the opposite substrate, respectively covering the surfaces of the third spacers, wherein the first The two transparent connecting pads are electrically connected to the signal routing wires and the connecting wires respectively. The method of manufacturing a display panel according to claim 19, wherein the transparent conductive shielding layer, the first transparent connecting pads, and the second transparent connecting pads are the same layer of patterned transparent conductive layers. The method of fabricating a display panel of claim 16, further comprising: providing at least one driving wafer on the peripheral region of the array substrate, wherein the at least one driving wafer is electrically connected to the connecting traces The first signal line is electrically connected to the signal connecting wires and the signal switching wires. The method of manufacturing a display panel according to claim 21, wherein the first signal lines comprise a plurality of gate lines, and the second signal lines comprise a plurality of data lines.