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TWI501378B - 積層型半導體裝置及其製造方法 - Google Patents

積層型半導體裝置及其製造方法 Download PDF

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Publication number
TWI501378B
TWI501378B TW102106791A TW102106791A TWI501378B TW I501378 B TWI501378 B TW I501378B TW 102106791 A TW102106791 A TW 102106791A TW 102106791 A TW102106791 A TW 102106791A TW I501378 B TWI501378 B TW I501378B
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TW
Taiwan
Prior art keywords
semiconductor wafer
thickness
semiconductor
layer
adhesive layer
Prior art date
Application number
TW102106791A
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English (en)
Other versions
TW201411806A (zh
Inventor
Akira Tanimoto
Takashi Imoto
Yoriyasu Ando
Masashi Noda
Naoki Iwamasa
Koichi Miyashita
Masatoshi Kawato
Masaji Iwamoto
Jun Tanaka
Yusuke Dohmae
Original Assignee
Toshiba Kk
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Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW201411806A publication Critical patent/TW201411806A/zh
Application granted granted Critical
Publication of TWI501378B publication Critical patent/TWI501378B/zh

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    • H—ELECTRICITY
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Description

積層型半導體裝置及其製造方法 [相關申請案]
本申請案享有以日本專利申請案2012-198367號(申請日：2012年9月10日)為基礎申請案之優先權。本申請案藉由參考該基礎申請案而包含基礎申請案之所有內容。
本發明之實施形態係關於一種積層型半導體裝置及其製造方法。
為了實現半導體裝置之小型化、高速化、高功能化等，而使於1個封裝體內積層複數片半導體晶片而進行密封之SiP(System in Package，系統級封裝)構造之半導體裝置實用化。SiP構造之半導體裝置例如包含配線基板、搭載於配線基板上之記憶體晶片或控制器晶片等半導體晶片、及將該等半導體晶片總括地密封之密封樹脂層。外形小於記憶體晶片之控制器晶片等系統LSI(Large Scale Integration，大型積體電路)晶片一般係配置於多段地積層記憶體晶片而成之晶片積層體上。於此情形時，配線基板至系統LSI晶片之配線長度變長，故而有信號傳輸速度降低等擔憂。
針對此種方面，提出將系統LSI晶片嵌入至使記憶體晶片接著於配線基板之接著劑層內。根據此種構造，可實現半導體裝置之小型 化，並且可縮短配線基板至系統LSI晶片之配線長度。因此，可提供小型且應對高速裝置之半導體裝置。然而，於將系統LSI晶片嵌入至記憶體晶片之接著劑層時，擔心會產生各種不良情況。例如，有如下之虞：於將系統LSI晶片嵌入至接著劑層內時記憶體晶片變形為凸狀，或者因系統LSI晶片之嵌入不足而導致產生空隙。記憶體晶片之變形成為動作不良之原因。又，產生於系統LSI晶片周圍之空隙成為裂痕等之產生原因。
本發明所欲解決之問題在於提供一種可消除於半導體晶片之接著劑層內嵌入較其小型之半導體晶片時所產生之缺點之積層型半導體裝置及其製造方法。
實施形態之積層型半導體裝置包含：電路基板；第1半導體晶片，其配置於電路基板上；接著層，其使第1半導體晶片固著於電路基板；第2半導體晶片，其至少一部分被嵌入至接著層內，且具有小於第1半導體晶片之外形；第1連接構件，其電性連接電路基板與第1半導體晶片；第2連接構件，其電性連接電路基板與第2半導體晶片；及密封樹脂層，其以將第1及第2半導體晶片與第1及第2連接構件一併密封之方式設置於電路基板上。第2半導體晶片具有75 μm以下之厚度。接著層具有95 μm以上且150 μm以下之範圍之厚度，且含有嵌入第2半導體晶片時之熱時黏度為500 Pa．s以上且5000 Pa．s以下之範圍之熱固性樹脂。
1‧‧‧積層型半導體裝置
2‧‧‧配線基板
2a‧‧‧配線基板2之第1面
2b‧‧‧配線基板2之第2面
3‧‧‧外部電極
4‧‧‧外部端子
5‧‧‧內部電極
6、6A~6D‧‧‧第1半導體晶片
7‧‧‧第1接著層
8A~8C‧‧‧第2接著層
9‧‧‧第1接合線
10‧‧‧第2半導體晶片
11‧‧‧第3接著層
12‧‧‧第2接合線
13‧‧‧密封樹脂層
14‧‧‧接著劑層
15A~15C‧‧‧接著劑層
21‧‧‧半導體晶圓
22‧‧‧接著劑層
23‧‧‧切割保護膠帶
24‧‧‧第1刀片
25‧‧‧第2刀片
D‧‧‧切割區域
T‧‧‧厚度
t1‧‧‧厚度
t2‧‧‧厚度
X‧‧‧元件區域
圖1係表示實施形態之積層型半導體裝置之剖面圖。
圖2係表示圖1所示之積層型半導體裝置之第1變化例之剖面圖。
圖3係表示圖1所示之積層型半導體裝置之第2變化例之剖面圖。
圖4(a)、(b)係基於第1半導體晶片上之密封樹脂層之厚度而表示實施形態之積層型半導體裝置之溫度與翹曲量之關係的圖。
圖5(a)~(d)係表示圖1所示之積層型半導體裝置之製造方法之剖面圖。
圖6(a)、(b)係表示圖5所示之積層型半導體裝置之製造方法中所使用之第1半導體晶片之製作步驟的剖面圖。
圖7係表示圖6所示之第1半導體晶片之製作步驟中之第1刀片之晶圓切割剩餘量與刀片磨耗量及拾取不良率之關係的圖。
以下，參照圖式對實施形態之積層型半導體裝置及其製造方法進行說明。圖1係表示實施形態之積層型半導體裝置之剖面圖。圖1所示之積層型半導體裝置1包含配線基板2作為電路基板。配線基板2例如係於絕緣樹脂基板或陶瓷基板等之表面或內部設置配線網(未圖示)而成者，具體而言可列舉使用如玻璃環氧樹脂之絕緣樹脂之印刷配線板。作為電路基板，亦可使用矽中介層(Silicon Interposer)等代替配線基板(插入式基板)2。配線基板2具有成為外部端子之形成面之第1面2a、及成為半導體晶片之搭載面之第2面2b。
配線基板2之第1面2a具有外部電極3。於外部電極3上形成有外部端子4。於將積層型半導體裝置1用作BGA(Ball Grid Array，球狀柵格陣列)封裝體之情形時，外部端子4包含使用焊料球或焊料鍍敷等之突起端子。於將積層型半導體裝置1用作LGA(Land Grid Array，平台柵格陣列)封裝體之情形時，應用使用有Au鍍敷等之金屬焊墊作為外部端子4。成為半導體晶片之搭載面之配線基板2之第2面2b具有內部電極5。內部電極5之至少一部分經由配線基板2之配線網及外部電極3與外部端子4電性連接。
於配線基板2之第2面2b上配置有複數片第1半導體晶片6(6A~6D)。第1半導體晶片6A~6D係以露出各自之電極墊之方式呈階梯狀積層。作為第1半導體晶片6之具體例，可列舉如NAND(Not-AND，與非)型快閃記憶體之半導體記憶體晶片，但並不限定於此。圖1表示積層4個第1半導體晶片6A~6D而成之構造，但第1半導體晶片6相對於配線基板2之搭載數並不限定於此。第1半導體晶片6之搭載數為1個或複數個均可。複數片第1半導體晶片6之厚度視其製造步驟等而有所不同，例如設為90 μm以上。又，亦可根據配置位置而應用不同厚度之半導體晶片6。
複數片第1半導體晶片6A~6D之中，位於最下段之第1半導體晶片6A係經由第1接著層7而固著於配線基板2之第2面2b。第1接著層7介存於配線基板2之第2面2b與第1半導體晶片6A之間，且接著於配線基板2之第2面2b。於位於最下段之第1半導體晶片6A上，經由第2接著層8A~8C依序接著有第2段至第4段之第1半導體晶片6B~6D。第1半導體晶片6A~6D之電極墊係藉由使其等呈階梯狀錯開積層而分別朝向上方露出。
第1半導體晶片6A~6D之電極墊係經由第1接合線9而與配線基板2之內部電極5電性連接。關於電氣特性或信號特性相等之電極墊，能以第1接合線9將配線基板2之內部電極5與第1半導體晶片6A~6D之電極墊依序連接。作為第1接合線9，可使用一般之Au線或Cu線等金屬線。關於下述第2接合線亦相同。第1接合線9係作為電性連接第1半導體晶片6A~6D之電極墊與配線基板2之內部電極5的第1連接構件而發揮功能者。
第1連接構件並不限定於接合線，亦可為藉由噴墨印刷等而形成之配線層(導體層)等。又，複數片第1半導體晶片6間之電性連接亦可經由設置於第1半導體晶片6之內部之貫通電極及凸塊電極而進行。於 此情形時，經由貫通電極及凸塊電極將複數片第1半導體晶片6間機械性及電性連接。進而，經由接合線將任一第1半導體晶片6、例如位於最上段之第1半導體晶片6與配線基板2之內部電極5電性連接。
於配線基板2之第2面2b上，以位於第1半導體晶片6之下側之方式進而配置有第2半導體晶片10，該第2半導體晶片10具有小於第1半導體晶片6之外形(尺寸)。即，第2半導體晶片10係經由第3接著層11而接著於配線基板2之第2面2b，進而嵌入至使位於最下段之第1半導體晶片6A固著於配線基板2之第1接著層7內。第2半導體晶片10之電極墊係經由第2接合線12而與配線基板2之內部電極5電性連接。電性連接第2半導體晶片10與配線基板2之第2連接構件並不限定於接合線12，亦可為凸塊電極等。
作為第2半導體晶片10，可列舉於作為第1半導體晶片6之記憶體晶片與外部機器之間收發數位信號之控制器晶片或介面晶片、邏輯晶片、RF(Radio Frequency，射頻)晶片等系統LSI晶片，但並不限定於此。藉由將第2半導體晶片直接搭載於配線基板2之第2面2b上，可縮短系統LSI晶片等之第2半導體晶片10至配線基板2之配線長度，又，可使基板配線最佳化。藉由其等，可實現積層型半導體裝置1之高速化應對。進而，由於第2半導體晶片10係嵌入至第1接著層7內，故而亦不會降低第1半導體晶片6A~6D相對於配線基板2之搭載性、或者妨礙裝置尺寸之小型化等。因此，可提供小型且應對高速裝置之積層型半導體裝置1。
於配線基板2之第2面2b上，以將第1半導體晶片6或第2半導體晶片10與接合線9、12一併密封之方式，例如模鑄成形(mold forming)有使用環氧樹脂等絕緣樹脂之密封樹脂層13。由該等構成要素構成實施形態之積層型半導體裝置1。再者，圖1表示將第2半導體晶片10之整體嵌入至第1接著層7內之構造，但第2半導體晶片10之向第1接著層7 內之嵌入構造並不限定於此。如圖2所示，亦可應用將第2半導體晶片10之一部分嵌入至第1接著層7內之構造。藉此，亦可實現配線長度之縮短或裝置尺寸之小型化等。第2半導體晶片10只要其至少一部分嵌入至第1接著層7內即可。
第2半導體晶片10並不限定於直接配置於配線基板2之第2面2b上之構造，亦可在第2半導體晶片10至配線基板2之配線長度不會對信號傳輸速度造成不良影響之範圍內配置於其他半導體晶片上。圖3表示於配線基板2之第2面2b上配置第1段之第1半導體晶片6A，並於其上配置第2半導體晶片10而成之構造。第2半導體晶片10係嵌入至使第2段之第1半導體晶片6B固著於配線基板2之接著層7內。第2半導體晶片10只要嵌入至使第1半導體晶片6固著於配線基板2之接著層7內即可，並不限定於將第1半導體晶片6直接接著於配線基板2之接著層7，亦可嵌入至將第1半導體晶片6介隔其他半導體晶片而接著於配線基板2之接著層7內。
於將第2半導體晶片10嵌入至接著層7內時，第2半導體晶片10具有75 μm以下之厚度。若第2半導體晶片10之厚度超過75 μm，則即便對構成接著層7之接著劑之特性等進行改良，亦無法良好地將第2半導體晶片10嵌入至接著層7內。第2半導體晶片10之厚度之下限值並無特別限定，一般而言為20 μm以上。進而，為了良好地嵌入厚度為75 μm以下之第2半導體晶片10，接著層7具有95 μm以上之厚度。若接著層7之厚度未達95 μm，則電性連接第2半導體晶片10與配線基板2之接合線12會與第1半導體晶片6接觸，或者第2半導體晶片10與第1半導體晶片6之間之絕緣耐性等會降低。
換言之，藉由應用厚度為95 μm以上之接著層7，可一面維持第2半導體晶片10之動作或可靠性一面嵌入至接著層7內。於僅考慮將第2半導體晶片10嵌入至接著層7內之情形時，藉由使接著層7之厚度更 厚，而提高第2半導體晶片10之嵌入性。然而，若使接著層7之厚度過厚，則會妨礙積層型半導體裝置1之小型化或薄型化。因此，將接著層7之厚度設為150 μm以下。於實施形態之積層型半導體裝置1中，應用厚度為95 μm以上且150 μm以下之範圍之接著層7，藉此可提高第2半導體晶片10之嵌入性。
然而，若應用厚度厚至95 μm以上之接著層7，則根據將第2半導體晶片10嵌入至形成接著層7之接著劑內時之硬度等，有第1半導體晶片6以呈凸狀鼓起之方式發生變形、或者於第2半導體晶片10之周圍產生空隙之虞。因此，於本實施形態中，作為成為接著層7之形成材料之接著劑，應用嵌入第2半導體晶片10時之熱時黏度為500 Pa．s以上且5000 Pa．s以下之範圍之熱固性樹脂。此處，所謂熱時黏度係表示於對半硬化狀態之熱固性樹脂進行加熱時，發生軟化或熔融而表現接著性之溫度下之黏度。使熱固性樹脂軟化或熔融之溫度係由構成接著劑之熱固性樹脂之材料特性或接著劑層之形成條件、例如使液狀(A階段)之樹脂組合物成為半硬化狀態(B階段)時之乾燥溫度或乾燥時間等決定。
藉由使用熱時黏度為5000 Pa．s以下之熱固性樹脂之接著劑，可提高嵌入第2半導體晶片10時之接著劑之流動性。因此，由於接著劑於第2半導體晶片10之上部良好地流動並擴展，故而可抑制由接著劑之硬度引起之第1半導體晶片6之凸狀變形或基於其之動作不良之產生等。進而，由於接著劑良好地流動，故而接著劑充分地環繞第2半導體晶片10之周圍。因此，可抑制產生於第2半導體晶片10之周圍之空隙或因其而導致之裂痕等。然而，若接著劑之熱時黏度過低，則有第1半導體晶片6相對於電路基板2之平行性降低、或者無法維持第1半導體晶片6與第2半導體晶片10之間隔之虞，故而將接著劑之熱時黏度設為500 Pa．s以上。
作為接著劑所使用之熱固性樹脂，可列舉環氧樹脂、聚醯亞胺樹脂、丙烯酸系樹脂、酚樹脂等。作為接著劑，可與一般之熱固性接著劑同樣地使用包含硬化劑、硬化促進劑、無機填充材料、各種添加劑、溶劑等之熱固性樹脂組合物。藉由調整此種熱固性樹脂組合物中之黏度調整劑之種類或添加量、設為B階段時之乾燥條件、具有流動性之低分子成分之添加量等，而可將接著劑之熱時黏度設為500~5000 Pa．s之範圍。下述接著劑於加熱硬化時之流動黏度可藉由除上述成分調整或條件調整以外亦對熱固性樹脂組合物中之效果促進劑之添加量等進行調整而設為所需之範圍。接著層7包含此種接著劑之硬化物。
如此，藉由使用熱時黏度為500 Pa．s以上且5000 Pa．s以下之接著劑，而可提高第2半導體晶片10向接著劑層內之嵌入性。由此，可抑制因第2半導體晶片10之嵌入不足而引起之不良之產生。接著層7係藉由使熱時黏度為500~5000 Pa．s之熱固性樹脂硬化而形成者。因此，藉由包含熱時黏度為500~5000 Pa．s之範圍之熱固性樹脂之接著層7，可提供如下積層型半導體裝置1，其抑制因第2半導體晶片10向接著層7內之嵌入不足而引起之不良之產生，即抑制第1半導體晶片6之變形或接著層7之空隙之產生。
又，於應用厚度厚至95 μm以上之接著層7之情形時，於使積層型半導體裝置1自常溫(25℃)升溫至2次安裝溫度(例如270℃)時，積層型半導體裝置1之翹曲量容易增大。因此，於本實施形態之積層型半導體裝置1中，將第1半導體晶片6(具體而言為位於最上段之第1半導體晶片6D)上之密封樹脂層13之厚度設為190 μm以上。藉由將第1半導體晶片6上之密封樹脂層13之厚度設為190 μm以上，可抑制升溫時之積層型半導體裝置1之翹曲。又，由於即便密封樹脂層13之厚度過厚，升溫時之積層型半導體裝置1之翹曲亦會增大，故而第1半導體晶 片6上之密封樹脂層13之厚度係設為440 μm以下。
於圖4中基於第1半導體晶片6上之密封樹脂層13之厚度表示積層型半導體裝置1之溫度與翹曲量之關係。積層型半導體裝置1之翹曲量係依據JEITA(Japan Electronics & Information Technology Industries Association，日本電子信息技術產業協會)標準之「由升溫引起之封裝體之翹曲之測定方法及最大容許量(ED-7306)」而進行測定。積層型半導體裝置1之尺寸係設為12 mm×17 mm。第1半導體晶片6上之密封樹脂層13之厚度係定義為自密封樹脂層13之整個厚度去除第1接著層7之厚度、第1半導體晶片6A~6D之厚度及第2接著層8A~8C之厚度所得的厚度。如圖4所示，於嵌入有第2半導體晶片10之接著層7之厚度為95~150 μm之情形時，藉由將第1半導體晶片6上之密封樹脂層13之厚度設為190 μm以上且440 μm以下之範圍，而可將積層型半導體裝置1之翹曲量設為容許範圍之70 μm以下。
配線基板2之厚度或特性、密封樹脂層13之整個厚度或特性等亦會影響升溫時之積層型半導體裝置1之翹曲量。就此方面而言，配線基板2之厚度較佳為設為100~160 μm之範圍。密封樹脂層13之整個厚度亦取決於第1半導體晶片6之搭載數，但較佳為設為750~810 μm之範圍。進而，於將接著層7之熱膨脹係數設為70~470 ppm/℃，將常溫彈性模數(硬化後)設為2~3 GPa之情形時，配線基板2之核心材料之熱膨脹係數較佳為8~10 ppm/℃之範圍，常溫彈性模數較佳為30~40 GPa之範圍，密封樹脂層13之熱膨脹係數較佳為8~10 ppm/℃之範圍，常溫彈性模數(硬化後)較佳為1~30 GPa之範圍。藉由該等，而再現性良好地抑制升溫時之積層型半導體裝置1之翹曲。
實施形態之積層型半導體裝置1係例如藉由以下方式而製作。參考圖5對積層型半導體裝置1之製造步驟進行說明。如圖5(a)所示，於配線基板2之第2面2b上經由接著層11而接著第2半導體晶片10。對第2 半導體晶片10實施引線接合，而經由第2接合線12將配線基板2之內部電極5與第2半導體晶片10之電極墊電性連接。繼而，如圖5(b)所示，準備於背面(非電路面)形成有接著劑層14之第1半導體晶片6A。接著劑層14係將使用熱時黏度為500~5000 Pa．s之範圍之熱固性樹脂之接著劑形成為層狀而成者，且設為半硬化狀態。關於接著劑層14之形成方法等，將於下文所述。
雖於圖5(b)中省略了圖示，但電路基板2係載置於載台上，第1半導體晶片6A例如保持於吸附頭。第1半導體晶片6A及接著劑層14係例如藉由內置於吸附頭之加熱機構而加熱至特定溫度。電路基板2亦視需要藉由內置於載台之加熱機構而加熱。將加熱而軟化或熔融之接著劑層14壓抵於電路基板2之第2面2b。此時，接著劑層14係以取入第2半導體晶片10之方式壓合於電路基板2。如圖5(c)所示，第2半導體晶片10被嵌入至接著劑層14內。由於構成接著劑層14之接著劑之熱時黏度為500~5000 Pa．s之範圍，故而可將第2半導體晶片10良好地嵌入至接著劑層14內。
繼而，如圖5(d)所示，於第1半導體晶片6A上依序積層第1半導體晶片6B~6D。第1半導體晶片6B~6D係經由具有通常厚度(例如55 μm左右)之接著劑層(晶片黏接薄膜(DAF，Die Attach Film)或晶片黏接膏(DAP，Die Attach Paste))15A~15C而依序進行積層。此後，對接著劑層14、15A~15C進行固化處理以使接著劑層14、15A~15C具有充分之硬度。於使用熱固性樹脂之接著劑層14、15A~15C之固化處理中，接著劑係於暫時軟化或熔融而顯示流動性後進行硬化反應，藉此成為具有特定硬度之包含熱固性樹脂之接著層7、8A~8C。
此時，若接著劑層14、15A~15C於加熱硬化時之流動黏度、即軟化或熔融而顯示流動性時之黏度過低，則尤其接著劑層14之變形量會增大，由此第1半導體晶片6之翹曲量增加。第1半導體晶片6之翹曲 與上述凸狀變形同樣地成為動作不良等之產生原因。因此，於本實施形態中，對接著劑層14應用加熱硬化時之流動黏度為1000 Pa．s以上之接著劑。若接著劑之加熱硬化時之流動黏度為1000 Pa．s以上，則可抑制接著劑層14之變形，進而可抑制第1半導體晶片6之翹曲。於加熱硬化時接著劑顯示流動性之溫度範圍為例如60~120℃之範圍。
此後，對第1半導體晶片6A~6D實施引線接合，經由第1接合線9將配線基板2之內部電極5與第1半導體晶片6A~6D之電極墊電性連接。進而，藉由在配線基板2之第2面2b上形成將半導體晶片6、10與接合線9、12一併密封之密封樹脂層13，而製作實施形態之積層型半導體裝置1。於對第1半導體晶片6A~6D實施引線接合時，若厚度較厚之第1接著層7之硬化後之彈性模數過低，則接合線9相對於第1半導體晶片6A之連接性會降低。因此，第1接著層7之硬化後之彈性模數較佳為20 MPa以上。
由於在引線接合時通常亦施加有熱，故而第1接著層7之硬化後之彈性模數較佳為焊接時之溫度、例如220~260℃時之熱時彈性模數。藉由將第1接著層7之熱時彈性模數設為20 MPa以上，而可提高相對於第1半導體晶片6之引線接合性。第1接著層7之熱時彈性模數可藉由對例如上述熱固性樹脂組合物中之無機填充材料之含量等進行調整而設為20 MPa以上。
繼而，參考圖6對具有接著劑層14之第1半導體晶片6之製作步驟進行說明。如圖6(a)所示，於相當於第1半導體晶片6之具有複數個元件區域X之半導體晶圓21之背面(非電路面)貼附半硬化狀態之接著劑片材(晶片黏接薄膜等)，或者於利用噴墨法或滴塗法塗佈液狀之接著劑樹脂(晶片黏接膏等)後使其半硬化，藉此形成於單片化後成為第1半導體晶片6之接著劑層14之接著劑層22。接著劑層22具有95~150 μm之範圍之厚度。於接著劑層22上貼附切割保護膠帶23。即，於半 導體晶圓21之背面依序積層接著劑層22與切割保護膠帶23。
其次，藉由沿著設置於元件區域X間之切割區域D將半導體晶圓21與接著劑層22一併切斷，而製作經單片化之具有接著劑層14之第1半導體晶片6。半導體晶圓21之切斷係使用例如2軸構造之刀片切割裝置、即以安裝於2個旋轉軸上之2個刀片以相同軌跡行進之方式構成的刀片切割裝置而實施。先行之第1刀片24係僅切削半導體晶圓21之厚度T之一部分者，而利用後方之第2刀片25切斷半導體晶圓21之剩餘部分之厚度及接著劑層22之厚度整體。
如圖6(a)所示，以第1刀片24僅切削半導體晶圓21之厚度T之一部分。即，第1刀片24係僅切削半導體晶圓21之厚度t1者。於利用第1刀片24進行之切削步驟中，半導體晶圓21並未被完全切斷，其一部分(厚度t2之部分)以未切削狀態殘留。繼而，如圖6(b)所示，以第2刀片25將半導體晶圓21之剩餘部分之厚度t2及接著劑層22之厚度整體與切割保護膠帶23之一部分一併切削。對第2刀片25使用刀刃寬度窄於第1刀片24之刀片。
藉由以第1刀片24僅切削半導體晶圓21之一部分之厚度t1，以刀刃寬度較窄之第2刀片25將半導體晶圓21之剩餘部分之厚度t2與接著劑層22一併切削，而將半導體晶圓21與接著劑層22一併切斷而進行單片化。藉由應用此種切斷步驟(階段式切割)，而如圖6(b)所示般於半導體晶圓21之切斷面產生階差。藉此，碎屑之產生得到抑制。然而，若第2刀片25對半導體晶圓21之切削量不充分，則有厚度厚至95~150 μm之接著劑層22之切斷性降低之虞。若接著劑層22之切斷不充分，則於自切割保護膠帶23拾取單片化後之半導體晶片6時會產生不良。認為其原因在於：由於第2刀片25之磨耗量少，故而切削時附著之接著劑層22之切削屑過度殘留於第2刀片25上。
因此，於實施形態中，將以第2刀片25切削之半導體晶圓21之厚 度t2、換言之為以第1刀片24進行切削後之半導體晶圓21之剩餘部分之厚度t2設為85 μm以上。藉由將第2刀片25對半導體晶圓21之切削量設為85 μm以上，而使第2刀片25於半導體晶圓21中適度地磨耗，故而可提高厚度厚至95~150 μm之接著劑層22之切斷性。即，為了良好地切斷包含熱固性樹脂組合物之半硬化物之接著劑層22，必需使第2刀片25於半導體晶圓21中適度地磨耗。藉由將半導體晶圓21之剩餘部分之厚度t2設為85 μm以上，而使第2刀片25之磨耗量成為例如0.3 μm/m以上，從而提高接著劑層22之切斷性。
圖7係表示第1刀片24對半導體晶圓21之切割剩餘量與刀片磨耗量及拾取不良率之關係的圖。藉由將第1刀片24對半導體晶圓21之切割剩餘量(t2)設為85 μm以上，而使刀片磨耗量成為0.3 μm/m以上。藉此，可防止具有接著劑層14之半導體晶片6之拾取不良之產生。又，就獲得藉由階段式切割之碎屑之抑制效果之方面而言，第1刀片24對半導體晶圓21之切削量(t1)較佳為設為5 μm以上。因此，實施階段式切割之半導體晶圓21之厚度T較佳為90 μm以上，若考慮各公差等，則更佳為100 μm以上，進而較佳為110 μm以上。
此後，使用吸附夾頭等自切割保護膠帶拾取單片化後之第1半導體晶片6。於第1半導體晶片6之背面形成有經單片化之接著劑層14。由於接著劑層22可藉由上述階段式切割而確實地單片化，故而可抑制由接著劑層22之切斷不良引起之拾取不良之產生。進而，藉由應用階段式切割，可抑制碎屑之產生。即，可一面抑制碎屑之產生，一面抑制第1半導體晶片6之拾取不良之產生。具有接著劑層14之第1半導體晶片6係使用於圖5(b)所示之半導體晶片6A之接著步驟中，一面將第2半導體晶片10嵌入至接著劑層14內一面接著於電路基板2。
再者，已對本發明之若干個實施形態進行了說明，但該等實施形態係作為示例而提示者，並不意圖限定發明之範圍。該等實施形態 能夠以其他各種形態實施，且可於不脫離發明主旨之範圍內進行各種省略、替換、變更。該等實施形態及其變形包含於發明之範圍或主旨內，同時包含於申請專利範圍所記載之發明及其均等之範圍內。
1‧‧‧積層型半導體裝置
2‧‧‧配線基板
2a‧‧‧配線基板2之第1面
2b‧‧‧配線基板2之第2面
3‧‧‧外部電極
4‧‧‧外部端子
5‧‧‧內部電極
6A~6D‧‧‧第1半導體晶片
7‧‧‧第1接著層
8A~8C‧‧‧第2接著層
9‧‧‧第1接合線
10‧‧‧第2半導體晶片
11‧‧‧第3接著層
12‧‧‧第2接合線
13‧‧‧密封樹脂層

Claims (5)

  1. 一種積層型半導體裝置，其特徵在於包含：電路基板；第1半導體晶片，其配置於上述電路基板上；接著層，其使上述第1半導體晶片固著於上述電路基板；第2半導體晶片，其至少一部分被嵌入至上述接著層內，且具有小於上述第1半導體晶片之外形；第1連接構件，其電性連接上述電路基板與上述第1半導體晶片；第2連接構件，其電性連接上述電路基板與上述第2半導體晶片；及密封樹脂層，其以將上述第1及第2半導體晶片與上述第1及第2連接構件一併密封之方式設置於上述電路基板上；且上述第1半導體晶片具有90μm以上之厚度；上述第2半導體晶片具有75μm以下之厚度；上述接著層具有95μm以上且150μm以下之範圍之厚度，並且含有嵌入上述第2半導體晶片時之熱時黏度為500Pa．s以上且5000Pa．s以下之範圍之熱固性樹脂；上述第1半導體晶片上之上述密封樹脂層之厚度為190μm以上且440μm以下之範圍。
  2. 一種積層型半導體裝置，其特徵在於包含：電路基板；第1半導體晶片，其配置於上述電路基板上；接著層，其使上述第1半導體晶片固著於上述電路基板；第2半導體晶片，其至少一部分被嵌入至上述接著層內，且具 有小於上述第1半導體晶片之外形；第1連接構件，其電性連接上述電路基板與上述第1半導體晶片；第2連接構件，其電性連接上述電路基板與上述第2半導體晶片；及密封樹脂層，其以將上述第1及第2半導體晶片與上述第1及第2連接構件一併密封之方式設置於上述電路基板上；且上述第2半導體晶片具有75μm以下之厚度；上述接著層具有95μm以上且150μm以下之範圍之厚度，並且含有嵌入上述第2半導體晶片時之熱時黏度為500Pa．s以上且5000Pa．s以下之範圍之熱固性樹脂。
  3. 一種積層型半導體裝置之製造方法，其特徵在於包括以下步驟：準備電路基板；準備第1半導體晶片、及具有小於上述第1半導體晶片之外形之第2半導體晶片；於上述電路基板上搭載上述第2半導體晶片；經由第1連接構件電性連接上述電路基板與上述第2半導體晶片；將上述第2半導體晶片之至少一部分嵌入至接著劑內，並且利用上述接著劑使上述第1半導體晶片固著於上述電路基板；經由第2連接構件電性連接上述電路基板與上述第1半導體晶片；及於上述電路基板上形成將上述第1及第2半導體晶片與上述第1及第2連接構件一併密封之密封樹脂層；且上述第2半導體晶片具有75μm以下之厚度，且由上述接著劑 所形成之接著層具有95μm以上且150μm以下之範圍之厚度；將嵌入上述第2半導體晶片時之熱時黏度為500Pa．s以上且5000Pa．s以下之範圍之熱固性樹脂用作上述接著劑。
  4. 如請求項3之積層型半導體裝置之製造方法，其中上述接著劑係於嵌入上述第2半導體晶片後進行硬化處理；上述熱固性樹脂於加熱硬化時之流動黏度為1000Pa．s以上。
  5. 如請求項3或4之積層型半導體裝置之製造方法，其中準備上述第1半導體晶片之步驟包括以下步驟：於半導體晶圓之背面依序積層上述接著劑層與切割保護膠帶；使用第1刀片僅切削上述半導體晶圓之厚度之一部分；使用刀刃寬度較上述第1刀片窄之第2刀片切削上述半導體晶圓之剩餘部分之厚度與上述接著劑層之厚度整體，而形成包含上述接著劑層之上述第1半導體晶片；及自上述切割保護膠帶拾取包含上述接著劑層之上述第1半導體晶片；且以上述第1刀片進行切削後之上述半導體晶圓之剩餘部分之厚度為85μm以上。
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Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5870198B2 (ja) * 2012-09-14 2016-02-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2015099890A (ja) * 2013-11-20 2015-05-28 株式会社東芝 半導体装置、及び半導体パッケージ
US9967984B1 (en) 2015-01-14 2018-05-08 Vlt, Inc. Power adapter packaging
US10264664B1 (en) 2015-06-04 2019-04-16 Vlt, Inc. Method of electrically interconnecting circuit assemblies
JP6373811B2 (ja) * 2015-09-08 2018-08-15 東芝メモリ株式会社 半導体装置の製造方法および製造装置
US20200258750A1 (en) * 2017-08-17 2020-08-13 Semiconductor Components Industries, Llc Die support structures and related methods
FR3044864B1 (fr) * 2015-12-02 2018-01-12 Valeo Systemes De Controle Moteur Dispositif electrique et procede d'assemblage d'un tel dispositif electrique
JP6523999B2 (ja) * 2016-03-14 2019-06-05 東芝メモリ株式会社 半導体装置およびその製造方法
JP6524003B2 (ja) * 2016-03-17 2019-06-05 東芝メモリ株式会社 半導体装置
KR102012789B1 (ko) * 2016-03-28 2019-08-21 주식회사 엘지화학 반도체 장치
US10158357B1 (en) 2016-04-05 2018-12-18 Vlt, Inc. Method and apparatus for delivering power to semiconductors
US10903734B1 (en) 2016-04-05 2021-01-26 Vicor Corporation Delivering power to semiconductor loads
CN107768259B (zh) * 2016-08-18 2020-04-24 福州瑞芯微电子股份有限公司 一种芯片的双面封装结构及封装方法
JP6349540B2 (ja) * 2016-10-06 2018-07-04 株式会社新川 半導体チップの実装装置、および、半導体装置の製造方法
US10147705B2 (en) 2017-02-21 2018-12-04 Micron Technology, Inc. Stacked semiconductor die assemblies with die substrate extensions
JP7034706B2 (ja) * 2017-12-27 2022-03-14 キオクシア株式会社 半導体装置
KR102542628B1 (ko) 2018-02-05 2023-06-14 삼성전자주식회사 반도체 패키지
US10546845B2 (en) * 2018-04-20 2020-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package on package structure
WO2020013250A1 (ja) * 2018-07-11 2020-01-16 日立化成株式会社 半導体装置の製造方法、熱硬化性樹脂組成物及びダイシング・ダイボンディング一体型フィルム
JP7042713B2 (ja) 2018-07-12 2022-03-28 キオクシア株式会社 半導体装置
JP2020021908A (ja) * 2018-08-03 2020-02-06 キオクシア株式会社 半導体装置およびその製造方法
JP2020025022A (ja) * 2018-08-07 2020-02-13 キオクシア株式会社 半導体装置およびその製造方法
JP2020043258A (ja) * 2018-09-12 2020-03-19 キオクシア株式会社 半導体メモリおよびその製造方法
JP2020047652A (ja) 2018-09-14 2020-03-26 キオクシア株式会社 半導体記憶装置及び電子機器
JP2020053655A (ja) * 2018-09-28 2020-04-02 キオクシア株式会社 半導体装置及び半導体装置の製造方法
EP3834227B1 (en) * 2018-10-30 2024-09-04 Yangtze Memory Technologies Co., Ltd. Ic package
JP2022513730A (ja) 2018-12-07 2022-02-09 長江存儲科技有限責任公司 新規の３ｄ ｎａｎｄメモリデバイスおよびそれを形成する方法
JP2020150146A (ja) * 2019-03-14 2020-09-17 キオクシア株式会社 半導体装置
JP2020155559A (ja) 2019-03-19 2020-09-24 キオクシア株式会社 半導体装置
JP7242366B2 (ja) * 2019-03-22 2023-03-20 キオクシア株式会社 半導体装置
JP2021015922A (ja) * 2019-07-16 2021-02-12 キオクシア株式会社 半導体装置およびその製造方法
US11424212B2 (en) * 2019-07-17 2022-08-23 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
JP7293056B2 (ja) * 2019-09-12 2023-06-19 キオクシア株式会社 半導体装置およびその製造方法
JP7427480B2 (ja) 2020-03-09 2024-02-05 キオクシア株式会社 半導体装置
JPWO2022004849A1 (zh) * 2020-07-03 2022-01-06
US20230326887A1 (en) * 2022-04-11 2023-10-12 Western Digital Technologies, Inc. Clamped semiconductor wafers and semiconductor devices

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060267173A1 (en) * 2005-05-26 2006-11-30 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
TW200739755A (en) * 2006-03-16 2007-10-16 Toshiba Kk Manufacturing method of semiconductor device
US20070246842A1 (en) * 2006-04-20 2007-10-25 Shinko Electric Industries Co., Ltd. Semiconductor device, electronic apparatus and semiconductor device fabricating method
TW201225189A (en) * 2010-12-10 2012-06-16 Toshiba Kk Method of manufacturing semiconductor device, manufacturing program, and manufacturing apparatus
TW201230286A (en) * 2010-12-17 2012-07-16 Toshiba Kk Semiconductor device and method for manufacturing same
US20120223441A1 (en) * 2011-03-04 2012-09-06 Kabushiki Kaisha Toshiba Stacked semiconductor device and manufacturing method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4188337B2 (ja) * 2004-05-20 2008-11-26 株式会社東芝 積層型電子部品の製造方法
JP4881044B2 (ja) 2006-03-16 2012-02-22 株式会社東芝 積層型半導体装置の製造方法
JP2007324443A (ja) 2006-06-02 2007-12-13 Toshiba Corp 積層型半導体装置とその製造方法
JP2009016420A (ja) * 2007-07-02 2009-01-22 Renesas Technology Corp 半導体装置の製造方法
JP2010118554A (ja) * 2008-11-13 2010-05-27 Nec Electronics Corp 半導体装置およびその製造方法
JP2011135034A (ja) * 2009-11-25 2011-07-07 Sumitomo Bakelite Co Ltd 半導体パッケージおよび半導体装置
JP2013062328A (ja) * 2011-09-12 2013-04-04 Toshiba Corp 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060267173A1 (en) * 2005-05-26 2006-11-30 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
TW200739755A (en) * 2006-03-16 2007-10-16 Toshiba Kk Manufacturing method of semiconductor device
US20070246842A1 (en) * 2006-04-20 2007-10-25 Shinko Electric Industries Co., Ltd. Semiconductor device, electronic apparatus and semiconductor device fabricating method
TW201225189A (en) * 2010-12-10 2012-06-16 Toshiba Kk Method of manufacturing semiconductor device, manufacturing program, and manufacturing apparatus
TW201230286A (en) * 2010-12-17 2012-07-16 Toshiba Kk Semiconductor device and method for manufacturing same
US20120223441A1 (en) * 2011-03-04 2012-09-06 Kabushiki Kaisha Toshiba Stacked semiconductor device and manufacturing method thereof

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