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TWI552282B - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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Publication number
TWI552282B
TWI552282B TW103138012A TW103138012A TWI552282B TW I552282 B TWI552282 B TW I552282B TW 103138012 A TW103138012 A TW 103138012A TW 103138012 A TW103138012 A TW 103138012A TW I552282 B TWI552282 B TW I552282B
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Taiwan
Prior art keywords
layer
semiconductor wafer
resist layer
build
patterned resist
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TW103138012A
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English (en)
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TW201618247A (zh
Inventor
陳彥亨
林畯棠
紀傑元
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矽品精密工業股份有限公司
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Priority to TW103138012A priority Critical patent/TWI552282B/zh
Priority to CN201410673285.5A priority patent/CN105590918B/zh
Priority to US14/836,613 priority patent/US9842758B2/en
Publication of TW201618247A publication Critical patent/TW201618247A/zh
Application granted granted Critical
Publication of TWI552282B publication Critical patent/TWI552282B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

封裝結構及其製法
本發明係有關於一種半導體結構及其製法，尤指一種半導體封裝結構及其製法。
隨著電子產品逐漸朝微型化發展，印刷電路板(PCB)表面可供設置半導體封裝件的面積越來越小，因此遂發展出一種半導體封裝件之立體堆疊技術，其係於一半導體封裝件上疊置另一半導體封裝件，而成為一層疊式封裝結構(package on package,POP)，以符合高密度元件設置之要求。
請參閱第1圖，係為習知之層疊式封裝結構的剖視圖。主要在一晶片11周圍設置封膠層(molding compound)12，並在該晶片11的主動面設置增層線路層13與銲球14，以及在封膠層12中設置導通孔(Through package via,TPV)15，另進一步在晶片11的非主動面設置線路層16，以使該線路層16可透過導通孔15與增層線路層13電性連接。
然而，在前述導通孔製作時，是使用雷射鑽孔技術， 但由於該封膠層中填充有封膠粒子(compound filler)，所以在鑽孔後，因為該些封膠粒子的阻礙或破損，造成導通孔側壁粗糙度過粗，衍生後續線路電鍍困難及電性不連續等問題。相對地，如降低封膠粒子尺寸雖可改善鑽孔孔壁粗糙問題，但卻會造成封裝結構強度不足問題。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑒於上述習知技術之缺失，本發明係提供一種封裝結構之製法，係包括：提供第一載板，並將至少一半導體晶片以其主動面接置於該第一載板上；於該第一載板上形成一阻層，並圖案化該阻層；於該第一載板上形成一封膠層，並使該封膠層覆蓋該半導體晶片及該圖案化阻層；以及薄化該封膠層，以外露出該半導體晶片非主動面及圖案化阻層。藉以構成本發明之封裝結構。
後續復可在該封裝結構上進行增層線路製程，於該封膠層、半導體晶片非主動面及圖案化阻層上覆蓋第二載板；移除該第一載板，以外露出該半導體晶片主動面、圖案化阻層及封膠層；於該半導體晶片主動面、圖案化阻層及封膠層上形成第一增層線路層，並使該第一增層線路層電性連接至該半導體晶片主動面；於該第一增層線路層上覆蓋第三載板；移除該第二載板，以外露出該半導體晶片非主動面、圖案化阻層及封膠層；對應該圖案化阻層處鑽孔形成導通孔，以外露出第一增層線路層部分；於該半導 體晶片非主動面、圖案化阻層及封膠層上形成第二增層線路層，並於該圖案化阻層導通孔處形成導電通孔，以使該第二增層線路層透過該導電通孔電性連接至該第一增層線路層；以及移除該第三載板，並於該第一增層線路層上植設銲球。該阻層為感光之光阻層。
本發明復提供一種封裝結構，係包括：一封膠層；至少一半導體晶片，該半導體晶片具有相對之主動面及非主動面，且該半導體晶片係嵌埋於該封膠層中，並使該半導體晶片主動面及非主動面外露出該封膠層；以及一圖案化阻層，該圖案化阻層具有相對之第一表面及第二表面，且該圖案化阻層係嵌埋於該封膠層中，並使該圖案化阻層之第一表面及第二表面外露出該封膠層。
另外該封裝結構復可包括：第一增層線路層，該第一增層線路層係形成於該封膠層、半導體晶片主動面及圖案化阻層第一表面上，且該第一增層線路層係電性連接至該半導體晶片主動面；第二增層線路層，該第二增層線路層係形成於該封膠層、半導體晶片非主動面及圖案化阻層第二表面上，且該第二增層線路層係透過形成於該圖案化阻層中的導電通孔電性連接至該第一增層線路層；以及銲球，係設於該第一增層線路層上。
因此，本發明之封裝結構及其製法，係以阻層取代部分之封膠層，並在該阻層鑽孔形成導通孔，俾得較細緻的鑽孔效果，避免習知製程直接在封膠層鑽孔時，因封膠層中填充有封膠粒子所導致孔壁粗糙及衍生後續線路電鍍困 難及電性不連續等問題。
11‧‧‧晶片
12‧‧‧封膠層
13‧‧‧增層線路層
14‧‧‧銲球
15‧‧‧導通孔
16‧‧‧線路層
20a‧‧‧第一載板
20b‧‧‧第二載板
20c‧‧‧第三載板
200a‧‧‧第一離形層
200b‧‧‧第二離形層
200c‧‧‧第三離形層
21‧‧‧半導體晶片
21a‧‧‧主動面
21b‧‧‧非主動面
22‧‧‧封膠層
23‧‧‧第一增層線路層
24‧‧‧銲球
27‧‧‧阻層
271‧‧‧第一表面
272‧‧‧第二表面
27a‧‧‧導通孔
27b‧‧‧導電通孔
第1圖係為習知層疊式封裝結構之剖面示意圖；第2A至2K圖係為本發明之封裝結構及其製法示意圖；以及第2E’圖係為對應第2E圖之另一實施態樣示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「頂」及「底」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2K圖，係為本發明之封裝結構之製法示意圖。
如第2A圖所示，在一第一載板20a上設置第一離形 層200a，並於該第一離形層200a上接置至少一半導體晶片21，其中該半導體晶片21具有一相對之主動面21a及非主動面21b，且該半導體晶片21係以其主動面21a接置於該第一載板20a之第一離形層200a上；該第一離形層200a設置目的係為方便後續該半導體晶片21與該第一載板20a分離。
如第2B及2C圖所示，於該第一載板20a及半導體晶片21上覆蓋一阻層27，該阻層為一光阻層，並圖案化該阻層27，以使該圖案化阻層27形成有複數開口而外露出半導體晶片21及部分第一離形層200a。該阻層27例如為負型感光光阻層。
如第2D圖所示，於該第一載板20a上形成一封膠層22，並使該封膠層22覆蓋該半導體晶片21及該圖案化阻層27，藉以將該半導體晶片21及圖案化阻層27嵌埋於該封膠層22中。該封膠層中填充有封膠粒子，且該封膠粒子之顆粒尺寸需夠大以提供足夠結構強度。
如第2E圖所示，透過研磨或切割等方式薄化該封膠層22，以外露出該半導體晶片21非主動面21b及圖案化阻層27之第二表面272，其中該半導體晶片21非主動面21b、圖案化阻層27之第二表面272係與封膠層22表面齊平。
請參閱第2E’圖，之後即可移除該離形層200a及第一載板20a，以構成本發明之封裝結構。
因此，本發明之封裝結構係包括：一封膠層22；至少 一半導體晶片21，具有相對之主動面21a及非主動面21b，且該半導體晶片21係嵌埋於該封膠層22中，並使該半導體晶片21主動面21a及非主動面21b外露出該封膠層22；以及一圖案化阻層27，具有相對之第一表面271及第二表面272，且該圖案化阻層27係嵌埋於該封膠層22中，並使該圖案化阻層27之第一表面271及第二表面272外露出該封膠層22。
後續可在該封裝結構上進行增層線路製程。
如第2F圖所示，於該封膠層22、半導體晶片21非主動面21b及圖案化阻層27第二表面上覆蓋第二離形層200b及第二載板20b，並移除該第一載板20a及第一離形層200a，以外露出該半導體晶片21主動面21a、封膠層22、及圖案化阻層27之第一表面271。
如第2G圖所示，於該半導體晶片21主動面21a、圖案化阻層27第一表面271、及封膠層22上形成第一增層線路層23，並使該第一增層線路層23電性連接至該半導體晶片21主動面21a。
如第2H圖所示，於該第一增層線路層23上覆蓋第三離形層200c及第三載板20c，並移除該第二載板20b及第二離形層200b，以外露出該半導體晶片21非主動面21b、圖案化阻層27第二表面272、及封膠層22。
如第2I圖所示，對應該圖案化阻層27處利用例如雷射鑽孔技術形成導通孔27a，以外露出第一增層線路層23部分。
如第2J圖所示，於該半導體晶片21非主動面21b、圖案化阻層27第二表面272、及封膠層22上形成第二增層線路層26，並於該圖案化阻層27之導通孔處形成導電通孔27b，以使該第二增層線路層26透過該導電通孔27b電性連接至該第一增層線路層23。
如第2K圖所示，移除該第三載板20c及第三離形層200c，並於該第一增層線路層23上植設銲球24。
請參閱第2K圖，係為本發明之封裝結構另一實施態樣剖面示意圖。該封裝結構包括有：半導體晶片21、圖案化阻層27、封膠層22、第一增層線路層23、第二增層線路層26、導電通孔27b、及複數銲球24。
該半導體晶片21具有相對之主動面21a及非主動面21b，且該半導體晶片21係嵌埋於該封膠層22中，並使該半導體晶片21主動面21a及非主動面21b外露出該封膠層22。
該圖案化阻層27具有相對之第一表面271及第二表面272，且該圖案化阻層27係嵌埋於封膠層22中，並使該圖案化阻層27之第一表面271及第二表面272外露出該封膠層22。
該導電通孔27b係形成於該圖案化阻層27中，且貫穿該圖案化阻層27之第一表面271及第二表面272。
該第一增層線路層23係形成於該封膠層22、半導體晶片主動面21a、及圖案化阻層27第一表面271上，且該第一增層線路層23係電性連接至該半導體晶片21主動面 21a。
該第二增層線路層26係形成於該封膠層22、半導體晶片21非主動面21b、及圖案化阻層27第二表面272上，且該第二增層線路層26係透過形成於該圖案化阻層27中的導電通孔27b電性連接至該第一增層線路層23。
另於該第一增層線路層23上設有複數銲球24，以供封裝結構進行堆疊及電性連接。
透過前述說明可知，本發明之封裝結構及其製法，係以阻層取代部分之封膠層，並在該阻層鑽孔形成導通孔，俾得較細緻的鑽孔效果，避免習知製程直接在封膠層鑽孔時，因封膠層中填充有封膠粒子所導致孔壁粗糙及衍生後續線路電鍍困難及電性不連續等問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
21‧‧‧半導體晶片
21a‧‧‧主動面
21b‧‧‧非主動面
22‧‧‧封膠層
27‧‧‧阻層
271‧‧‧第一表面
272‧‧‧第二表面

Claims (17)

  1. 一種封裝結構之製法，係包括：將至少一半導體晶片以其主動面接置於一載板上；於該載板上形成一圖案化阻層；於該載板上形成一封膠層，使該封膠層覆蓋該半導體晶片及該圖案化阻層；薄化該封膠層，以外露出該半導體晶片相對於該主動面之非主動面及圖案化阻層；以及移除該載板；其中，該阻層為感光光阻層。
  2. 如申請專利範圍第1項所述之封裝結構之製法，其中，該載板上設有離形層。
  3. 如申請專利範圍第1項所述之封裝結構之製法，其中，該阻層為負型感光光阻層。
  4. 如申請專利範圍第1項所述之封裝結構之製法，其中，該封膠層中填充有封膠粒子。
  5. 一種封裝結構之製法，係包括：於一封膠層中嵌埋半導體晶片及圖案化阻層，並使該半導體晶片之相對之主動面及非主動面與該圖案化阻層之相對之第一表面及第二表面外露出該封膠層；形成第一增層線路層於該半導體晶片主動面、圖案化阻層第一表面及封膠層上，並使該第一增層線路層電性連接至該半導體晶片之主動面；自該圖案化阻層之第二表面鑽孔該圖案化阻層，以 形成複數外露出部分該第一增層線路層之導通孔；以及於該半導體晶片之非主動面、圖案化阻層之第二表面及封膠層上形成第二增層線路層，並於該導通孔處形成導電通孔，以使該第二增層線路層透過該導電通孔電性連接至該第一增層線路層；其中，該阻層為感光光阻層。
  6. 如申請專利範圍第5項所述之封裝結構之製法，復包括於該第一增層線路層上植設銲球。
  7. 如申請專利範圍第5項所述之封裝結構之製法，其中，該阻層為負型感光光阻層。
  8. 如申請專利範圍第5項所述之封裝結構之製法，其中，該封膠層中填充有封膠粒子。
  9. 一種封裝結構之製法，復包括：將一半導體晶片以其主動面接置於一第一載板上；於該第一載板上形成一圖案化阻層；於該第一載板上形成一封膠層，使該封膠層覆蓋該半導體晶片及該圖案化阻層；薄化該封膠層，以外露出該半導體晶片相對於該主動面之非主動面及圖案化阻層；於該封膠層、半導體晶片之非主動面及圖案化阻層上覆蓋一第二載板；移除該第一載板，以外露出該半導體晶片之主動面、圖案化阻層及封膠層；形成第一增層線路層於該半導體晶片之主動面、圖 案化阻層及封膠層上，並使該第一增層線路層電性連接至該半導體晶片之主動面；於該第一增層線路層上覆蓋一第三載板；移除該第二載板，以外露出該半導體晶片之非主動動面、圖案化阻層及封膠層；鑽孔該圖案化阻層，以形成複數外露出部分該第一增層線路層之導通孔；於該半導體晶片之非主動面、圖案化阻層及封膠層上形成第二增層線路層，並於該圖案化阻層導通孔處形成導電通孔，以使該第二增層線路層透過該導電通孔電性連接至該第一增層線路層；以及移除該第三載板，並於該第一增層線路層上植設銲球；其中，該阻層為感光光阻層。
  10. 如申請專利範圍第9項所述之封裝結構之製法，其中，該第一載板、第二載板及第三載板上設有離形層。
  11. 如申請專利範圍第9項所述之封裝結構之製法，其中，該阻層為負型感光光阻層。
  12. 如申請專利範圍第9項所述之封裝結構之製法，其中，該封膠層中填充有封膠粒子。
  13. 一種封裝結構，係包括：一封膠層；至少一半導體晶片，具有相對之主動面及非主動面，且該半導體晶片係嵌埋於該封膠層中，且其主動面 及非主動面外露出該封膠層；以及一圖案化阻層，具有相對之第一表面及第二表面，且該圖案化阻層係嵌埋於該封膠層中，該圖案化阻層之第一表面及第二表面並外露出該封膠層；其中，該阻層為感光光阻層。
  14. 如申請專利範圍第13項所述之封裝結構，復包括：導電通孔，係形成於該圖案化阻層中，且貫穿該圖案化阻層之第一表面及第二表面；第一增層線路層，係形成於該封膠層、半導體晶片主動面及圖案化阻層第一表面上，且該第一增層線路層係電性連接至該半導體晶片主動面；以及第二增層線路層，係形成於該封膠層、半導體晶片非主動面及圖案化阻層第二表面上，且該第二增層線路層係透過該導電通孔電性連接至該第一增層線路層。
  15. 如申請專利範圍第13項所述之封裝結構，復包括有銲球，係設於該第一增層線路層上。
  16. 如申請專利範圍第13項所述之封裝結構，其中，該阻層為負型感光光阻層。
  17. 如申請專利範圍第13項所述之封裝結構，其中，該封膠層中填充有封膠粒子。
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