TWI423742B - Printed wiring board with copper foil and the use of its layered body - Google Patents
Printed wiring board with copper foil and the use of its layered body Download PDFInfo
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- TWI423742B TWI423742B TW100110724A TW100110724A TWI423742B TW I423742 B TWI423742 B TW I423742B TW 100110724 A TW100110724 A TW 100110724A TW 100110724 A TW100110724 A TW 100110724A TW I423742 B TWI423742 B TW I423742B
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- copper foil
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- printed wiring
- wiring board
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
- B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C30/00—Coating with metallic material characterised only by the composition of the metallic material, i.e. not characterised by the coating process
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
- C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Metallurgy (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Organic Chemistry (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Chemical & Material Sciences (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- ing And Chemical Polishing (AREA)
- Laminated Bodies (AREA)
- Physical Vapour Deposition (AREA)
Description
本發明係有關於一種印刷配線板用銅箔及使用其之積層體,尤其係關於一種可撓性印刷配線板用銅箔及使用其之積層體。The present invention relates to a copper foil for a printed wiring board and a laminated body using the same, and more particularly to a copper foil for a flexible printed wiring board and a laminated body using the same.
印刷配線板歷於這半個世紀來發展快速,如今幾乎所有電子設備中均有使用。隨著近年來對電子設備之小型化、高性能化之需求增大,搭載零件之高密度構裝化及訊號之高頻化不斷進展,對印刷配線板要求導體圖案之微細化(細間距化(fine pitch))或高頻對應等。Printed wiring boards have developed rapidly over the past half century and are used today in almost all electronic devices. With the increase in the demand for miniaturization and high performance of electronic devices, the high-density mounting of components and the high-frequency of signals have been progressing, and the wiring pattern is required to be fine-grained (fine pitch). (fine pitch)) or high frequency correspondence.
印刷配線板通常係經下述步驟來製造:將絕緣基板接著於銅箔而製成積層體之後,藉由蝕刻於銅箔面形成導體圖案。因此,要求印刷配線板用銅箔具有良好的蝕刻性。The printed wiring board is usually manufactured by forming an insulating substrate on a copper foil to form a laminated body, and then etching a copper foil surface to form a conductor pattern. Therefore, copper foil for printed wiring boards is required to have good etching properties.
若不對銅箔之與樹脂不接著之面實施表面處理,則蝕刻後之銅箔電路的銅部分自銅箔表面朝下,亦即朝向樹脂層逐漸擴展地蝕刻(產生壓陷)。通常會成為電路側之面的角度較小的「壓陷」,尤其當產生較大的「壓陷」時,亦有於樹脂基板附近發生銅電路短路而成為不良品之情形。此處,第4圖係表示於形成銅電路時產生「壓陷」而在樹脂基板附近發生銅電路短路之一例的電路表面放大照片。If the surface of the copper foil and the resin are not surface-treated, the copper portion of the copper foil circuit after etching is etched from the surface of the copper foil, that is, gradually spread toward the resin layer (indentation is generated). In general, the "indentation" of the surface on the circuit side is small, and in particular, when a large "indentation" occurs, a copper circuit is short-circuited in the vicinity of the resin substrate to cause a defective product. Here, Fig. 4 is an enlarged photograph of a circuit surface which is an example of a case where a copper circuit is formed and a "crush" occurs in the vicinity of a resin substrate, and a copper circuit is short-circuited in the vicinity of a resin substrate.
必須極力地減少此種「壓陷」,但為了防止這種逐漸擴展之蝕刻不良,亦考慮有延長蝕刻時間,進行更多蝕刻,以減少該「壓陷」。但是,此時將存在下述問題:當存在已達特定寬度尺寸之部位時,則該部位將會被進一步蝕刻,故其銅箔部分的電路寬度會因而變窄,電路設計上無法獲得所要之均一的線寬度(電路寬度),尤其是該部分(被細線化之部分)會發熱,有時會發生斷線。於進一步推展電子電路之精細圖案化之過程中,目前因此種蝕刻不良而引起之問題更嚴重,於電路形成上成為較大問題。This "indentation" must be minimized, but in order to prevent such a gradual expansion of etching, it is also considered to extend the etching time and perform more etching to reduce the "indentation". However, at this time, there will be a problem that when there is a portion having a certain width dimension, the portion will be further etched, so that the circuit width of the copper foil portion is thus narrowed, and the circuit design cannot obtain the desired one. A uniform line width (circuit width), especially in this part (the thinned portion), generates heat and sometimes breaks. In the process of further engraving the fine patterning of electronic circuits, the problems caused by such poor etching are more serious, and it becomes a big problem in circuit formation.
在專利文獻1中揭示有改善上述問題之方法,係於蝕刻面側之銅箔形成蝕刻速度比銅慢的金屬或合金層之表面處理。此時之金屬或合金係Ni、Co及其等之合金。於設計電路時,由於蝕刻液係自抗蝕劑塗佈側,亦即自銅箔表面開始浸透,因此,若於抗蝕劑正下方具有蝕刻速度較慢的金屬或合金層,則可以抑制該金屬或合金層附近的銅箔部分之蝕刻,而其他銅箔部分之蝕刻仍進行,因此能得到「壓陷」減少且可形成寬度更為均一之電路之效果,與先前技術相比較可以形成較為陡峭之電路,可謂之具有較大進步。Patent Document 1 discloses a method for improving the above problem, in which a copper foil on the etching surface side is subjected to a surface treatment of a metal or alloy layer having an etching rate slower than that of copper. The metal or alloy at this time is an alloy of Ni, Co, and the like. When the circuit is designed, since the etching liquid is permeated from the resist coating side, that is, from the surface of the copper foil, if a metal or alloy layer having a slow etching rate is directly under the resist, the etching can be suppressed. The etching of the copper foil portion near the metal or alloy layer is performed, and the etching of the other copper foil portions is still performed, so that the effect of reducing the "indentation" and forming a circuit having a more uniform width can be obtained, which can be formed in comparison with the prior art. The steep circuit can be said to have made great progress.
又,於專利文獻2中,形成厚度為1000~10000之Cu薄膜,並於該Cu薄膜上形成厚度為10~300之蝕刻速度比銅慢之Ni薄膜。Further, in Patent Document 2, a thickness of 1000 to 10,000 is formed. Cu film, and formed on the Cu film to a thickness of 10 to 300 A Ni film that is slower to etch than copper.
專利文獻1:日本特開2002-176242號公報Patent Document 1: Japanese Laid-Open Patent Publication No. 2002-176242
專利文獻2:日本特開2000-269619號公報Patent Document 2: Japanese Laid-Open Patent Publication No. 2000-269619
近年來,進一步發展電路之微細化及高密度化,需要具有側面傾斜更為陡峭之電路。然而,專利文獻1所記載之技術並不能滿足該等要求。In recent years, in order to further develop the miniaturization and high density of circuits, it is necessary to have a circuit having a steeper side slope. However, the technique described in Patent Document 1 does not satisfy these requirements.
又,專利文獻1所揭示之表面處理層,須藉由軟蝕刻來除去,進而與樹脂之非接著面之表面處理銅箔在加工成積層體之步驟中,須實施樹脂黏貼等高溫處理。這將引起表面處理層氧化,結果導致銅箔蝕刻性劣化。Further, the surface treatment layer disclosed in Patent Document 1 is required to be removed by soft etching, and further, in the step of processing the surface-treated copper foil with the non-adhesive surface of the resin into a laminate, high-temperature treatment such as resin adhesion is required. This causes oxidation of the surface treatment layer, resulting in deterioration of the etching property of the copper foil.
關於前者,為了縮短除去蝕刻之時間,並較為乾淨地除去,必須極力使表面處理層的厚度較薄,並且於後者之情形下,因具有下述問題,故須加以改良或替換為其他材料,該問題係:基底的銅層因受熱而被氧化(由於會變色,因此通稱為「燒痕」),且抗蝕劑的塗佈性(均勻性、密合性)不良或於蝕刻時界面氧化物過度蝕刻等導致發生圖案蝕刻的蝕刻性、短路及電路圖案寬度之控制性等不良之問題。In the former, in order to shorten the time for removing the etching and to remove it relatively cleanly, it is necessary to make the thickness of the surface treatment layer as thin as possible, and in the latter case, it is necessary to improve or replace it with other materials because of the following problems. This problem is caused by the fact that the copper layer of the substrate is oxidized by heat (generally referred to as "burn marks" due to discoloration), and the coating property (uniformity, adhesion) of the resist is poor or the interface is oxidized at the time of etching. Excessive etching or the like causes problems such as etchability of pattern etching, short-circuiting, and controllability of circuit pattern width.
進而,專利文獻1和專利文獻2所揭示之表面處理層係使用Ni或Co來形成,然而這將帶來Ni或Co會因其磁性而對電子設備造成不良影響之擔憂。Further, the surface treatment layers disclosed in Patent Document 1 and Patent Document 2 are formed using Ni or Co, but this causes a concern that Ni or Co may adversely affect the electronic device due to its magnetic properties.
因此,本發明的課題在於提供一種於形成電路圖案時蝕刻性良好且適於細間距化、並且可良好地抑制磁性之印刷配線板用銅箔及使用其之積層體。In view of the above, it is an object of the present invention to provide a copper foil for a printed wiring board which is excellent in etchability when formed into a circuit pattern and which is suitable for fine pitch, and which can satisfactorily suppress magnetic properties, and a laminated body using the same.
本發明人等經潛心研究,結果發現在將包含鉑、鈀及金之任一種以上之被覆層,以特定之金屬附著量設置於銅箔之與樹脂不接著之面側之情形下,可形成電路側之面的傾斜角為80°以上之電路。藉此能夠形成可充分對應近年來之電路微細化及高密度化之電路。As a result of intensive studies, the present inventors have found that a coating layer containing at least one of platinum, palladium, and gold can be formed by providing a specific amount of metal adhesion on the side of the copper foil which is not adjacent to the resin. The circuit on the side of the circuit has an inclination angle of 80° or more. Thereby, it is possible to form a circuit that can sufficiently correspond to the miniaturization and high density of circuits in recent years.
在基於以上見解而完成之本發明於一個態樣中,係提供一種印刷配線板用銅箔,具備銅箔基材以及被覆層,該被覆層被覆銅箔基材表面的至少一部分,並且該被覆層包含鉑、鈀及金之任一種以上;並且,被覆層中的鉑附著量為1050μg/dm2 以下,鈀附著量為600μg/dm2 以下,金附著量為1000μg/dm2 以下。In one aspect of the present invention, which has been completed based on the above findings, there is provided a copper foil for a printed wiring board comprising a copper foil substrate and a coating layer covering at least a portion of a surface of the copper foil substrate, and the coating The layer contains at least one of platinum, palladium and gold, and the platinum adhesion amount in the coating layer is 1050 μg/dm 2 or less, the palladium adhesion amount is 600 μg/dm 2 or less, and the gold adhesion amount is 1000 μg/dm 2 or less.
於本發明之印刷配線板用銅箔的一實施方式中,係被覆層中的鉑附著量為20~400μg/dm2 ,鈀附著量為20~250μg/dm2 ,金附著量為20~400μg/dm2 。A printed wiring board according to the present invention with a copper foil embodiment, the coating weight of the platinum-based coating layer is 20 ~ 400μg / dm 2, a deposition amount of palladium 20 ~ 250μg / dm 2, the amount of adhesion of gold 20 ~ 400μg /dm 2 .
於本發明之印刷配線板用銅箔的另一實施方式中,係被覆層中的鉑附著量為50~300μg/dm2 ,鈀附著量為30~180μg/dm2 ,金附著量為50~300μg/dm2 。A printed wiring board according to the present invention of another embodiment of a copper foil, the adhesion amount of platinum-based coating layer is 50 ~ 300μg / dm 2, a deposition amount of palladium 30 ~ 180μg / dm 2, the amount of adhesion of 50 to gold 300 μg/dm 2 .
於本發明之印刷配線板用銅箔的又一實施方式中,係印刷配線板為可撓性印刷配線板。In still another embodiment of the copper foil for a printed wiring board of the present invention, the printed wiring board is a flexible printed wiring board.
於本發明的又一方面,提供一種電子電路之形成方法,包括下述步驟:準備由本發明銅箔所構成之壓延銅箔或電解銅箔之步驟;以銅箔的被覆層為蝕刻面,製作銅箔與樹脂基板之積層體之步驟;以及,利用氯化鐵水溶液或氯化銅水溶液對積層體進行蝕刻,除去不需要銅的部分來形成銅電路之步驟。According to still another aspect of the present invention, a method for forming an electronic circuit includes the steps of: preparing a rolled copper foil or an electrolytic copper foil composed of the copper foil of the present invention; and preparing the coated layer of the copper foil as an etched surface. a step of laminating a copper foil and a resin substrate; and a step of etching the layered body with an aqueous solution of ferric chloride or copper chloride to remove a portion not requiring copper to form a copper circuit.
於本發明的又一方面,提供一種積層體,係本發明的銅箔與樹脂基板之積層體。According to still another aspect of the present invention, a laminate comprising a laminate of a copper foil and a resin substrate of the present invention is provided.
於本發明的又一方面,提供一種積層體,係銅層與樹脂基板之積層體,其具備被覆銅層表面至少一部分之本發明的被覆層。According to still another aspect of the invention, there is provided a laminate comprising a laminate of a copper layer and a resin substrate, comprising a coating layer of the invention comprising at least a part of a surface of the copper layer.
於本發明積層體的一實施方式中,樹脂基板係聚醯亞胺基板。In one embodiment of the laminate of the present invention, the resin substrate is a polyimide substrate.
於本發明的又一方面,提供一種印刷配線板,其係以本發明積層體作為材料。In still another aspect of the invention, there is provided a printed wiring board using the laminate of the invention as a material.
根據本發明,可以提供一種在形成電路圖案時蝕刻性良好且適於細間距化、並且可良好地抑制磁性之印刷配線板用銅箔及使用其之積層體。According to the present invention, it is possible to provide a copper foil for a printed wiring board which is excellent in etchability and which is suitable for fine pitch and which can satisfactorily suppress magnetism when a circuit pattern is formed, and a laminate body using the same.
(銅箔基材)(copper foil substrate)
可用於本發明之銅箔基材的形態並無特別限制,典型而言可以壓延銅箔或電解銅箔之型態來使用。通常,電解銅箔係將銅自硫酸銅鍍浴電解析出至鈦或不鏽鋼的滾筒(drum)上銅而製造,壓延銅箔係反覆進行利用壓延輥之塑性加工和熱處理來製造。多將壓延銅箔用於要求彎曲性之用途。The form of the copper foil substrate which can be used in the present invention is not particularly limited, and it is typically used in the form of a rolled copper foil or an electrolytic copper foil. Usually, an electrolytic copper foil is produced by electrically analyzing copper from a copper sulfate plating bath to copper on a titanium or stainless steel drum, and the rolled copper foil is repeatedly produced by plastic working and heat treatment using a calender roll. Rolled copper foil is often used for applications requiring flexibility.
銅箔基材的材料,除了通常用作印刷配線板導體圖案之韌煉銅、無氧銅等高純度銅以外,例如亦可使用:摻雜Sn之銅、摻雜Ag之銅以及如添加有Cr、Zr或Mg等之銅合金、添加有Ni和Si等之卡遜系銅合金之類的銅合金。另外,於本說明書中,當單獨使用術語「銅箔」時,亦包含銅合金箔。As the material of the copper foil substrate, in addition to high-purity copper such as toughened copper or oxygen-free copper which is generally used as a conductor pattern of a printed wiring board, for example, copper doped with Sn, copper doped with Ag, and, if added, may be used. A copper alloy such as Cr, Zr or Mg, or a copper alloy to which a Cason copper alloy such as Ni or Si is added. In addition, in the present specification, when the term "copper foil" is used alone, a copper alloy foil is also included.
可用於本發明之銅箔基材的厚度亦並無特別限制,只要適度調節為適合用於印刷配線板之厚度即可。例如,可以為5~100μm左右。其中,於以形成精細圖案為目的之情形下為30μm以下,較佳為20μm以下,典型為5~20μm左右。The thickness of the copper foil substrate which can be used in the present invention is also not particularly limited as long as it is appropriately adjusted to be suitable for the thickness of the printed wiring board. For example, it may be about 5 to 100 μm. However, in the case of forming a fine pattern, it is 30 μm or less, preferably 20 μm or less, and typically about 5 to 20 μm.
用於本發明之銅箔基材並無特別限制,例如,亦可使用未經粗化處理之銅箔基材。先前,通常為如下情況:利用特殊鍍敷於表面附上μm級之凹凸,而實施表面粗化處理,藉由物理性的定準效應使銅箔基材具有與樹脂間之接著性,然而,另一方面,就細節距或高頻電氣特性而言,平滑之箔較好,而粗化箔會朝不利方向起發展。又,若為未經粗化處理之銅箔基材,則由於粗化處理步驟被省略而具有提高經濟性和生產性之效果。The copper foil substrate used in the present invention is not particularly limited, and for example, a copper foil substrate which has not been subjected to roughening treatment can also be used. In the past, it is generally the case that the surface roughening treatment is performed by attaching a special surface to the surface with a μm-order unevenness, and the copper foil substrate has a bond with the resin by a physical registration effect. On the other hand, in terms of fine pitch or high frequency electrical characteristics, a smooth foil is preferred, and a roughened foil develops in an unfavorable direction. Moreover, in the case of the copper foil base material which is not roughened, since the roughening process step is abbreviate|omitted, it has the effect of improving economics and productivity.
(被覆層的構成)(construction of the cover layer)
於銅箔基材之與絕緣基板接著之面的相反側(預定形成電路之面側)的表面至少一部分,形成有被覆層。被覆層包含鉑、鈀及金之任1種以上。於由鉑構成被覆層之情形下,鉑附著量為1050μg/dm2 以下,較佳為20~400μg/dm2 ,更佳為50~300μg/dm2 。於由鈀構成被覆層之情形下,鈀附著量為600μg/dm2 以下,較佳為20~250μg/dm2 ,更佳為30~180μg/dm2 。於由金構成被覆層之情形下,金附著量為1000μg/dm2 以下,較佳為20~400μg/dm2 ,更佳為50~300μg/dm2 。若被覆層的鉑附著量超過1050μg/dm2 、被覆層的鈀附著量超過600μg/dm2 以及被覆層的金附著量超過1000μg/dm2 ,將分別對初期蝕刻性造成不良影響。A coating layer is formed on at least a part of the surface of the copper foil substrate opposite to the surface on the subsequent surface of the insulating substrate (the side on which the circuit is to be formed). The coating layer contains at least one of platinum, palladium, and gold. In the case where the coating layer is composed of platinum, the platinum adhesion amount is 1050 μg/dm 2 or less, preferably 20 to 400 μg/dm 2 , and more preferably 50 to 300 μg/dm 2 . In the case where the coating layer is made of palladium, palladium deposition amount of 600μg / dm 2 or less, preferably 20 ~ 250μg / dm 2, more preferably 30 ~ 180μg / dm 2. In the case where the coating layer is composed of gold, the amount of gold adhered is 1000 μg/dm 2 or less, preferably 20 to 400 μg/dm 2 , and more preferably 50 to 300 μg/dm 2 . When the platinum adhesion amount of the coating layer exceeds 1050 μg/dm 2 , the palladium adhesion amount of the coating layer exceeds 600 μg/dm 2 , and the gold adhesion amount of the coating layer exceeds 1000 μg/dm 2 , the initial etching property is adversely affected.
(銅箔的製造方法)(Manufacturing method of copper foil)
本發明的印刷配線板用銅箔可藉由濺鍍法形成。亦即,藉由濺鍍法,利用被覆層來被覆銅箔基材表面的至少一部分。具體而言,係藉由濺鍍法,於銅箔的蝕刻面側形成被覆層,該被覆層係由選自由蝕刻速率比銅低之鉑族金屬、金及銀所構成之群中的一種所構成。被覆層並不限於藉由濺鍍法來形成,亦可利用例如電鍍、無電鍍等濕式鍍敷法而形成。The copper foil for a printed wiring board of the present invention can be formed by a sputtering method. That is, at least a part of the surface of the copper foil substrate is coated by the coating layer by a sputtering method. Specifically, a coating layer is formed on the etched surface side of the copper foil by a sputtering method, and the coating layer is one selected from the group consisting of a platinum group metal having a lower etching rate than copper, gold, and silver. Composition. The coating layer is not limited to being formed by a sputtering method, and may be formed by a wet plating method such as electroplating or electroless plating.
(印刷配線板的製造方法)(Manufacturing method of printed wiring board)
可使用本發明的銅箔根據常用方法來製造印刷配線板(PWB)。以下舉出印刷配線板的製造方法之例。A printed wiring board (PWB) can be manufactured according to a usual method using the copper foil of the present invention. An example of a method of manufacturing a printed wiring board is given below.
首先,貼合銅箔與絕緣基板來製造積層體。積層有銅箔之絕緣基板,只要具有適用於印刷配線板之特性,則並無特別限制,例如,用於剛性PWB時,可使用紙基材酚樹脂、紙基材環氧樹脂、合成纖維布基材環氧樹脂、玻璃布-紙複合基材環氧樹脂、玻璃布-玻璃不織布複合基材環氧樹脂及玻璃布基材環氧樹脂等,用於FPC時,可使用聚酯膜或聚醯亞胺膜等。First, a copper foil and an insulating substrate are bonded together to manufacture a laminated body. The insulating substrate in which the copper foil is laminated is not particularly limited as long as it has characteristics suitable for the printed wiring board. For example, when used for a rigid PWB, a paper substrate phenol resin, a paper substrate epoxy resin, a synthetic fiber cloth can be used. Substrate epoxy resin, glass cloth-paper composite substrate epoxy resin, glass cloth-glass non-woven composite substrate epoxy resin and glass cloth substrate epoxy resin, etc. For FPC, polyester film or poly醯 imine film and the like.
關於貼合之方法,在用於剛性PWB之情形下,準備以下之預浸體:將樹脂含浸於玻璃布等基材中,且使樹脂硬化至半硬化狀態為止。可將銅箔自被覆層的相反側之面重疊於預浸體,並進行加熱加壓,藉此進行貼合。Regarding the bonding method, in the case of using the rigid PWB, the following prepreg is prepared: the resin is impregnated into a substrate such as a glass cloth, and the resin is cured to a semi-hardened state. The surface of the copper foil from the opposite side of the coating layer may be superposed on the prepreg, and heated and pressed to bond the copper foil.
在用於可撓性印刷配線板(FPC)之情形下,可使用環氧系或丙烯酸系接著劑來將聚醯亞胺膜或聚酯膜與銅箔接著(3層結構)。又,不使用接著劑之方法(2層結構),可以列舉:澆鑄法,將作為聚醯亞胺之前驅物之聚醯亞胺清漆(聚醯胺酸(polyamic acid)清漆)塗佈於銅箔,並透過加熱而醯亞胺化;或積層法,於聚醯亞胺膜上塗佈熱塑性之聚醯亞胺,並於其上疊合銅箔,並進行加熱加壓。於澆鑄法中,在塗佈聚醯亞胺清漆之前,預先塗佈熱塑性聚醯亞胺等錨固塗層(anchor coat)材料亦極為有效。In the case of use in a flexible printed wiring board (FPC), an epoxy-based or acrylic-based adhesive may be used to bond the polyimide film or the polyester film to the copper foil (three-layer structure). Further, a method (two-layer structure) in which an adhesive is not used is exemplified by a casting method in which a polyimine varnish (polyamic acid varnish) which is a precursor of polyimine is applied to copper. The foil is imidized by heating; or the laminate method is applied to the polyimide film, and the thermoplastic polyimide is coated thereon, and the copper foil is laminated thereon and heated and pressurized. In the casting method, it is also extremely effective to apply an anchor coat material such as thermoplastic polyimide under the coating before the coating of the polyimide varnish.
本發明的積層體可用於各種印刷配線板(PWB),並無特別限制,例如,就導體圖案的層數之觀點而言,可應用於單面PWB、雙面PWB及多層PWB(3層以上),就絕緣基板材料的種類之觀點而言,可應用於剛性PWB、可撓性PWB(FPC)及剛性-可撓性PWB中。又,本發明的積層體,並不限定於將銅箔貼附於樹脂上而形成之上述覆銅積層板,亦可為利用濺鍍、鍍敷而於樹脂上形成銅層之金屬噴敷材料。The laminate of the present invention can be used for various printed wiring boards (PWB), and is not particularly limited. For example, from the viewpoint of the number of layers of the conductor pattern, it can be applied to single-sided PWB, double-sided PWB, and multilayer PWB (three or more layers). From the viewpoint of the type of the insulating substrate material, it can be applied to rigid PWB, flexible PWB (FPC), and rigid-flexible PWB. Moreover, the laminated body of the present invention is not limited to the copper-clad laminate formed by attaching a copper foil to a resin, and may be a metal spray material in which a copper layer is formed on a resin by sputtering or plating. .
將形成有下述結構之積層體浸漬於蝕刻液中,該結構係:在形成於以上述方法製作之積層體的銅箔上之被覆層表面塗佈抗蝕劑,且藉由遮罩曝光圖案,藉由顯影形成抗蝕劑圖案。此時,選自由抑制蝕刻之鉑族金屬、金及銀所構成之群中的1種所構成之被覆層,係位於銅箔上靠近抗蝕劑部分之位置,抗蝕劑側之銅箔之蝕刻,係以比該被覆層附近被蝕刻之速度更快之速度,對遠離被覆層之部位之銅進行蝕刻,藉此銅的電路圖案之蝕刻係大致垂直地進行。藉此可除去不需要銅的部分,繼而剝離/除去蝕刻抗蝕劑,露出電路圖案。The layered body having the structure in which a resist is applied on the surface of the coating layer formed on the copper foil formed on the layered body produced by the above method and covered by the mask is immersed in the etching liquid. A resist pattern is formed by development. In this case, the coating layer composed of one selected from the group consisting of platinum group metals, gold, and silver which are suppressed from etching is located on the copper foil at a position close to the resist portion, and the copper foil on the resist side The etching is performed by etching the copper away from the coating layer at a speed faster than the etching of the vicinity of the coating layer, whereby the etching of the copper circuit pattern is performed substantially vertically. Thereby, the portion which does not require copper can be removed, and then the etching resist is peeled off/removed to expose the circuit pattern.
相對於用以在積層體形成電路圖案之蝕刻液,被覆層的蝕刻速度充分小於銅,因此,具有改善蝕刻因數之效果。蝕刻液可使用氯化銅水溶液或氯化鐵水溶液等,但氯化鐵水溶液尤其有效。其原因在於:微細電路的蝕刻需要花費時間,而氯化鐵水溶液的蝕刻速度比氯化銅水溶液快。又,於形成被覆層之前,亦可預先於銅箔基材表面形成耐熱層。The etching rate of the coating layer is sufficiently smaller than that of copper with respect to the etching liquid for forming the circuit pattern in the laminated body, and therefore, the effect of improving the etching factor is obtained. As the etching solution, an aqueous solution of copper chloride or an aqueous solution of ferric chloride or the like can be used, but an aqueous solution of ferric chloride is particularly effective. The reason for this is that the etching of the fine circuit takes time, and the etching solution of the aqueous solution of ferric chloride is faster than the aqueous solution of copper chloride. Further, a heat-resistant layer may be formed in advance on the surface of the copper foil substrate before the formation of the coating layer.
[實施例][Examples]
以下,舉出本發明的實施例,提供這些實施例係為了更好地理解本發明,其意圖並非在於限定本發明。The embodiments of the present invention are exemplified below, and are intended to provide a better understanding of the present invention and are not intended to limit the invention.
(例1:實施例1~33)(Example 1: Examples 1 to 33)
(於銅箔形成被覆層)(forming a coating on copper foil)
準備厚度為12或17μm的壓延銅箔(日礦金屬製造C1100)來作為實施例1~21和實施例25~30的銅箔基材。壓延銅箔的表面粗糙度(Rz)為0.7μm。又,準備厚度為9μm之未經粗化處理之電解銅箔來作為實施例22~24的銅箔基材。電解銅箔的表面粗糙度(Rz)為1.5μm。進而,準備厚度為8μm之金屬噴敷CCL(日礦金屬製造makinasu,銅層側Ra為0.01μm,連結塗層的金屬附著量Ni為1780μg/dm2 ,Cr為360μg/dm2 )來作為實施例31~33的銅箔基材。A rolled copper foil (manufactured by Nippon Steel Co., Ltd. C1100) having a thickness of 12 or 17 μm was prepared as the copper foil substrates of Examples 1 to 21 and Examples 25 to 30. The surface roughness (Rz) of the rolled copper foil was 0.7 μm. Further, an electrolytic copper foil having a thickness of 9 μm which was not roughened was prepared as the copper foil substrates of Examples 22 to 24. The surface roughness (Rz) of the electrolytic copper foil was 1.5 μm. Further, a metal sprayed CCL having a thickness of 8 μm (mangansu made from Nippon Minerals, 0.01 μm on the copper layer side, and a metal adhesion amount Ni of the tie coat layer of 1780 μg/dm 2 and Cr of 360 μg/dm 2 ) was prepared. The copper foil substrates of Examples 31 to 33.
藉由逆向濺鍍去掉附著於銅箔表面之薄氧化膜,並利用以下裝置及條件對Au、Pt及/或Pd之靶進行濺鍍,藉此形成被覆層。被覆層的厚度可藉由調整成膜時間而變化。濺鍍所使用之各種金屬的單體係使用純度為3N者。A thin oxide film adhering to the surface of the copper foil was removed by reverse sputtering, and a target of Au, Pt, and/or Pd was sputtered by the following apparatus and conditions to form a coating layer. The thickness of the coating layer can be varied by adjusting the film formation time. A single system of various metals used for sputtering is used with a purity of 3N.
‧裝置:批次式濺鍍裝置(ULVAC公司,型號MNS-6000)‧Installation: Batch Sputtering Device (ULVAC, Model MNS-6000)
‧極限真空(ultimate vacuum):1.0×10-5 Pa‧ ultimate vacuum: 1.0 × 10 -5 Pa
‧濺鍍壓:0.2Pa‧ Sputtering pressure: 0.2Pa
‧逆向濺鍍功率:100W‧Reverse sputtering power: 100W
‧濺鍍功率:50W‧ Sputtering power: 50W
‧成膜速度:針對各靶經一定時間成膜約0.2μm,用三維測定器測定厚度,計算出每單位時間的濺鍍速率。‧ Film formation rate: The film was formed into a film for about 0.2 μm for a certain period of time, and the thickness was measured by a three-dimensional measuring device to calculate the sputtering rate per unit time.
於上述實施例中,實施例28~30使用了以下靶。In the above examples, Examples 28 to 30 used the following targets.
‧靶:Au-50質量%Pd、Pt-50質量%Pd及Au-50質量%Pt‧Target: Au-50% by mass Pd, Pt-50% by mass Pd, and Au-50% by mass Pt
對形成有上述被覆層之表面之相反側的銅箔基材表面,根據以下條件藉由逆向濺鍍預先將附著於銅箔基材表面之薄氧化膜去掉,並對Ni和Cr單層之靶進行濺鍍,藉此依次使Ni層和Cr層成膜。Ni層和Cr層的厚度可藉由調整成膜時間而變化。On the surface of the copper foil substrate on the opposite side to the surface on which the coating layer was formed, the thin oxide film adhering to the surface of the copper foil substrate was previously removed by reverse sputtering according to the following conditions, and the target of the Ni and Cr single layer was removed. Sputtering is performed to sequentially form a Ni layer and a Cr layer. The thickness of the Ni layer and the Cr layer can be varied by adjusting the film formation time.
‧裝置:批次式濺鍍裝置(ULVAC公司,型號MNS-6000)‧Installation: Batch Sputtering Device (ULVAC, Model MNS-6000)
‧極限真空:1.0×10-5 Pa‧ ultimate vacuum: 1.0 × 10 -5 Pa
‧濺鍍壓:0.2Pa‧ Sputtering pressure: 0.2Pa
‧逆向濺鍍功率:100W‧Reverse sputtering power: 100W
‧靶:‧target:
Ni層用=Ni(純度為3N)Ni layer = Ni (purity is 3N)
Cr層用=Cr(純度為3N)Cr layer = Cr (purity is 3N)
‧濺鍍功率:50W‧ Sputtering power: 50W
‧成膜速度:針對各靶經一定時間成膜約0.2μm,用三維測定器測定厚度,計算出每單位時間的濺鍍速率。‧ Film formation rate: The film was formed into a film for about 0.2 μm for a certain period of time, and the thickness was measured by a three-dimensional measuring device to calculate the sputtering rate per unit time.
按照以下順序,將聚醯亞胺膜接著於銅箔基材之Ni層和Cr層形成側表面。The polyimide film was formed into a side surface on the Ni layer and the Cr layer of the copper foil substrate in the following order.
(1)使用塗佈器,對7cm×7cm之銅箔以乾燥體達25μm之方式塗佈宇部興產製造的UVarnish-A(聚醯亞胺清漆)。(1) UVarnish-A (polyimine varnish) manufactured by Ube Industries was applied to a copper foil of 7 cm × 7 cm in a dry body of 25 μm using an applicator.
(2)將由(1)所得之附有樹脂之銅箔於空氣下使用乾燥機以130℃乾燥30分鐘。(2) The resin-attached copper foil obtained in (1) was dried at 130 ° C for 30 minutes under air using a dryer.
(3)於氮流量設為10L/min之高溫加熱爐中,以350℃進行醯亞胺化30分鐘。(3) The hydrazine imidization was carried out at 350 ° C for 30 minutes in a high-temperature heating furnace in which the nitrogen flow rate was set to 10 L/min.
<附著量的測定><Measurement of adhesion amount>
被覆層的Au、Pd及Pt的附著量測定,係利用王水將表面處理銅箔樣本溶解,稀釋該溶解液,藉由原子吸光分析法來進行。The amount of adhesion of Au, Pd, and Pt in the coating layer was measured by dissolving the surface-treated copper foil sample with aqua regia, diluting the solution, and performing the atomic absorption spectrometry.
(藉由蝕刻而形成之電路形狀)(circuit shape formed by etching)
藉由於銅箔之形成有被覆層之面塗佈感光性抗蝕劑及進行曝光步驟而印刷10條電路,進而根據以下條件來實施除去不需要銅箔的部分之蝕刻處理。By applying a photosensitive resist to the surface of the coating layer on which the copper foil is formed and performing an exposure process, 10 circuits are printed, and an etching process for removing a portion where the copper foil is not required is performed under the following conditions.
<蝕刻條件><etching conditions>
‧氯化鐵水溶液:(37wt%、波美度:40°)‧ Aqueous ferric chloride solution: (37wt%, Baume: 40°)
‧液溫:50℃‧ liquid temperature: 50 ° C
‧噴壓:0.25MPa‧ spray pressure: 0.25MPa
(形成間距為50μm之電路)(Form a circuit with a pitch of 50 μm)
‧抗蝕劑L/S=33μm/17μm‧Resist L/S=33μm/17μm
‧完成電路下部(底部)寬度:25μm‧Complete circuit bottom (bottom) width: 25μm
‧蝕刻時間:10~130秒‧ Etching time: 10 ~ 130 seconds
(形成間距為30μm之電路)(Forming a circuit with a pitch of 30 μm)
‧抗蝕劑L/S=25μm/5μm‧Resist L/S=25μm/5μm
‧完成電路下部(底部)寬度:15μm‧Complete circuit bottom (bottom) width: 15μm
‧蝕刻時間:30~70秒‧ etching time: 30 to 70 seconds
‧蝕刻終點之確認:改變時間,按多個標準進行蝕刻,利用光學顯微鏡確認銅未殘留於電路之間,該時間即為蝕刻時間。‧ Confirmation of etching end point: The time was changed, etching was performed according to a plurality of standards, and it was confirmed by an optical microscope that copper did not remain between the circuits, and this time was the etching time.
蝕刻後,於45℃的NaOH水溶液(100g/L)中浸漬1分鐘,剝離抗蝕劑。After the etching, the mixture was immersed in an aqueous NaOH solution (100 g/L) at 45 ° C for 1 minute to remove the resist.
<蝕刻因數的測定條件><Measurement conditions of etching factor>
蝕刻因數係用來表示下述a與銅箔厚度b之比b/a,該a係表示逐漸展開蝕刻時(產生壓陷時)、以及假設電路垂直蝕刻時之來自銅箔上面的垂線與樹脂基板之交點開始之壓陷長度的距離,該b/a數值越大,意味著傾斜角變得越大,無蝕刻殘渣殘留,壓陷變小。圖1係表示部分電路圖案的表面照片、該部分中的電路圖案的寬度方向橫剖面示意圖及使用該示意圖之蝕刻因數計算方法之概略。該a係自電路上方藉由SEM觀察來測定,計算出蝕刻因數(EF=b/a)。藉由使用該蝕刻因數,可以簡單地判斷出蝕刻性之良否。進而,傾斜角θ係藉由利用按照上述順序測定之a及銅箔的厚度b來計算反正切而算出。其測定範圍係電路長為600μm,12點蝕刻因數,採用其標準偏差和傾斜角θ的平均值作為結果。The etching factor is used to indicate the ratio b/a of the following a to the thickness b of the copper foil, which indicates the gradual development of the etching (when the depression occurs), and the vertical line from the copper foil and the resin when the circuit is vertically etched. The distance of the indentation length from the intersection of the substrates, the larger the b/a value means that the inclination angle becomes larger, and no etching residue remains, and the depression becomes small. 1 is a photograph showing a surface of a partial circuit pattern, a schematic cross-sectional view in the width direction of a circuit pattern in the portion, and an outline of a method for calculating an etching factor using the schematic. This a is measured from the top of the circuit by SEM observation, and the etching factor (EF = b / a) is calculated. By using this etching factor, it is possible to easily judge whether or not the etching property is good. Further, the inclination angle θ is calculated by calculating the arctangent by using a measured in the above-described order and the thickness b of the copper foil. The measurement range is a circuit length of 600 μm, a 12-point etching factor, and the average value of the standard deviation and the inclination angle θ is used as a result.
(例2,比較例1~3:胚料)(Example 2, Comparative Examples 1 to 3: blank)
準備12μm厚、17μm厚及9μm厚之壓延銅箔,分別按照與例1相同的順序接著聚醯亞胺膜。繼而於相反面藉由塗佈感光性抗蝕劑及進行曝光步驟來印刷10條電路,進而以例1之條件實施除去不需要銅箔的部分之蝕刻處理。A rolled copper foil having a thickness of 12 μm, a thickness of 17 μm, and a thickness of 9 μm was prepared, and the polyimide film was subsequently laminated in the same order as in Example 1. Then, 10 circuits were printed by applying a photosensitive resist and performing an exposure step on the opposite side, and etching treatment for removing a portion not requiring a copper foil was carried out under the conditions of Example 1.
(例3:比較例4~6)(Example 3: Comparative Examples 4 to 6)
準備厚度為12μm之壓延銅箔,按照與例1相同的順序接著聚醯亞胺膜。繼而,與例1相同地於銅箔表面藉由濺鍍來形成Au、Pd及/或Pt之各層,利用蝕刻形成電路。A rolled copper foil having a thickness of 12 μm was prepared, and a polyimide film was attached in the same order as in Example 1. Then, in the same manner as in Example 1, each layer of Au, Pd, and/or Pt was formed by sputtering on the surface of the copper foil, and an electric circuit was formed by etching.
例1~3的各測定結果如表1~4所示。The measurement results of Examples 1 to 3 are shown in Tables 1 to 4.
再者,如圖2(b)所示,電路的剖面形狀,精確地說並非斜邊為直線之梯形。於表2和表4中,記載有實施例和比較例的電路的傾斜角,但這不過為藉由圖1所示之定義式計算出之值。Furthermore, as shown in Fig. 2(b), the cross-sectional shape of the circuit is precisely a trapezoid in which the oblique side is a straight line. In Tables 2 and 4, the inclination angles of the circuits of the examples and the comparative examples are described, but this is merely a value calculated by the definition shown in Fig. 1.
(評價)(Evaluation)
(實施例1~33)(Examples 1 to 33)
實施例1~33均可形成蝕刻因數較大且無不均、並且剖面近似於矩形方狀之電路。Each of Examples 1 to 33 can form a circuit having a large etching factor and no unevenness, and the cross section is approximately rectangular.
圖2係表示根據實施例27所形成之電路的照片及其剖面照片。2 is a photograph showing a circuit formed according to Embodiment 27 and a cross-sectional photograph thereof.
(比較例1~6)(Comparative Examples 1 to 6)
比較例1~3分別為銅箔表面未經處理之胚料,未能形成剖面為矩形方狀之電路。Comparative Examples 1 to 3 were unprocessed blanks on the surface of the copper foil, respectively, and a circuit having a rectangular cross section was not formed.
於比較例4~6中,鉑附著量超過1050μg/dm2 ,鈀附著量超過600μg/dm2 或者金附著量超過1000μg/dm2 ,因此,未能形成剖面為矩形方狀之電路。此處,作為一例,圖3係表示根據比較例6所形成之電路的照片。In Comparative Examples 4 to 6, the platinum adhesion amount exceeded 1050 μg/dm 2 , the palladium adhesion amount exceeded 600 μg/dm 2 or the gold adhesion amount exceeded 1000 μg/dm 2 , and thus a circuit having a rectangular cross section was not formed. Here, as an example, FIG. 3 is a photograph showing a circuit formed in accordance with Comparative Example 6.
圖1:係表示部分電路圖案的表面照片、該部分中的電路圖案的寬度方向之橫剖面示意圖及使用該示意圖之蝕刻因數(Etching factor;EF)之概略計算方法。Fig. 1 is a photograph showing a surface of a partial circuit pattern, a cross-sectional view in the width direction of a circuit pattern in the portion, and an outline calculation method using an etching factor (EF) of the schematic.
圖2:係表示根據實施例27所形成之電路及其剖面之照片。Fig. 2 is a photograph showing a circuit formed according to Embodiment 27 and a cross section thereof.
圖3:係表示根據比較例6所形成之電路之照片。Fig. 3 is a photograph showing the circuit formed in accordance with Comparative Example 6.
圖4:係表示於形成銅電路時產生「壓陷」而在樹脂基板附近發生銅電路短路之一例的電路表面放大照片。Fig. 4 is a magnified photograph of a circuit surface showing an example of occurrence of "indentation" in the formation of a copper circuit and short-circuiting of a copper circuit in the vicinity of a resin substrate.
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US5338619A (en) * | 1991-05-16 | 1994-08-16 | Fukuda Metal Foil And Powder Co., Ltd. | Copper foil for printed circuits and method of producing same |
CN1111567A (en) * | 1993-12-28 | 1995-11-15 | 日本电解株式会社 | Copper clad laminate, multilayer printed circuit board and their processing method |
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