TWI404119B - Method for fabricating semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device includes forming a first mask pattern over an etch target layer, forming a second mask pattern over the etch target layer, forming spacers at sidewalls of the first mask pattern and the second mask pattern, and etching the etch target layer with an etching mask where the second mask pattern is removed. The method improves a profile of a pad pattern and critical dimension uniformity.

Description

Method of manufacturing a semiconductor component Cross-references for related applications

The priority of Korean Patent Application No. 10-2007-0140859 and No. 10-2008-49895, filed on Dec. 28, 2007 and May 28, 2008, is hereby incorporated by reference.

This invention relates to a method for fabricating a semiconductor component using a spacer patterning technique (SPT).

When the degree of integration of the semiconductor elements is increased, the size and pitch of the patterns constituting the circuits are reduced. In order to form a fine pattern in the semiconductor element, various manufacturing apparatuses and process methods have been proposed.

Photolithography (also known as optical lithography) is a process for microfabrication to selectively remove a portion of a film (or a body of a substrate). It uses light to transfer a geometric pattern from a reticle to a photochemical (photo-resist or simply ''resist'') on the substrate. According to the ruibic equation, the size of one of the fine patterns in a semiconductor component is proportional to the wavelength of the light used in the photolithography process and inversely proportional to the size of the lens used in the process. As a result, the wavelength of the light used in the exposure process is reduced or the size of the lens is increased to obtain a fine pattern. However, these methods require the development of new manufacturing equipment, which causes difficulties in equipment management; and, therefore, increases manufacturing costs.

In order to overcome the above problems, other methods of forming a highly integrated fine pattern by using a conventional device (not a new manufacturing device) have been proposed. One kind The method is a double patterning technique, which implements an exposure process in which a photoresist film is patterned twice with different masks to print a circuit pattern, and another method uses a spacer as an etching mask to obtain a Fine pattern spacer patterning technique (SPT). Hereinafter, the SPT will be described in detail.

Figures 1a through 1e illustrate cross-sectional views of one of the conventional semiconductor components, SPT (particularly a method for forming a control gate of a flash memory device). Typically, the flash memory component includes a cell string coupled to a plurality of (16 or 32) control gates and a source select line (SSL) coupled to both ends of the cell string. And a switching transistor for a drain select line (DSL).

Referring to FIG. 1a, an etch target layer 110 is formed over a semiconductor substrate 100, and a sacrificial film 120 is formed over the etch target layer 110. The etch target layer 110 has a deposition structure including a polysilicon 110a and a nitride film 110b. The sacrificial film 120a includes a tetraethyl orthosilicate (TEOS) oxide film. The deposited thickness of the sacrificial film 120a determines the height of a spacer used in the SPT.

A hard mask layer 160, a bottom anti-reflective coating (BARC) film 170 and a first photoresist film are formed over the sacrificial film 120a. However, when an exposure process is performed, it is difficult to form a first one defined in a mask due to the difference in refractive index between a photoresist film and a hard mask formed at the bottom of the photoresist film. Fine photoresist pattern. As a result, the BARC film 170 is used to prevent the light reflected by the difference in refractive index between the photoresist film and the hard mask from damaging the photoresist film 180.

Usually, an anti-reflection film has been used in a semiconductor lithography process. A thin layer of light absorbing photoresist material for stably forming a fine circuit. In the antireflection film, a contact interface and optical characteristics are required to match a photoresist material having high resolution used in a conventional process. The anti-reflection film adjusts a substrate reflectance in a corresponding wavelength range to obtain a photoresist pattern without a standing wave or a notching. Moreover, the anti-reflective film improves critical dimension (CD) uniformity and adhesion of the photoresist pattern to the substrate. As a result, the anti-reflective film plays an important role in a DUV process. The anti-reflection film comprises a top anti-reflective coating (TARC) film formed on the photoresist film and a BARC film formed on the bottom of the photoresist film. The BARC film has been widely used to obtain a fine circuit pattern.

Referring to FIG. 1a, the BARC film 170 and the hard mask layer 160 are etched using the first photoresist pattern 180 as a mask. The sacrificial film 120a is etched using the patterned hard mask layer 160 to form a sacrificial pattern 120. After the sacrificial pattern 120 is formed, the first photoresist pattern 180, the anti-reflection film 170, and the hard mask layer 160 are removed.

Referring to Figure 1b, a layer of spacer material is formed over the formed structure, including the sacrificial pattern 120. An etching process is performed to form a spacer 130 on the sidewall of the sacrificial pattern 120. The spacer 130 includes a polysilicon and defines the control gate.

Referring to FIG. 1c, a wet etching process is performed to remove the sacrificial pattern 120 to retain only the spacer 130.

Referring to FIG. 1d, a second photoresist pattern 140 for defining a gate of a switching transistor is formed in a peripheral region (not in an intermediate region having a plurality of control gates formed in the semiconductor substrate 100).

The switching transistor connected to the SSL and DSL in the peripheral area is usually disposed at both ends of the cell string. In the exposure process, the switching transistor, rather than the control gate formed in the intermediate region, may have a defective focus. When the out-of-focus of the peripheral region becomes more serious, the manufacturing margin of the depth of focus (DOF) is insufficient. Moreover, the switching cell system for connecting the select lines SSL and DSL is related to the conduction of a channel, so that accurate control of the size of the CD and the size of the pattern is required. Moreover, the size and width of the switching transistor and the select lines are larger than the size of the control gate included in the cell string, so that it is difficult to form a fine pattern using the spacer 130. As a result, an additional second photoresist pattern 140 is required in the peripheral region.

Referring to FIG. 1e, the spacer 130 and the second photoresist pattern 140 are used as a mask to etch the etch target layer 110 to form a plurality of control gates and at both ends of the string. The etch target patterns 155a and 155b of the gate of the switching transistor are arranged.

A third photoresist pattern (not shown) is formed to expose outer edges of the semiconductor substrate on which the etch target patterns 155a and 155b are formed. The third photoresist pattern (not shown) is a cut mask for dividing a spacer portion of a line end region produced in the deposition of the spacer material layer. Using the third photoresist pattern (not shown) as a mask to remove a portion of the etch target patterns 155a and 155b disposed on the line end to divide each line and remove the third photoresist pattern (not shown).

In the SPT, when a pad pattern 140 having a pad type for defining a gate of the switching transistor is formed, before the photoresist pattern 140 is formed, A BARC film is formed to prevent the photoresist pattern 140 from being damaged. However, the BARC film could not be formed due to the spacer 130 previously formed. As shown in FIG. 1d, when the BARC film cannot be formed when the spacer 130 is formed, the photoresist pattern 140 may have a defect profile and other defects.

Although the anti-reflection film may be deposited to have a predetermined thickness in a peripheral region having no spacer 130 when the spacer 130 is formed, the anti-reflection film is not formed on the spacer Fine areas of 130, but deposited to have a large thickness. In this case, the anti-reflective film is deposited to improve the profile and CD uniformity of the photoresist pattern 140. However, when the etch target layer 110 is etched after forming the photoresist pattern 140 having the pad type, the method is required to include using the photoresist pattern 140 as a mask to remove the anti-reflection film. Also, it is necessary to increase the thickness of the photoresist pattern 140, so that it is impossible to ensure a manufacturing margin.

When the anti-reflective film is removed by an etching gas including CF ₄ , the spacer 130 is eroded to reduce its height. As a result, the etching selectivity is insufficient in etching the etching target layer 110.

As described above, in the conventional method for manufacturing a semiconductor element, it is difficult to apply an anti-reflection film in the formation of the pad-type photoresist pattern 140, which causes a slit due to reflection of light, The pattern of the photoresist pattern formed in the peripheral region, the slag in the narrow block between the patterns, and the pattern due to the decrease in adhesion to the substrate.

Various embodiments of the present invention are directed to providing a method for fabricating a semiconductor device, the method comprising the step of forming a semiconductor device by a mask An anti-reflection film is applied before the etching target pattern to form a pattern for the pad to improve the contour and CD uniformity of the pattern for the pad and prevent the slag and pattern of the photoresist pattern from being pulled up, thereby improving the component. Characteristics.

According to an embodiment of the invention, a method for fabricating a semiconductor device includes: forming a first mask pattern over an etch target layer; forming a second mask pattern over the etch target layer; forming a spacer The etch target layer is etched on the sidewalls of the first mask pattern and the second mask pattern; and an etch mask having the second mask pattern removed. Here, the material and size of the second mask pattern are different from the material and size of the first mask pattern.

Preferably, the first mask pattern and the spacer formed on the sidewall of the first mask pattern are used as the etching mask for forming a gate pattern of a switching transistor, wherein the switching The crystal connects a source select line and a drain select line to both ends of a string. And, a spacer formed on a sidewall of the second mask pattern is used as the etching mask for forming a plurality of control gate patterns in the cell string.

According to an embodiment of the invention, a method for fabricating a semiconductor device includes: continuously forming a rough mask pattern for forming a gate pattern of a switching transistor and forming a pattern in a cell string. a fine mask pattern for controlling the gate pattern; and forming spacers on the sidewalls of the coarse mask pattern and the thin mask pattern to perform an STI process.

According to an embodiment of the invention, a method for fabricating a semiconductor device includes: forming an etch target layer over a semiconductor substrate; forming a pad pattern on the etch target disposed on an edge of the semiconductor substrate Forming a planarization sacrificial film over the formed structure (including the pad pattern); etching the sacrificial film to form a sacrificial pattern without etching the pad pattern; forming a spacer on the sacrificial pattern and the On the pad pattern; removing the sacrificial pattern to retain the spacers; and etching the etch target layer by using the spacers and the pad pattern having the spacers as a mask.

2a through 2g are cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. In this embodiment, the semiconductor device includes a cell string connected to a plurality of control gates and a source select line (SSL) and a drain select line (DSL) connected to both ends of the cell string. Switch the transistor.

Referring to FIG. 2a, an etch target layer 210 is formed over a semiconductor substrate 200. A polysilicon layer 220a and a first BARC film 250a are formed over the etch target layer 210. A first photoresist pattern 260a defining a pattern for the pad is formed over the first BARC film 250a. The etch target layer 210 has a deposition structure including a polysilicon 210a and a nitride film 210b.

Referring to FIG. 2b, the polysilicon layer 220a is etched by using the first photoresist pattern 260a as a mask to form a pattern 220 for the pad, wherein the pattern 220 defines the switching power for connecting SSL or DSL. The gate of the crystal. A spacer is formed on the sidewall of the pattern 220 via a subsequent spacer formation process. As a result, the pattern 220 is formed to be smaller than the gate of the switching transistor (having the thickness of the spacer).

After forming the first BARC film 250a, an exposure process is performed to The defect or the slit of the first photoresist pattern 260a is prevented. That is, after forming a BARC film over an etch target layer, a photoresist pattern is formed to reduce the reflective capability of the etch target layer, thereby preventing the defect of the pattern for the pad and the slag of the photoresist pattern and Pull up.

Referring to FIG. 2c, a chemical mechanical polishing (CMP) process is performed to planarize a sacrificial film 230 formed over the pattern 220 and the etch target layer 210.

The sacrificial film 230 includes a TEOS film. Moreover, since the sacrificial film 230 determines the height of the spacer in an SPT process, the sacrificial film 230 is formed to have more than a predetermined height. When the sacrificial film 230 is formed to have a small height, it is difficult to form a spacer having a desired height and thickness via a subsequent process. For example, a spacer formed on the side of a mask pattern can be deposited at a thickness of about 30 nm at a time. However, when the mask pattern is not higher than 30 nm, the spacer is formed to have a thin thickness.

When the sacrificial film 230 is deposited to have a predetermined thickness, a step difference is generated due to the pattern 220. This step may cause out-of-focus in a subsequent process to degrade the plurality of fine control gate patterns in a cell string. As a result, the CMP process is implemented to remove the step.

A hard mask 240 and a second anti-reflection film 250b are formed over the planarization sacrificial film 230. The hard mask 240 includes a polysilicon because it has insufficient etch selectivity to etch the sacrificial film 230 at the bottom in the photoresist pattern.

A second photoresist pattern 260b for defining a word line is formed over the second anti-reflection film 250b.

The second photoresist pattern 260b is formed to have a line/space type. Line: The ratio of the intervals is 1:3.

Referring to FIG. 2d, the second photoresist pattern 260b is used as a mask to etch the second anti-reflection film 250b and the hard mask 240.

The second photoresist pattern 260b, the second anti-reflection film 250b and the hard mask 240 are used as a mask to etch the bottom sacrificial film 230.

The pattern 220 is retained without etching because the sacrificial film 230 has an etch selectivity difference from the TEOS film and the pattern 220, wherein the pattern 220 is a polysilicon.

As shown in FIGS. 2c and 2d, when the second photoresist pattern 260b is formed by the exposure process, the second anti-reflection film 250b prevents a defect pattern which may be generated due to a difference in refractive index of the hard mask 240.

The second photoresist pattern 260, the second anti-reflection film 250, and the hard mask 240 are removed.

Referring to FIG. 2e, a polysilicon layer as a spacer forming material is deposited over the formed structure (including a sacrificial pattern 230a and the pattern 220).

An etching process is performed until the sacrificial pattern 230a is exposed to form a spacer 270 on the sidewalls of the sacrificial pattern 230a and the pattern 220.

The spacer 270 is formed on the sidewall of the pattern 220 to increase the CD of the pattern 220 so that a gate pattern larger than the pattern 220 can be formed.

Referring to Figure 2f, the sacrificial pattern 230a is removed so that spacers 270 for forming a plurality of control gate patterns in the cell string can be retained.

The sacrificial pattern 230a is removed by a wet etching method using HF. The nitride film 210b as the following material was not removed due to the resistance in the HF solution. Pattern 220 having the same etch selectivity as the spacer 270 is also not removed.

Referring to FIG. 2g, the etch target layer 210 is etched by using the spacer 270 and the pattern 220 on the sidewall on which the spacer 270 is formed as a mask. The nitride film 210b and the polysilicon 210a are continuously etched.

The pattern 220 used as a mask includes a polysilicon which improves etching uniformity compared to other materials used as a mask because the pattern 220 etches the same underlying material.

The spacer 270 and the pattern 220 are removed to form etch target patterns 215a and 215b, wherein the etch target patterns 215a and 215b define a plurality of control gate patterns and gates for connecting the SSL or DSL switching transistors pole.

A third photoresist pattern (not shown) exposing an outer edge of the semiconductor substrate 200 having the etch target patterns 215a and 215b is formed. The third photoresist pattern (not shown) is a cut mask for dividing a portion of the spacer disposed on one of the line end regions produced in the deposition of the spacer material layer.

Removing a portion of the etch target pattern 215 disposed on the line end with the third photoresist pattern (not shown) as a mask to divide each line and remove the third photoresist pattern ( Not shown).

Compared with the conventional method, in the embodiment of the present invention, a polysilicon film is formed (the polysilicon film is used to form an etching mask for forming a thick gate pattern). And forming a spacer for forming a fine gate pattern, and simultaneously forming a spacer (the spacer is an etching mask for forming a fine gate pattern) and forming a thick The photoresist pattern of the gate pattern. By a double exposure process, gate patterns having different sizes can be formed in a semiconductor device, thereby reducing the complexity of the process. Furthermore, after forming a BARC film, each exposure process is performed to increase the accuracy of formation of each photoresist pattern having a different size.

As described above, in a method for fabricating a semiconductor device in accordance with an embodiment of the present invention, an anti-reflection film is applied to form an etch target pattern by a unit mask process to form a The pattern of the pad, thereby improving the contour and CD uniformity of the pattern for the pad and preventing the slag and pattern of the photoresist pattern from being pulled up to improve the characteristics of the element.

The above-described embodiments of the present invention are described and not limited. Various alternatives and equalities are possible. The invention is not limited by the type of deposition, etch milling, and the patterning steps described herein. The invention is also not limited to any particular type of semiconductor component. For example, the invention can be implemented in a dynamic random access memory (DRAM) or non-volatile memory component. Other additions, deletions, or modifications are apparent to the present disclosure and are intended to fall within the scope of the appended claims.

200‧‧‧Semiconductor substrate

210‧‧‧etch target layer

220‧‧‧ pattern

220a‧‧ polycrystalline layer

230‧‧‧Sacrificial film

240‧‧‧hard mask

250a‧‧‧First BARC film

250b‧‧‧second anti-reflection film

260b‧‧‧second photoresist pattern

270‧‧‧ spacers

1a to 1e are cross-sectional views showing a conventional method for fabricating a semiconductor device.

2a through 2g are cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

200‧‧‧Semiconductor substrate

210‧‧‧etch target layer

210a‧‧‧ Polysilicon

210b‧‧‧ nitride film

220‧‧‧ pattern

230‧‧‧Sacrificial film

Claims (20)

A method for fabricating a semiconductor device, the method comprising: forming a first mask pattern on an etch target layer; forming a second mask pattern on the etch target layer; forming a first spacer on the first a sidewall of a mask pattern and a second spacer on a sidewall of the second mask pattern; removing the second mask pattern; and including the first mask pattern and the first spacer and the An etching mask of the second spacer etches the etch target layer. The method of claim 1, wherein the first mask pattern and the first spacer formed on the sidewall of the first mask pattern are used as a gate pattern for forming a switching transistor. The switching mask connects the source selection line and a drain selection line to both ends of a cell string. The method of claim 2, wherein the second spacer formed on the sidewall of the second mask pattern is used as the etching for forming a plurality of control gate patterns in the cell string. Cover. The method of claim 1, wherein the first mask pattern comprises a polysilicon film, and the second mask pattern comprises a TEOS film. The method of claim 1, wherein the first spacer and the second spacer comprise a polycrystalline germanium film. The method of claim 1, wherein the forming of the first mask pattern comprises: Forming a polysilicon film over the etch target layer; forming an anti-reflection film over the polysilicon film; patterning a photoresist film formed on the anti-reflection film; and etching the anti-reflection film with the photoresist film and The polycrystalline germanium film. The method of claim 1, wherein the forming of the second mask pattern comprises: forming a TEOS film over the etch target layer and the first mask pattern; forming an anti-reflection film over the TEOS film; Patterning a photoresist film formed on the anti-reflection film; and etching the anti-reflection film and the TEOS film with the photoresist film. A method for fabricating a semiconductor device, the method comprising: continuously forming a rough mask pattern for forming a gate pattern of a switching transistor and a control gate pattern for forming a cell string a fine mask pattern; and forming a spacer on the sidewall of the coarse mask pattern and the thin mask pattern to perform an SPT process. The method of claim 8, wherein the rough mask pattern and the fine mask pattern are formed by: forming a first anti-reflection film on a hard mask layer; and the first anti-reflection film a thick photoresist pattern formed thereon to pattern the hard mask layer; forming a sacrificial film covering the hard mask layer to planarize the sacrificial film; Forming a second anti-reflective film over the sacrificial film; and patterning the sacrificial film with a fine photoresist pattern formed on the second anti-reflective film. The method of claim 8, wherein the rough mask pattern has an etch selectivity that is the same as the spacer, and the fine mask pattern has an etch selectivity different from the spacer. The method of claim 8, wherein the SPT process comprises: forming a spacer on the sidewall of the coarse mask pattern and the fine mask pattern; removing the fine mask pattern; and using the spacer And the rough mask pattern is used to etch the etch target layer. A method for fabricating a semiconductor device, the method comprising: forming an etch target layer over a semiconductor substrate; forming a pad pattern on the etch target layer disposed on an edge of the semiconductor substrate; forming a planarization a sacrificial film over the structure including the pad pattern; etching the sacrificial film to form a sacrificial pattern without etching the pad pattern; forming spacers on the sacrificial pattern and sidewalls of the pad pattern; removing the Sacrificating the pattern to retain the spacers; and etching the etch target layer with the spacers and the pad pattern having the spacers as a mask. The method of claim 12, wherein the etch target layer has a deposition structure including a polysilicon layer and a nitride film. The method of claim 12, wherein the pad pattern defines a gate for a source select line (SSL) and a gate for a drain select line (DSL). The method of claim 12, wherein an anti-reflection film is used when forming a photoresist pattern for forming the pad pattern. The method of claim 12, wherein the critical dimension (CD) of the pad pattern is formed as a CD smaller than a target pattern. The method of claim 12, wherein the sacrificial film comprises a TEOS film. The method of claim 12, wherein an anti-reflection film is used when forming a photoresist pattern for forming the sacrificial pattern. The method of claim 13, wherein the sacrificial pattern is etched by a wet etching process using an HF solution. The method of claim 13, wherein the sacrificial pattern is formed to have a line/space pattern, and the line: spacing ratio is 1:3.