KR100784062B1 - Method for forming micro pattern in semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a fine pattern of a semiconductor device, comprising the steps of forming a predetermined polysilicon film pattern on a semiconductor substrate having an etched layer, forming a nitride film spacer on the side of the polysilicon film pattern, Forming an oxide film on the whole structure, removing a thickness of the oxide film, the nitride spacer, and a part of the polysilicon film pattern, removing the nitride spacer, and removing the oxide film and the polysilicon film Etching the etched layer using a pattern as a mask.

Fine pattern, superposition accuracy, spacer

Description

Method for forming micro pattern in semiconductor device

1A to 1C are diagrams for describing a double exposure etching technique according to the prior art.

2A to 2F are cross-sectional views of a fine pattern forming process of the semiconductor device according to the first embodiment of the present invention.

3A to 3J are cross-sectional views of a fine pattern forming process of a semiconductor device in accordance with a second embodiment of the present invention.

4A to 4C are plan views illustrating a fine pattern forming process of a semiconductor device according to a third exemplary embodiment of the present invention.

5 is a plan view of the mask used in the third embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

20: semiconductor substrate 21: etched layer

22: alpha carbon film 23: protective layer

24 polysilicon film 25 nitride film spacer

26: oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a fine pattern of a semiconductor device for forming a fine pattern having a pitch less than or equal to the resolution capability of an exposure apparatus.

The minimum pitch of the pattern formed in the photolithography process using light during the manufacturing process of the semiconductor element is determined according to the wavelength of the exposure light used in the exposure apparatus. Therefore, in the present situation in which high integration of semiconductor devices is accelerated, light having a shorter wavelength than that of currently used light must be used to form a pattern of smaller pitch. For this purpose, it is preferable to use X-rays or E-beams, but due to technical problems and productivity, they are still at the laboratory level. Accordingly, a double exposure etching technique (DEET) has been proposed.

1A to 1C are cross-sectional views for describing DEET. As shown in FIG. 1A, a first photoresist PR1 is coated on a semiconductor substrate 10 having an etched layer 11 and subjected to an exposure and development process. After the first photoresist PR1 is patterned, the etched layer 11 is etched using the patterned first photoresist PR1 as a mask. The line width of the etched layer 11 is 150 nm and the space width is 50 nm.

Subsequently, after the first photoresist PR1 is removed and the second photoresist PR2 is applied onto the entire structure, an exposure and development process is performed such that a portion of the etched layer 11 is exposed as shown in FIG. 1B. The second photoresist PR2 is patterned.

Subsequently, as shown in FIG. 1C, the etched layer 11 is re-etched using the patterned second photoresist PR2 as a mask to form a final pattern having a line and space width of 50 nm, and then the second photoresist ( PR2) is removed.

In the above-described double exposure etching technique, the overlay accuracy in the second photoresist PR2 exposure process is directly connected to the CD (Critical Dimension) variation of the final pattern. In fact, the overlapping accuracy of the exposure equipment is difficult to control the CD variation because it is difficult to control below 10nm, there is also a difficulty in controlling OPC (Optical Proximity Correction) by the circuit separation according to the double exposure.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a method of forming a fine pattern of a semiconductor device capable of reducing CD variation of a pattern.

In accordance with another aspect of the present invention, a method of forming a micropattern of a semiconductor device includes forming a first auxiliary pattern on a semiconductor substrate having an etched layer, forming a spacer on a side surface of the first auxiliary pattern, and forming the spacer. Forming a second auxiliary pattern on the semiconductor substrate in between, removing the spacers, and etching the target layer using the first auxiliary pattern and the second auxiliary pattern as a mask to form a fine pattern Steps.

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Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

2A to 2F are cross-sectional views of a micropattern forming process of a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 2A, an alpha-carbon film 22 and a protective layer 23 are sequentially formed on the semiconductor substrate 20 on which the etched layer 21 is formed, and then hard on the protective layer 23. The polysilicon film 24 for a mask is formed.

The alpha carbon layer 22 serves to compensate for the lack of etching selectivity during etching of the etching target layer 21 by using a mask formed on the upper layer, and the protective layer 23 protects the lower layer when forming an upper mask. It is preferable to form a SiON film as it plays a role.

The polysilicon layer 24 serves as an etch mask for the lower protective layer 23 and the alpha carbon layer 22, and the thickness of the polysilicon layer 24 is minimized in order to minimize the slope of a spacer to be formed later. Although it is preferable to increase the thickness of the polysilicon film 24, if the thickness of the polysilicon film 24 is too thick, it is difficult to gap fill the oxide film between the polysilicon film 24 during the deposition of the oxide film after formation of the spacer. You need to adjust it. Preferably, the polysilicon film 24 is formed to a thickness of 500 ~ 3000Å.

Then, the photo-etching polysilicon film 24 is patterned. At this time, it is preferable that the line width of the polysilicon film 24 is 50 nm and the space width is 130 nm.

Next, as shown in FIG. 2B, a nitride film is deposited on the entire structure and etched back to form a nitride film spacer 25 on the side of the polysilicon film 24. It is preferable that the nitride film spacer 25 has a thickness of, for example, 30 nm. When the nitride film spacer 25 is formed to a thickness of 30 nm, the space width between the polysilicon films 24 including the nitride film spacer 25 is 70 nm.

Then, as shown in FIG. 2C, an oxide film 26 for hard mask is formed on the entire structure so that the space between the polysilicon films 24 is completely filled. As the oxide layer 26, a high density plasma (HDP) oxide layer or a spin on glass (SOG) oxide layer having excellent gap fill characteristics may be used.

Subsequently, as shown in FIG. 2D, the oxide film 26, the polysilicon film 24, and the nitride film spacer 25 are partially flattened by a planarization process to remove the plurality of oxide films separated by the nitride film spacer 25. 26 and polysilicon films 24 are formed. In this case, it is preferable to use a chemical mechanical polishing (CMP) process or an entire surface etching process as the planarization process, and the oxide layers 26 and the polysilicon layers 24 remaining after the planarization process may be used. The width of the nitride film spacers 25 is 70 nm, 50 nm, and 30 nm, respectively.

Then, the nitride film spacer 25 is removed as shown in FIG. 2E.

Next, as shown in FIG. 2F, a cleaning process is performed to adjust the width of the oxide films 26, the width of the polysilicon films 24, and the space width caused by the removal of the nitride film spacers 25. For example, the reduction width of the oxide film 26 is 12.5 nm / side, and the reduction width of the polysilicon film 24 is 2.5 nm / side so that the line width of the polysilicon film 24 and the oxide film 26 are reduced. ) And the space width between the polysilicon film 24 and the oxide film 26 is equal to 45 nm.

Subsequently, although not shown, the polysilicon layers 24 and the oxide layers 26 are etched with the hard protective layer 23 and the alpha carbon layer 22 under the hard mask, and then the remaining polysilicon layers 24 are etched. The lower etching target layer 21 is etched using the peroxide films 26 and the alpha carbon film 22 as a mask to form a fine pattern having a pitch below the resolution limit of the exposure equipment.

In the above-described embodiment, a method of reducing the width of the polysilicon film 24 by 2.5 nm / side in the cleaning process after patterning the polysilicon film 24 to a width of 50 nm is difficult to pattern the width of the polysilicon film 24 to 50 nm. In this case, the width of the polysilicon film 24 may be patterned to be 60 nm or more, and the process may be performed so that the line and space widths are the same by adjusting the thickness of the nitride film spacer 25 and the time of the cleaning process.

In the aforementioned fine pattern forming technique according to the first embodiment of the present invention, since the exposure process is performed only once, the pattern CD variation caused by the double exposure etching technique can be prevented.

3A to 3J are cross-sectional views illustrating a process of forming a micropattern of a semiconductor device according to a second embodiment of the present invention, and include a drain select line (DSL) constituting a unit cell string of a NAND flash memory device according to the present invention; This is the case where it is applied to a process for forming gates of cell transistors and a source select line.

First, as shown in FIG. 3A, alpha carbon is deposited on a semiconductor substrate 30 on which a tunnel oxide film 31, a floating gate conductive film 32, a dielectric film 33, and a control gate conductive film 34 are stacked. The film 35 and the protective layer 36 are sequentially formed, and the polysilicon film 37 for hard mask is formed on the protective layer 36.

The alpha carbon layer 35 serves to compensate for the lack of etching selectivity when etching the control gate conductive layer 34, the dielectric layer 33, and the floating gate conductive layer 32 using a mask formed thereon. The protective layer 36 serves to protect the lower layer when the mask is formed, and is preferably formed of a SiON film.

The polysilicon layer 37 serves as an etch mask for the lower protective layer 36 and the alpha carbon layer 35, and the thickness of the polysilicon layer 37 is minimized to minimize the slope of the spacer to be formed later. Although it is preferable to increase the thickness of the polysilicon film 37, if the thickness of the polysilicon film 37 is too thick, it is difficult to gap fill the oxide film between the polysilicon film 37 during the deposition of the oxide film after formation of the spacer. You need to adjust it. Preferably, the polysilicon film 37 is formed to a thickness of 500 ~ 3000Å.

Subsequently, the polysilicon layer 37 is patterned by a photolithography process so that gates of the drain select line DSL, the cell transistor, and the source select line SSL are defined.

Next, as illustrated in FIG. 3B, a nitride film is deposited on the entire structure and etched back to form a nitride film spacer 38 on the side of the polysilicon film 37.

Then, as shown in FIG. 3C, an oxide film 39 for a hard mask is formed on the entire structure so that the space between the polysilicon films 37 is completely filled.

Subsequently, as shown in FIG. 3D, the oxide film 39, the polysilicon film 37, and the nitride film spacer 38 are partially flattened to remove the thickness, and the plurality of oxide films are separated with the nitride film spacer 38 interposed therebetween. 39 and polysilicon films 37 are formed. As the planarization process, it is preferable to use any one of a chemical mechanical polishing (CMP) process or an entire surface etching process.

Then, the nitride film spacer 38 is removed as shown in Fig. 3E, and the width of the oxide films 39, the width of the polysilicon films 37, and the oxide film as shown in Fig. 3F are formed. The widths of the oxide films 39 and the polysilicon films 37 are reduced by a wet etching process so that the space width between the 39 and the polysilicon films 37 is the same.

An oxide film A is also formed between the polysilicon films 37 that define the gate of the drain select line DSL and between the polysilicon films 37 that define the gate of the source select line SSL. When the etching process is performed on the lower layers while 39 remains, an unwanted gate pattern is formed in the drain region and the source region. The gate of the drain select line DSL is defined to prevent this phenomenon. The corresponding oxide film A formed between the polysilicon films 37 and between the polysilicon films 37 defining the gate of the source select line SSL must be removed.

Thus, as shown in FIG. 3G, the antireflection film 40 is formed on the entire structure, and the photoresist PR is applied on the antireflection film 40, and then the portion where the corresponding oxide film A is formed is exposed. The photoresist PR is patterned by exposure and development processes as much as possible.

Next, as shown in FIG. 3H, the antireflection film 40 and the corresponding oxide film A are removed using the patterned photoresist PR. In this case, in order to improve the overlap margin due to the double exposure, it is preferable to proceed with the etching process under the condition that the etching rate of the oxide film is faster than the polysilicon film.

Since the pattern pitch is larger than the portion where the cell transistor is to be formed, the DSL and SSL are not sensitive to the overlapping accuracy, so the variation of the pattern size due to the double exposure is not a problem. When the etching process is performed at a high etching rate, the polysilicon film 37 is etched even when the oxide film A and the polysilicon film 37 adjacent to the oxide film 39 are exposed during the photoresist exposure process. Since only the oxide film A and the anti-reflection film 40 may be selectively etched without developing, an overlap margin may be secured during the exposure process.

Subsequently, the photoresist PR and the anti-reflection film 40 are removed as shown in FIG. 3I, and then the oxide films 39 and the polysilicon films 37 are protected with a hard mask as shown in FIG. 3J. The layer 36 and the alpha carbon film 35 are etched, and the lower control gate conductive film 34 is formed by using the remaining oxide films 39, the polysilicon films 37, and the alpha carbon film 35 as a mask. And the dielectric film 33 and the floating gate conductive film 32 are etched to form gates having a pitch less than or equal to the resolution of the exposure equipment.

In the second embodiment, by using the difference in the etching ratio between the oxide film and the polysilicon film, it is possible to secure the overlap margin during the exposure process in the DSL and SSL formation region where the double exposure and etching process is inevitable.

After forming a hard mask film having an alternating structure of an oxide film and a polysilicon film, the above-described method of removing an oxide film of a portion not desired to form a pattern by using an etch ratio difference between the oxide film and the polysilicon film is performed in the interconnection and peripheral circuit regions. It is also applicable at the time of pattern formation.

A third embodiment in which the present invention is applied to the interconnection and the pattern formation of the peripheral circuit region will be described with reference to the accompanying drawings.

4A to 4C are plan views illustrating a method of forming a micropattern of a semiconductor device according to a third exemplary embodiment of the present invention, and FIG. 5 is a planar structural diagram of a mask used in the third exemplary embodiment of the present invention.

4A shows the formation of an alpha carbon film (not shown) and a protective layer (not shown) and a polysilicon film 41 for a hard mask on a semiconductor substrate having an etched layer, and patterning the polysilicon film 41 by a photolithography process. After that, the nitride film spacer 42 is formed on the side surface of the polysilicon film 41.

4B is a plan view of forming a hard mask oxide film 43 on the entire structure and partially removing the oxide film 43, the nitride spacer 42, and the polysilicon film 41 by a planarization process.

4C shows that the nitride spacer 42 is removed, an antireflection film (not shown) and a photoresist (not shown) are applied to the entire structure, and the patterned photoresist is patterned with a mask shown in FIG. It is a plan view which removed the oxide film 43 formed in the part which does not want to form a pattern using the difference in the etching ratio of a polysilicon film and an oxide film using the photoresist as an etching mask.

In this manner, a hard mask film made of the oxide film 43 and the polysilicon film 41 is formed, and then the protective layer and the alpha carbon film are etched using the hard mask film as a mask, and the remaining hard mask film and the alpha carbon film are used as a mask. Etching the etched layer can form a desired type of interconnect and pattern of peripheral circuitry.

In the above description, a case in which the present invention is applied to a flash memory device has been described as an example. However, the present invention provides a gate fabrication process, a device isolation trench process, and a contact formation process of all semiconductor devices such as DRAM and SRAM. It is also applicable to the back.

As described above, the present invention has the following effects.

First, a pattern having a pitch less than half the resolution of the exposure equipment is formed by forming a hard mask film having a pitch less than the resolution of the exposure equipment using a polysilicon film, a nitride spacer and an oxide film, and reducing the width of the hard mask through the wet etching process. Can be formed.

Second, since the pattern density is dense and the cell pattern sensitive to the overlapping accuracy may be formed through one exposure process instead of the double exposure process, pattern size variation due to lack of overlap margin of the double exposure process may be prevented.

Third, since the hard mask is composed of an oxide film and a polysilicon film, and an oxide film formed on a portion where pattern formation is unnecessary is removed by using an etch ratio difference between the oxide film and the polysilicon film, double exposure is inevitable, such as a pattern of a peripheral circuit area and an interconnection pattern. The overlap margin can be improved in the second exposure in the portion.

Claims (10)

Forming a first auxiliary pattern 24 on a semiconductor substrate having an etched layer 21; Forming a spacer 25 on a side of the first auxiliary pattern; Forming a second auxiliary pattern (26) on the semiconductor substrate between the spacers; Removing the spacers; Forming a fine pattern by etching the object layer using the first auxiliary pattern and the second auxiliary pattern as a mask. The method of claim 1, And forming an alpha carbon film on the semiconductor substrate having the etched layer prior to forming the first auxiliary pattern. The method of claim 1, And removing the second auxiliary pattern formed on a portion where pattern formation is not desired before performing the step of etching the etched layer after removing the spacer. Way. The method of claim 1, The removing of the second auxiliary pattern may include forming an anti-reflection film on the entire structure; Forming a photoresist on the anti-reflection film, the photoresist exposing the anti-reflection film on the second auxiliary pattern formed at a portion not desired to form a pattern; Removing the anti-reflection film and the second auxiliary pattern under the photoresist; And Removing the photoresist and the anti-reflection film. The method of claim 3, wherein And performing a wet etching process to adjust widths of the first auxiliary pattern and the second auxiliary pattern after removing the spacers and before removing the second auxiliary pattern. Method of forming a fine pattern of a semiconductor device. The method of claim 1, And forming the second auxiliary pattern as either an HDP oxide film or an SOG oxide film. The method of claim 1, The first auxiliary pattern is formed to a thickness of 500 ~ 3000Å micro pattern forming method of a semiconductor device. The method of claim 2, And forming a protective layer on the alpha carbon film after the forming of the alpha carbon film and before the forming of the first auxiliary pattern. The method of claim 8, The protective layer is a fine pattern forming method of a semiconductor device, characterized in that the SiON film. The method of claim 1, The method of forming a fine pattern of a semiconductor device, wherein the first auxiliary pattern is formed of polysilicon.

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