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TWI462266B - 晶片堆疊結構及其製造方法 - Google Patents

晶片堆疊結構及其製造方法 Download PDF

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Publication number
TWI462266B
TWI462266B TW101109411A TW101109411A TWI462266B TW I462266 B TWI462266 B TW I462266B TW 101109411 A TW101109411 A TW 101109411A TW 101109411 A TW101109411 A TW 101109411A TW I462266 B TWI462266 B TW I462266B
Authority
TW
Taiwan
Prior art keywords
wafer
glass substrate
signal processing
optical
holes
Prior art date
Application number
TW101109411A
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English (en)
Other versions
TW201340292A (zh
Inventor
Geng Shin Shen
Ya Chi Chen
I Hsin Mao
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW101109411A priority Critical patent/TWI462266B/zh
Priority to CN201210258997.1A priority patent/CN103325799B/zh
Priority to US13/801,255 priority patent/US8809088B2/en
Publication of TW201340292A publication Critical patent/TW201340292A/zh
Application granted granted Critical
Publication of TWI462266B publication Critical patent/TWI462266B/zh

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Description

晶片堆疊結構及其製造方法
本發明係關於一種晶片堆疊結構及其製造方法，該晶片堆疊結構特別是包含訊號處理晶片及光學晶片的堆疊結構。
隨著人們生活習慣的演變及製程技術的進步，影像感測器已廣泛地應用於日常生活中。已知的影像感測器例如：互補金屬氧化半導體(complementary metal-oxide semiconductor，CMOS)影像感測器、及電荷耦合元件(charge coupled device，CCD)影像感測器等等。其中，CMOS影像感測器具有價格低廉、耗電量低等優點，通常較適用於低階產品；而CCD影像感測器所擷取的影像品質較佳，則長期主宰了高階影像感測器的市場。
然而，由於數位訊號處理器(digital signal processor，DSP)晶片的加入，其與CMOS影像感測器的配合，恰補足了CMOS影像感測器的不足。詳言之，DSP晶片可模擬人眼，來處理感光元件無法辨識的情況，並進一步利用演算法輔助CMOS影像感測器的影像效能。因此，組合CMOS影像感測器與DSP晶片之模組，已逐漸使用在數位攝影機及數位相機等高畫素可攜式產品。
請參考第1A圖至第1C圖，所示為習知的影像感測(CMOS imaging sensor，CIS)晶片11與數位訊號處理器晶片12的封裝結構1及其製造過程。如第1A圖所示，複數個影像感測晶片11係形成於一晶圓13上，再進行切割而成之單一影像感測晶片11，各影像感測晶片11具有多個第一接點111分佈於影像感測晶片11之二側。而同樣地，複數個數位訊號處理器晶片12如第1B圖所示，亦是形成於一晶圓14上，再進行切割而成之單一數位訊號處理器晶片12，各數位訊號處理器晶片12具有多個第二接點121分佈於二側。
請參閱第1C圖，習知的技術是，將切割後的單一影像感測晶片11與單一數位訊號處理器晶片12橫向對齊排列定位於基板上，再以打線方式，將該等第一接點111與該等第二接點141依序電性連接。
可想見地，習知技術需先分別切割晶圓13及晶圓14，以製成單一且尺寸相應的影像感測晶片11及數位訊號處理器晶片12，後續還需要分別固定影像感測晶片11及數位訊號處理器晶片12，然後再進行打線連接。製程上較為繁複且生產時間長，製造成本偏高。另外，影像感測晶片11及數位訊號處理器晶片12的配置係為橫向並排設置於基板上，所佔據面積較大，且打線結合可靠度不佳，容易產生接觸不良或穩定性不佳的缺點。
有鑑於此，提供一種可改善製程、縮減體積與所佔面積、及提升可靠度之晶片堆疊結構及製造方法，乃為此一業界亟欲達成之目標。
本發明之一目的在於節省晶片堆疊結構的配置空間，藉由堆疊晶片之封裝結構，可避免習知封裝結構平行排列時所占較大面積之問題，本發明之晶片堆疊結構除了可節省所佔據的面積之外，所節省的空間更可提供給其它元件運用。
本發明之另一目的在於簡化晶片堆疊結構之製程。藉由將包含多個影像感測晶片之晶圓與包含多個數位訊號處理器晶片之基板先予以連接對合，再進行切割，以製成單一晶片堆疊結構，而非先個別切割形成影像感測晶片及數位訊號處理器晶片，故不需要習知的後續定位、打線連接等製程，可大幅簡化製程及降低生產的成本。
本發明之又一目的在於提高晶片堆疊結構及其製程的可靠度及穩定性，藉由以堆疊方式對合影像感測晶片與數位訊號處理器晶片，並透過基板中內鍍有金屬材料的複數貫穿孔(through hole)，電性連接於基板的外表面，使得整體之結構的穩定性及可靠度大幅提昇。
為達上述目的，本發明提供一種晶片堆疊結構，包含：一訊號處理晶片模組及一光學晶片模組，該訊號處理晶片模組包含：一玻璃基板，具有一第一表面、以及與該第一表面相對之一第二表面，該第一表面上更形成一凹穴，其中，該玻璃基板的第一表面與該凹穴內分別形成有貫穿孔，並於該貫穿孔內鍍有金屬材料以電性連接該第一表面及該第二表面；及一訊號處理晶片，設置於該凹穴中；該光學晶片模組包含一光學晶片，該光 學晶片模組於該第一表面上與該訊號處理晶片模組疊置，該光學晶片之面積係大於該訊號處理晶片之面積，以涵蓋該訊號處理晶片；其中，該訊號處理晶片及該光學晶片更分別包含複數導電接點，相應地連接該等貫穿孔，以於該第二表面上電性連接。
本發明更提供一種製造晶片堆疊結構之方法，包含下列步驟：提供一玻璃基板，其中，該玻璃基板具有一第一表面、以及與該第一表面相對之一第二表面，並依據一佈局於第一表面上形成複數個凹穴，凹穴與第一表面上設有內鍍金屬材料之複數貫穿孔，其中，該等訊號處理晶片嵌設於凹穴與貫穿孔電性連接；提供一晶圓，其中，該晶圓上設置有複數個光學晶片；及疊合該玻璃基板及該晶圓，使對應之該光學晶片及該訊號處理晶片，經由該等貫穿孔電性連接。
為讓上述目的、技術特徵、和優點能更明顯易懂，下文係以較佳實施例配合所附圖式進行詳細說明。
11‧‧‧影像感測晶片
111‧‧‧第一接點
12‧‧‧數位訊號處理器晶片
121‧‧‧第二接點
13‧‧‧晶圓
14‧‧‧晶圓
2‧‧‧晶片堆疊結構
21‧‧‧光學晶片模組
210‧‧‧晶圓
213‧‧‧光學晶片
213a‧‧‧導電接點
23‧‧‧訊號處理晶片模組
231‧‧‧玻璃基板
231a‧‧‧第一表面
231b‧‧‧第二表面
233‧‧‧訊號處理晶片
233a‧‧‧導電接點
235‧‧‧貫穿孔
237‧‧‧凹穴
25‧‧‧導電線路層
27‧‧‧銲球
29‧‧‧黏著層
901~907‧‧‧步驟
第1A圖係為習知製造影像感測晶片之示意圖；第1B圖係為習知製造數位訊號處理器晶片之示意圖；第1C圖係習知晶片封裝結構之示意圖；第2圖係本發明晶片堆疊結構之示意圖；第3圖至第8圖係本發明製造晶片堆疊結構之示意圖；及第9圖係本發明製造晶片堆疊結構之流程圖。
請參閱第2圖，所示為本發明第一實施例之晶片堆疊結構2之剖面示意圖，其係為包含一光學晶片模組21及一訊號處理晶片模組23所堆疊組成之結構。
其中，訊號處理晶片模組23係包含一玻璃基板231及一訊號處理晶片233，該訊號處理晶片233較佳係一數位訊號處理器(digital signal processor，DSP)晶片。為方便說明，進一步定義該玻璃基板231具有一第一表面231a、以及與該第一表面231a相對之一第二表面231b，玻璃基板231更形成有複數貫穿孔(through hole)235，其內鍍有金屬材料以連接該第一表面231a及該第二表面231b。
玻璃基板231之第一表面231a上更形成一凹穴237，以供訊號處理晶片233設置於該凹穴237中。凹穴237內亦形成鍍有金屬材料之貫穿孔235，而該訊號處理晶片233更包含複數導電接點233a，例如習知之凸塊，相應地電性連接至對應之貫穿孔235。
較佳地，晶片堆疊結構2更包含一導電線路層25及複數銲球27，該導電線路層25形成於玻璃基板231之第二表面231b上，以選擇性地電性連接該等貫穿孔235，而銲球27係形成於該導電線路層25上之適當位置。
而光學晶片模組21係包含一光學晶片213，較佳係為一影像感測(CMOS imaging sensor，CIS)晶片，該光學晶片模組21係於訊號處理晶片模組23之第一表面231a上，與訊號處理晶片模組23疊置，且該光學晶片213之面積係大於該訊號處理晶片233之面積， 以涵蓋該訊號處理晶片233，使光學晶片213之導電接點233a得以準確地對應連接於訊號處理晶片233外側的部分貫穿孔235。同樣地，該光學晶片213亦可包含複數導電接點213a，例如習知之凸塊，相應地連接至對應之部分貫穿孔235。
為穩固地結合該訊號處理晶片模組23與該光學晶片模組21，本發明之晶片堆疊結構2較佳更包含一黏著層29，施加於訊號處理晶片模組23與光學晶片模組21之間。
如此一來，透過該等貫穿孔235及導電線路層25，光學晶片213與訊號處理晶片233得以於玻璃基板231之第二表面231b上電性連接。
接下來將說明本發明之第二實施例，其係用於製造前述晶片堆疊結構2之方法，以下將配合第3圖至第8圖之示意圖以及第9圖之流程圖，一併說明。
首先，如第9圖之步驟901及第3圖所示，提供一玻璃基板231，其上形成複數貫穿孔235及複數個凹穴237以供複數個訊號處理晶片233設置；其中，該玻璃基板231具有第一表面231a、以及與該第一表面231a相對之第二表面231b，該等凹穴237係依據一佈局形成於第一表面231a上，凹穴237與第一表面231a上之該等貫穿孔235係內鍍金屬材料，以於第一表面231a及第二表面231b上形成接點，該等訊號處理晶片233分別嵌設於凹穴237內以與對應之貫穿孔235電性連接。
然後進行步驟902，於玻璃基板231之第二表面231b上形成導電線路層25，以選擇性地電性連接該等貫穿孔235。
接著，如第9圖之步驟903及第4圖所示，提供一晶圓210(通常包含一矽基板)，其中，該晶圓210上形成有複數個光學晶片213。如第一實施例所說明，光學晶片213更包含並顯露出複數導電接點213a，該導電接點213a可為習知之凸塊，例如：金凸塊、鍚球、銅凸塊、銀凸塊、複合金屬凸塊或結線凸塊等等。
然後如第9圖之步驟904及第5圖所示，疊合玻璃基板231及晶圓210，使對應之光學晶片213及訊號處理晶片233，經由該等貫穿孔235電性連接。更明確而言，此步驟係將晶圓210貼合於玻璃基板231之第一表面231a上，使光學晶片213之導電接點213a，連接至相對應之貫穿孔235。
疊合後之結構，如第6圖之剖面圖所示。其中，各光學晶片213包含複數導電接點213a，各訊號處理晶片233包含複數導電接點233a，該疊合玻璃基板231及晶圓210之步驟，係將該等導電接點213a、233a對準並電性連接至對應之貫穿孔235。
較佳地，於進行步驟904之疊合製程時，更施加黏著層29於玻璃基板231及晶圓210之間，以利其相互結合，其中，該黏著層29可為一填充膠材(Underfill)。於本發明之另一較佳實施例中，該黏著層29可為一半固化之兩階段特性黏膠(B-Stage)預設於晶圓凸塊之周圍，於疊合玻璃基板231及晶圓210時一併固化該黏著層29，以增加該光學晶片213與訊號處理晶片23彼此間之結合性。
接下來，如第9圖之步驟905及第7圖所示，研磨晶圓210背面，以減少其整體厚度。
最後，如第8圖所示，先執行步驟906，於導電線路層25上植入複數銲球27，再執行步驟907，切割疊合後之玻璃基板231及晶圓，而最終製成第一實施例之晶片堆疊結構2。無疑地，晶片堆疊結構2包含光學晶片21及訊號處理晶片23所組成，光學晶片21如影像感測(CMOS imaging sensor，CIS)晶片，訊號處理晶片23如數位訊號處理器(digital signal processor，DSP)晶片。
綜上所述，本發明所揭露之晶片堆疊結構及其製造方法，改以於晶圓時直接堆疊後切割以形成堆疊晶片之封裝結構，不僅可節省晶片堆疊結構的配置空間及所佔面積，亦可大幅簡化製程及降低成本，更可提高晶片堆疊結構的可靠度及穩定性。
上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利保護範圍應以申請專利範圍為準。
2‧‧‧晶片堆疊結構
21‧‧‧光學晶片模組
213‧‧‧光學晶片
213a‧‧‧導電接點
23‧‧‧訊號處理晶片模組
231‧‧‧玻璃基板
231a‧‧‧第一表面
231b‧‧‧第二表面
233‧‧‧訊號處理晶片
233a‧‧‧導電接點
235‧‧‧貫穿孔
237‧‧‧凹穴
25‧‧‧導電線路層
27‧‧‧銲球
29‧‧‧黏著層

Claims (10)

  1. 一種晶片堆疊結構，包含：一訊號處理晶片模組，包含：一玻璃基板，具有一第一表面、以及與該第一表面相對之一第二表面，該第一表面上更形成一凹穴，其中，該玻璃基板的第一表面與該凹穴內分別形成有貫穿孔(through hole)，並於該貫穿孔內鍍有金屬材料以電性連接該第一表面及該第二表面；及一訊號處理晶片，設置於該凹穴中與該些貫穿孔電性連接；及一光學晶片模組，包含一光學晶片，該光學晶片模組於該第一表面上與該訊號處理晶片模組疊置，該光學晶片之面積係大於該訊號處理晶片之面積，以涵蓋該訊號處理晶片；其中，該訊號處理晶片及該光學晶片更分別包含複數導電接點相應地連接該等貫穿孔，以於該第二表面上電性連接。
  2. 如請求項1所述之晶片堆疊結構，其中該等導電接點係為複數凸塊。
  3. 如請求項1所述之晶片堆疊結構，更包含一導電線路層及複數銲球，該導電線路層形成於該第二表面上，以選擇性地電性連接該等貫穿孔，而該複數銲球形成於該導電線路層上。
  4. 如請求項1所述之晶片堆疊結構，更包含一黏著層，施加於該訊號處理晶片模組與該光學晶片模組之間，以結合該訊號處理晶片 模組與該光學晶片模組。
  5. 一種製造一晶片堆疊結構之方法，包含下列步驟：提供一玻璃基板，其中，該玻璃基板具有一第一表面、以及與該第一表面相對之一第二表面，並依據一佈局於第一表面上形成複數個凹穴，該等凹穴與該第一表面上設有內鍍金屬材料之複數貫穿孔，其中，複數個訊號處理晶片分別嵌設於該等凹穴中以與該等貫穿孔電性連接；提供一晶圓，其中，該晶圓上形成有複數個光學晶片；及疊合該玻璃基板及該晶圓，使對應之該光學晶片及該訊號處理晶片，經由該等貫穿孔電性連接。
  6. 如請求項5所述之方法，其中，該疊合該玻璃基板及該晶圓之步驟，係將該晶圓貼合於該玻璃基板之第一表面上。
  7. 如請求項6所述之方法，其中該疊合該玻璃基板及該晶圓之步驟，包含：施加一黏著層於該玻璃基板及該晶圓之間。
  8. 如請求項5所述之方法，其中該提供一玻璃基板之步驟，更包含：於該第二表面上形成一導電線路層，以選擇性地電性連接該等貫穿孔。
  9. 如請求項5所述之方法，其中於該疊合該玻璃基板及該晶圓之步驟之後，更包含：研磨該晶圓； 於該導電線路層上，植入複數銲球；以及切割疊合後之該玻璃基板及該晶圓。
  10. 如請求項5所述之方法，其中各該訊號處理晶片及各該光學晶片更分別包含複數導電接點，該疊合該玻璃基板及該晶圓之步驟，係將該等導電接點對準並電性連接至該等貫穿孔。
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