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TWI451547B - 基板結構及其製法 - Google Patents

基板結構及其製法 Download PDF

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TWI451547B
TWI451547B TW101106927A TW101106927A TWI451547B TW I451547 B TWI451547 B TW I451547B TW 101106927 A TW101106927 A TW 101106927A TW 101106927 A TW101106927 A TW 101106927A TW I451547 B TWI451547 B TW I451547B
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layer
copper
nickel
substrate
substrate body
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TW101106927A
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TW201338111A (zh
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洪良易
白裕呈
蕭惟中
林俊賢
孫銘成
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矽品精密工業股份有限公司
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Priority to TW101106927A priority Critical patent/TWI451547B/zh
Priority to US13/534,620 priority patent/US20130228921A1/en
Publication of TW201338111A publication Critical patent/TW201338111A/zh
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
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Description

基板結構及其製法
本發明係有關於一種基板結構及其製法，尤指一種藉由銲球對外電性連接之基板結構及其製法。
為符合現今電子產品輕薄短小之發展趨勢，同時有效縮小半導體封裝結構的尺寸，業界發展出一種球柵陣列半導體封裝結構，其係將半導體晶片設置於基板本體的一表面上，並藉由複數銲線將該半導體晶片電性連接至基板，且於該基板本體之另一表面之電性連接墊上形成銲球，該銲球係用以連接其他電子裝置，例如電路板或另一封裝結構。
請參閱第1A至1B圖，係習知之基板結構之電性連接墊之剖視圖(基板結構省略而未圖示)。
如第1A圖所示，該電性連接墊係包括依序層疊之銅層11、鎳層12與金層13。
如第1B圖所示，將助銲劑14塗佈在該金層13上，並藉由該助銲劑14將銲球15沾黏在該金層13上，接著，進行回銲步驟，由於該金層13較薄且擴散速度也較快，因而回銲過程中，該金層13會溶解進入銲球15，且該銲球15會與鎳層12形成接合層16以完成銲接的動作，該接合層16包含鎳錫合金，故具有較高的熱傳導性與較低的應力耐受性，因此在落下試驗(drop test)時，該銲球容易脫落。
請參閱第2A至2B圖，係另一習知之基板結構之電性連接墊之剖視圖(基板結構省略而未圖示)。
如第2A圖所示，該電性連接墊係包括依序層疊之銅層21與有機保焊劑(Organic Solderability Preservative，簡稱OSP)層22。
如第2B圖所示，將助銲劑23塗佈在該有機保焊劑層22，並藉由該助銲劑23將銲球24沾黏在該有機保焊劑層22上，接著，進行回銲步驟，該有機保焊劑層22與助銲劑23會在回銲過程中揮發，因該助銲劑23的任務是清潔該銅層21表面以使其外露新鮮的表面，促使該銲球24與銅層21之間形成接合層25，該接合層25包含銅錫合金，故具有較高的應力耐受性與較低的熱傳導性，因此在落下試驗時，該銲球較不容易脫落。
惟，在第2B圖之結構中，與該金層13相比較，該有機保焊劑層22較容易氧化及吸濕，故保存期限較短，使得後續製程之銲球24接合性的可靠度下降，最終導致產品的出現問題。
因此，如何避免上述習知技術中之種種問題，俾解決基板結構的落下試驗結果不良與保存期限較短的問題，實已成為目前亟欲解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種基板結構，係包括：基板本體；以及設於該基板本體之表面上的複數電性連接墊，該電性連接墊係包括依序堆疊之第一銅層、鎳層、第二銅層與金層，且該第二銅層之厚度小於該第一銅層之厚度。
本發明復提供另一種基板結構，係包括：基板本體；設於該基板本體之表面上的複數電性連接墊，該電性連接墊係包括依序堆疊之銅層與鎳層；接合層，係形成於該電性連接墊上；以及銲球，係形成於該接合層上。
本發明復提供一種基板結構之製法，係包括：提供一基板本體；以及於該基板本體之表面上依序形成第一銅層、鎳層、第二銅層與金層，且該第二銅層之厚度小於該第一銅層之厚度。
本發明復提供一種基板結構，係包括：基板本體；以及設於該基板本體之表面上的複數電性連接墊，該電性連接墊係包括依序堆疊之銅層、鎳銅混合層與金層，其中，該鎳銅混合層係含有少量銅的鎳層，亦即銅含量低於鎳的含量。
本發明復提供又一種基板結構，係包括：基板本體；設於該基板本體之表面上的複數電性連接墊，該電性連接墊係包括依序堆疊之銅層與鎳銅混合層，其中，該鎳銅混合層的銅含量低於鎳的含量；接合層，係形成於該電性連接墊上；以及銲球，係形成於該接合層上。
本發明復提供另一種基板結構之製法，係包括：提供一基板本體，於該基板本體之表面上設有複數電性連接墊，該電性連接墊係包括銅層；以及於該銅層上依序形成鎳銅混合層與金層，其中，該鎳銅混合層的銅含量低於鎳的含量。
由上可知，由於本發明之基板結構的電性連接墊之表面處除了有鎳與金之外，又包含少量的銅，使得銲球與電性連接墊之間的接合層由原本的以四錫化三鎳(Ni3 Sn4 )為主轉變成以五錫化六銅(Cu6 Sn5 )為主，而具有較佳的結合性，又因為本發明的基板結構的電性連接墊之表面係為金，而可延緩氧化及吸濕的現象，所以本發明之基板結構也具有保存期限較長之優點。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第一實施例
請參閱第3A至3E圖，係本發明之基板結構及其製法之第一實施例的剖視圖。
首先，如第3A圖所示，提供一基板本體30，於該基板本體30之表面上設有複數電性連接墊31(本圖以一電性連接墊31作說明)，該電性連接墊31係包括依序堆疊之第一銅層311與鎳層312。
如第3B圖所示，接著，於該鎳層312上依序形成第二銅層313與金層314，且該第二銅層313之厚度小於該第一銅層311之厚度。
如第3C圖所示，於該金層314上形成助銲劑32，於該助銲劑32上植接銲球33。
如第3D圖所示，進行回銲步驟，使得該助銲劑32揮發，該金層314溶解進入該銲球33，且該第二銅層313亦溶解，而於該銲球33與鎳層312之間形成接合層34，該接合層34之材質包括五錫化六銅341與含量低於該五錫化六銅341之四錫化三鎳342；要注意的是，此處係呈現該接合層34的放大形態，主要是方便示意，而非用以限制其形狀。
如第3E圖所示，於該基板本體30設有該電性連接墊31之相對側上設置晶片35，並以銲線36將該晶片35電性連接該基板本體30，且形成包覆該晶片35與銲線36的封裝材料37。
本發明復提供一種基板結構，係包括：基板本體30；以及複數電性連接墊31，係設於該基板本體30之表面上，該電性連接墊31係包括依序堆疊之第一銅層311、鎳層312、第二銅層313與金層314，且該第二銅層313之厚度小於該第一銅層311之厚度。
於前述之基板結構中，復可包括助銲劑32，係形成於該金層314上，且復包括銲球33，係設於該助銲劑32上。
本發明復提供另一種基板結構，係包括：基板本體30；複數電性連接墊31，係設於該基板本體30之表面上，該電性連接墊31係包括依序堆疊之第一銅層311與鎳層312；接合層34，係形成於該電性連接墊31上；以及銲球33，係形成於該接合層34上。
所述之基板結構之該接合層34之材質包括五錫化六銅341與含量低於該五錫化六銅341之四錫化三鎳342。
第二實施例
請參閱第4A至4D圖，係本發明之基板結構及其製法之第二實施例的剖視圖。
首先，如第4A圖所示，提供一基板本體40，於該基板本體40之表面上設有複數電性連接墊41，該電性連接墊41係包括銅層411。
如第4B圖所示，接著，於該銅層411上依序形成鎳銅混合層412與金層413，其中，該鎳銅混合層412的銅含量低於鎳的含量。
如第4C圖所示，於該金層413上形成助銲劑42，於該助銲劑42上植接銲球43。
如第4D圖所示，進行回銲步驟，使得該助銲劑42揮發，該金層413溶解進入銲球43，且該銲球43與鎳銅混合層412之間形成接合層44，該接合層44之材質包括五錫化六銅441與含量低於該五錫化六銅441之四錫化三鎳442；要注意的是，此處係呈現該接合層44的放大形態，主要是方便示意，而非用以限制其形狀。
要注意的是，本實施例亦可如前一實施例地於該基板本體40設有該電性連接墊41之相對側上設置晶片(未圖示)並進行封裝等步驟，惟其具體實施內容係所屬技術領域之通常知識者所能瞭解，故不在此加以贅述與圖示。
本發明復提供一種基板結構，係包括：基板本體40；以及複數電性連接墊41，係設於該基板本體40之表面上，該電性連接墊41係包括依序堆疊之銅層411、鎳銅混合層412與金層413，其中，該鎳銅混合層412的銅含量低於鎳的含量。
於前述之基板結構中，復可包括助銲劑42，係形成於該金層413上，且復包括銲球43，係設於該助銲劑42上。
本發明復提供另一種基板結構，係包括：基板本體40；複數電性連接墊41，係設於該基板本體40之表面上，該電性連接墊41係包括依序堆疊之銅層411與鎳銅混合層412，其中，該鎳銅混合層412的銅含量低於鎳的含量；接合層44，係形成於該電性連接墊41上；以及銲球43，係形成於該接合層44上。
所述之基板結構之該接合層44之材質包括五錫化六銅441與含量低於該五錫化六銅441之四錫化三鎳442。
綜上所述，相較於習知技術，由於本發明之基板結構的電性連接墊之表面處除了有鎳與金之外，又包含少量的銅，使得銲球與電性連接墊之間的接合層由原本的以四錫化三鎳為主轉變成以五錫化六銅為主，而具有較佳的銲球結合性(即落下試驗結果較佳)；又因為本發明的基板結構的電性連接墊之表面係為金，而可延緩氧化及吸濕的現象，所以本發明之基板結構也具有保存期限較長之優點。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
11,21,411．．．銅層
12,312．．．鎳層
13,314,413．．．金層
14,32,42‧‧‧助銲劑
15,24,33,43‧‧‧銲球
16,25,34,44‧‧‧接合層
22‧‧‧有機保焊劑層
23‧‧‧助銲劑
30,40‧‧‧基板本體
31,41‧‧‧電性連接墊
311‧‧‧第一銅層
313‧‧‧第二銅層
341,441‧‧‧五錫化六銅
342,442‧‧‧四錫化三鎳
35‧‧‧晶片
36‧‧‧銲線
37‧‧‧封裝材料
412‧‧‧鎳銅混合層
第1A至1B圖係習知之基板結構之電性連接墊之剖視圖；
第2A至2B圖係另一習知之基板結構之電性連接墊之剖視圖；
第3A至3E圖係本發明之基板結構及其製法之第一實施例的剖視圖；以及
第4A至4D圖係本發明之基板結構及其製法之第二實施例的剖視圖。
30．．．基板本體
31．．．電性連接墊
311．．．第一銅層
312．．．鎳層
313．．．第二銅層
314．．．金層

Claims (21)

  1. 一種基板結構，係包括：基板本體；以及複數電性連接墊，係設於該基板本體之表面上，該電性連接墊係包括依序堆疊之第一銅層、鎳層、第二銅層與金層，且該第二銅層之厚度小於該第一銅層之厚度。
  2. 如申請專利範圍第1項所述之基板結構，復包括助銲劑，係形成於該金層上。
  3. 如申請專利範圍第1項所述之基板結構，復包括晶片，係設於該基板本體上，且電性連接該基板本體。
  4. 一種基板結構，係包括：基板本體；複數電性連接墊，係設於該基板本體之表面上，該電性連接墊係包括依序堆疊之銅層與鎳層；接合層，係形成於該電性連接墊上，且係由較該銅層之厚度為薄的另一銅層溶解而形成為包括五錫化六銅與含量低於該五錫化六銅之四錫化三鎳的材質；以及銲球，係形成於該接合層上。
  5. 如申請專利範圍第4項所述之基板結構，復包括晶片，係設於該基板本體上，且電性連接該基板本體。
  6. 一種基板結構之製法，係包括：提供一基板本體；以及 於該基板本體之表面上依序形成第一銅層、鎳層、第二銅層與金層，且該第二銅層之厚度小於該第一銅層之厚度。
  7. 如申請專利範圍第6項所述之基板結構之製法，復包括於該金層上形成助銲劑。
  8. 如申請專利範圍第7項所述之基板結構之製法，復包括於該助銲劑上設置銲球，並進行回銲步驟，使得該助銲劑揮發，該金層溶解進入該銲球，且該第二銅層溶解，而於該銲球與該鎳層之間形成接合層。
  9. 如申請專利範圍第8項所述之基板結構之製法，其中，該接合層之材質包括五錫化六銅與含量低於該五錫化六銅之四錫化三鎳。
  10. 如申請專利範圍第6項所述之基板結構之製法，復包括於該基板本體上設置晶片，且該晶片電性連接該基板本體。
  11. 一種基板結構，係包括：基板本體；以及複數電性連接墊，係設於該基板本體之表面上，該電性連接墊係包括依序堆疊之銅層、鎳銅混合層與金層，其中，該鎳銅混合層的銅含量低於鎳的含量。
  12. 如申請專利範圍第11項所述之基板結構，復包括助銲劑，係形成於該金層上。
  13. 如申請專利範圍第11項所述之基板結構，復包括晶片，係設於該基板本體上，且電性連接該基板本體。
  14. 一種基板結構，係包括：基板本體；複數電性連接墊，係設於該基板本體之表面上，該電性連接墊係包括依序堆疊之銅層與鎳銅混合層，其中，該鎳銅混合層的銅含量低於鎳的含量；接合層，係形成於該電性連接墊上；以及銲球，係形成於該接合層上。
  15. 如申請專利範圍第14項所述之基板結構，其中，該接合層之材質包括五錫化六銅與含量低於該五錫化六銅的四錫化三鎳。
  16. 如申請專利範圍第14項所述之基板結構，復包括晶片，係設於該基板本體上，且電性連接該基板本體。
  17. 一種基板結構之製法，係包括：提供一基板本體，於該基板本體之表面上設有複數電性連接墊，該電性連接墊係包括銅層；以及於該銅層上依序形成鎳銅混合層與金層，其中，該鎳銅混合層的銅含量低於鎳的含量。
  18. 如申請專利範圍第17項所述之基板結構之製法，復包括於該金層上形成助銲劑。
  19. 如申請專利範圍第18項所述之基板結構之製法，復包括於該助銲劑上設置銲球，並進行回銲步驟，使得該助銲劑揮發，該金層溶解進入該銲球，且該銲球與鎳銅混合層之間形成接合層。
  20. 如申請專利範圍第19項所述之基板結構之製法，其 中，該接合層之材質包括五錫化六銅與含量低於該五錫化六銅的四錫化三鎳。
  21. 如申請專利範圍第17項所述之基板結構之製法，復包括於該基板本體上設置晶片，且該晶片電性連接該基板本體。
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