TWI304694B - A method and apparatus for ensuring high quality audio playback in a wireless or wired digital audio communication system - Google Patents

Description

MODIFICATION 1304694 IX. DESCRIPTION OF THE INVENTION: 1. Field of the Invention The present invention relates to a device and method for transmitting and receiving digital data communication signals, and more particularly to synchronizing the received digital data communication signals (synchroni zat丨on) ). [Prior Art] For most wireless or wired systems, the transmission and reception of digital data is not complicated. However, due to the is〇chronous nature of the audio necessary conditions, it is more difficult to transmit the digital audio data and reliably transmit the sound back to the receiver. In addition, the recording and playback system uses standard sound digital data to transmit to the analog converter to maintain audio (audioci〇ck), which requires periodic pulse code modulation to maintain a smooth recording and playback. For a wireless transmitter and a receiver that does not perform a frequency recovery from the transmitted signal, the transmitter's audio system is different from the receiver's audio, so the rate and consumption of digital data is reduced. one question. The frequency of the transmitter may over-supply digital data at a faster rate than the digital data consumed by the receiver, or the frequency of the transmitting device may supply insufficient data at a slower rate to make the digital data of the receiving device scarce. As shown in the first figure, an example of a digital data communication system is a wireless infrared digital sound headset 25. The transmitter 10 needs to digitally decode the audio signal formatted by the synchronization signal, the control signal and the error signal. The formatted decoded data is adjusted to a transmitted signal using pulse positioned modulation. The adjusted transmission signal is used to control the propagation of the light signal 2 emitted from the LED 15. The optical signal 2 is broadcast to the headset 25' and the headset 25 has a photodetector 40. The optical debt detector 40 is typically located on the outside of the headset 25 for receiving optical signals. The detection signal of the optical pre-detector 40 is transmitted to the receiver 30, and the demodulated and reformatted decoded audio signals are converted to the flavor Xspeakers 35a and 35b. The flavors 35a and 35b are located near the ear of a person 45 wearing the headset 25. The wireless transmission of digital data is often accomplished by continuously translating the formatting of the digital data to the 1304694 formatted frame. For example, the Infrared Data Association (irDA), the system listed in the "Serial Infrared Physical Layer Specification,", May 2001, as listed in the 1st edition, has a lead as shown in the architecture of 5.4.2. A Preamble Field (PA), a Start Flag Field (FA), a Data Field (DD), and a Stop Flag Field. The Receiver 30 uses the Preamble Field to receive The clocking system of the device 30 is synchronized to the incoming message. In general, a phase-locked loop oscillator (phase i〇ck ι〇ορ oscillator) is used to synchronize the receiver 30 to the leading bit field. When the preamble field is detected and the receiver 30 is synchronized, the receiver 30 will begin to detect the Start Flag Field to establish symbol synchronization. If the start flag field is correct, the receiver 30 will continue. Start receiving the data symbol of the data field (DataFieid), and continue to receive until the stop flag field (St〇p Flag Field) is received. The second figure is an idealized transfer diagram description of a digital data. In time During the period i, the first frame ADO of the digital data symbol is generated by the sampling of the analog analog signal and the result of the conversion sampling into a digital decoding representing the analog signal size. During the time period, the interleave is interleaved. The block symbol is decoded with an error correction code ECCE. At the same time, a second frame ship is sampled and converted into a symbol of a digital data. During time period 3, the interleaved and decoded data frame is used to adjust A transmission signal RF T0 is played by the LED 15 from the transmitting device 1 through the air to the LED 42 of the headset 25. Ideally, this situation occurs immediately during the period 3. The receiver device 30 is restored. The transmitted signal and the symbol frame for restoring the received data. At the same time, the second frame of the data is interleaved and decoded with an error correction code ECCE1, and the second sample AD2 is converted into the digital data. During the period 4, the received data RF R0 is deinterleaved, and there is an error correction, and the symbol frame for receiving and recovering the original digital signal ECCD0 is performed. At the same time, the interleaved and decoded frame of the material ECCE1 adjusts the transmitted transmission signal RFTi. The transmission signal RF T1 is received and the frame ri is replied. At the same time, the third frame of the symbol is Interleaving and error correction JL decoding, the opposite side of the frame 2, and a first revision of the _ 130 130 1 146 464 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 During the time period, the original data ECCD0 symbol frame is converted into an analog signal ad〇 for use on the speakers 35a and 35b. For each time period %..., η·continuous sequence, like the process of receiving digital data by sampling analog signal; interleaving and decoding digital data with error correction code; adjusting and transmitting digital data; receiving and restoring digital data Data; interleaving and decoding digital data and correcting errors in digital data; converting digital data into an analog signal for transmission to Lakou 8 35a and 35b. In 5.4·1, “Serial Infrared Physical Layer

The Specification specifies the decoding of the data. The four-pulse position modulation is used to transmit the digital data. In this example, a two-bit signal is decoded by locating a pulse signal within a symbol. Data structure. Each position represents a binary hexadecimal decoding, which is divided into four time positions during the duration of the symmetry. The 刖 pilot field, the start flag field and the stop flag field are all unique codes. , which has symbol streams, and does not confuse this symbol stream with the four-pulse position adjustment device of the two-bit data structure. The synchronization of the receiver using the phase-locked loop is delayed by the local receiver frequency jitter. (jitter) is affected by the frequency of the transmitted data. Furthermore, any shift of the local money device (1 〇 (^ os^llator) will cause the earthquake to be re-locked periodically. Without this earthquake, the signal is periodically re-fixed, and there will be errors in data reception. Moreover, the multi-path reception problem causes the received (10) sequence data "(tiffling data) to follow the path. Delays in the change of the difference. Daxue knows that the Shenfu County (elGek reeGvery) is not perfect. Due to the interference of the transmission path, when the receiver in the wireless environment cannot access the data phase-locked loop, the synchronization is transmitted. This transmission will cause this digital data loss or X to be corrupted. The fine suppression technique _ light loss of the digital data symbol, and therefore the frequency synchronization. (9) ^Special number 5,457,718 (Ande, et al.) teach one A simple phase recovery structure, which is a fine-digit circuit. The phase-recovery circuit is a real-time integrated-body-corrected digital 1346949 digital filter, which is activated by a phase comparator (fine ec〇 s ator). To provide - phase-locked loop and data retiming, function. This number is provided by the wave device. "The function of data timing re-spinning is transmitted through the transmission of the four-bit juicer to the iB-to-digit delay tillage, and the whistling delay. The data signal is output and input between the phase comparators. When the data is asynchronous with respect to the local clock (1〇cal clock), the ugly slaves are the binary of her, and the required phase repair is determined. The polarity is then sent back to the delay element. The delay element then adjusts the phase of the incoming data relative to the local clock phase. US Patent No. 5,887,040 (Jung, et al.) provides a high speed digital data timing device (digital data) Retiming apparatus), its binary data can be re-timed in a stable manner, even if static skew (staticsk & ¥) is due to the difference between the clock pulse and data in the timing re-determination, and this data is dynamic in the field Dynamic skew is a change in characteristics due to time and temperature. The external clock pulse is delayed by a delay region, so the execution of the system is independent of the form of the data. If the data phase shows a continuous wandering for more than a certain period of time, an elastic buffer absorbs the difference, so there is no data loss. U.S. Patent No. 5,886,552 (Chai, et al.) discloses a data timing retiming circuit that uses a plurality of frequencies from a voltage controlled oscillator of a phase-locked loop to enable more efficient timing reconfiguration. External input data. U.S. Patent No. 5,608,357 (Ta, et al.) teaches a data timing reconfiguration system that is responsible for timing re-introduction of incoming data and jitter removal. The data timing re-routing system includes a local clock; a phase aiigner for receiving incoming data and generating a recovered frequency from the incoming data, and then using the recovered frequency timing Resizing the incoming data to generate incoming data with time series re-sequence; and a buffer memory, which stores the incoming data that has been re-scheduled by the timing, and the incoming data that is re-equalized from the timing is The jitter is moved to the buffer memory, and the data stored from the buffer memory is read in accordance with the local frequency. Even at very high data rates, data timing reconfiguration provides reliable operation.

nLow-Latency Plesiochronous Data 1304694 Revised by Dennison et al.

Retiming", published in the 1995 Proceedings of the VLSI Conference on Advanced Studies in March 1995, was attached on April 2, 2002. Mit. Edu/pub/cva/plesio. Ps. On the Z website, I found the paper presented by Dennison et al. Dennison et al. re-received the received data by delaying the data, so the data can be intercepted by the receiving device frequency. In October 1995, Sarmenta et al. published a paper entitled "Rational cl〇cking" at the IEEE International Conference on Computer Design, describing the maintenance of a known phase relationship between clock frequencies and rational factors, and There is no run-time arbitration contest, and the relative phase is used to predict the predictability of time communication. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method and apparatus for ensuring ifjna sound recording and playback in a wireless or wired digital sound communication system, which synchronizes received and replied data from a transmission medium to a data center. The transmission medium to which it is transmitted. Another object of the present invention is to provide a method and apparatus for ensuring high quality sound recording and playback in a wireless or wired digital sound communication system, and data received and replied from a transmission medium is different even when the transmission clock and the reception clock are different. There will also be no under-run or overrun. To achieve the above and other objects, the present invention provides a method and apparatus for ensuring quality sound recording and playback in a wireless or wired digital sound communication system, the communication system comprising a data communication system having a transmitter and a receiver. The transmitter includes a frame formatter and a transport component. This frame formatter decodes the digital data into consecutive symbols. The decoding of digital data includes interleaving digital data and providing error detection and correct encoding. The transport component is responsible for & the sash sash "to receive this continuous 槪, and to transmit _ the continuous adjustment signal. The receiver is responsible for contacting the transmitter for receiving the adjustment signal, re-storing the adjustment signal and reconstructing the symbol of the digital data of the adjustment signal, and synchronizing the digital data to a first reference signal. The receiver has an amplification and adjustment circuit, and an adjustment circuit for receiving, re-storing, and sampling the adjustment signal (c〇nditi (5) ing 1304694 to correct the circuit). The adjustment signal is sampled in the plurality of first reference signals, so that within the adjustment signal, a transition between the bits representing the boundary in the digital data is detected, and the digital data is reconstructed and synchronized to the second reference signal. Once the amplification and adjustment circuitry reconstructs and synchronizes the digital data, the digital data is forwarded to a buffer data retention circuit, so that the reconstructed digital data is retained. The buffer data retention circuit has at least one buffer circuit for retaining the symbol group. The digital data is transferred from the buffer data retention circuit to a data correction and interleaving circuit for reorganizing the digital data to the original continuous symbol. The data correction and interleaving circuitry will further correct any errors in the transmission of the tuning signal. Based on the interleaving and correction of the digital data, the reorganized and corrected digital signals are replaced in the buffer data retention circuit. The μ-boundary marker signal detection circuit is responsible for contacting the amplification and adjustment circuit to receive the reconstructed digital data. From the reconstructed digital data, the boundary mark signal detecting circuit extracts a mark signal indicating the boundary of the mark of the digital data. This flag signal provides a time indication that the transmitting device is playing digital data. The receiver has a jitter management unit that synchronizes the digital data to the first reference signal. The jitter management unit has a first-in first-out (FIF) data retention component that receives and reconstructs digital data from the buffer data retention circuit at a rate of the first reference signal, and transmits the synchronized digital data in order to approach the third reference signal. The rate is further advanced, wherein the speed of the second reference 接近 is close to the time of transmitting the digital data. The jitter management unit has a - adjustable reference 峨 generator, which is connected with the _ data retention component _ digital __ sister Tixiang two reference base. The buffer data retention circuit transfers the digital data to the FIFO data retention component, until the FiF0 data retention component contains the -number of the digital data (approximately half of the component capacity of the fifq data (four)). Then the FIFO data retention component starts transmitting the digital data. . In addition, the buffer data retention circuit must be two marked positions, and the number of digits (10) is converted to avoid all digits (GVemin). In order to complete the face _ record to reduce the signed conversion, the buffer f escaping must be 健 健 健 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , This prevents the data overflow that is converted to the buffer data retention circuit. The beta jitter management unit has a generator management circuit (generat〇rc〇ntr〇l circuit) for receiving the signal from the adjustment signal through the boundary marker signal detection circuit. Mark the signal. The generator management circuit is further operative to contact the FIF0 data retention component to receive an occupancy signal indicative of the amount of digital data present within the FIFO data retention component. From the mark signal and the occupation signal, the generator management circuit generates a generator control signal, resulting in adjustment of the adjustable reference signal generator, so the second reference signal synchronizes the digital data to the time when the digital data is transmitted. point. If the occupant signal indicates that the FIFO data retention component contains a second amount of digital data (approximately half of the FIFO data retention component capacity), the generator control circuit causes the generator control signal to be indicated by the tunable reference signal generator There is no adjustment to the second reference signal. However, if the occupation signal indicates that the FIF0 data retention component contains less than the second number of digital data, the control circuit generates a generator control signal to adjust the second reference signal to increase the FIFO data retention component by using the variable reference signal generator. Capacity until the FIFO data retention element contains a second quantity equal to the digit data. Conversely, 'if the occupancy signal indicates that the FIFO data retention component contains a second quantity greater than the digital data, the generator control circuit generates a generator control signal indicating the adjustable reference signal generator, and the second reference signal should be adjusted to reduce the FIF. The data retains the capacity of the component until the FIFO data retention component contains a second amount equal to the digital data. [Embodiment] The present invention provides a communication system that can be applied to wired or wireless digital audio communication, and provides digital data with isochronous timing (is〇chr〇n〇us timing) for high-quality sound recording and playback. The communication system includes a transmitter and a receiver, and both the transmitter and the receiver will use their own local clock for communication. In addition, the receiver includes a jitter management unit, and the jitter management unit includes a first in first out (FIFO) data retention component or buffer, and a standard voltage controlled crystal oscillator (VCX0). And a VCX0 control logic unit. The jitter management unit tracks the transmitter's audio by using a FIFO buffer, and is easily implemented or incorporated into a digital sound system that separates the sound recording and playback and source. The revision 1304694 FIFO buffer is similar to a container, and the manufacturer (receiver) dumps the digital data symbol of the analog sound signal with a clock cycle rate equal to the receiver. Initially, the container is empty, and the consumer (player) will not begin until the digital data symbol has reached the threshold. Once the digital data symbol reaches this level, the consumer will begin to consume digital data symbols. In theory, if the manufacturer and the consumer operate at the same rate, then the FIFO buffer or container criteria will always be at the threshold standard because the receivers receive and output at the same rate. ^ However, if the manufacturer speeds up and the digital data symbols are transferred to the FIF0 buffer faster, and the consumer still captures the digital data at a slower container rate, the container 〇r FIFO buffer will increase the level. . When this level is increased by the FIF buffer, the FIFO buffer will overflow and the overflow of the digital data symbols will result in loss of digital data. Conversely, if the manufacturer's rate is slower than the consumer and the digital data symbol is sent to the FIFO buffer more slowly, and the consumer still captures the digital data at a faster container rate, the container or FIFO buffer will be at the same level. cut back. When this level of FIF buffer is reduced, the FIFO buffer will be empty and the lack of digital data symbols will cause the recording and playback process to stop 'until the manufacturer supplies more digital data symbols, so the isochronous digits Distortion during recording and playback of data symbols. If the FIFO buffer has an indication of the level of the existing digital data symbols within it' then the consumer can adjust by the rate at which the digital data is removed from the FIFO buffer. If an intermediate region between the upper and lower limits is referred to as the applicable zone (c〇mf〇rt zone), the consumer does not change with the rate at which the digital sampling result is removed from the FIF buffer. However, when the amount of data existing in the FIFO buffer exceeds the upper or lower limit, the consumer must increase or decrease the rate of consumption of the digital data symbols from the FIF0 buffer. For example, if the manufacturer provides a digital data symbol to the FIF buffer faster than the consumer is sampling the digital data symbols, the FIF buffer will exceed the upper limit and the number of digital data symbols in the FIFO buffer will be No longer, apply zone,,. In order to avoid the overflow of the container and the loss of digital data symbols, the consumer will increase the consumption rate to match the manufacturer's transfer rate, and attempt to make the FIF 〇 buffer digital data 12 correction this 1304694 again close to the Shu Lai belt The number β is monitored every other week to monitor the current number of bits of the r m symbol, and the consumer increases the rate of transmission from the _buffer. The rate at which the consumer increases the amount of data consumed is synchronized with the phase at which the existing amount of touch 21 begins to decrease, and then the consumer increases the transfer rate and the number of digits such as digital data symbols into the comfort zone. However, if the rate of the number of material transmissions is much larger than that of the silker, then the upper limit of the upper two areas of the touch is entered. The current number of digits of the data symbol enters this hard == domain, and the miscellaneous must then be accelerated. Transfer rate. Through transmission rate consumption # «The rate of the consumer is close to the manufacturer rate. Through the "consumer" from the FIF0 buffer button data consumption rate and comfort ϊί ^ will be completely - like 'but the silker finally has _ consumption rate in the comfort zone' and the speed of the spine will be silky pure money speed. The principle of the same principle applies to the fact that the manufacturer initially transmits the signal at a rate slower than that consumed by the consumer. The consumer will make the transfer rate ^ 4 until the digital data symbol in the F-IF0 buffer ^ is close to the comfort zone. The third diagram of wir is the universal domain of the present invention. Sampling—analog signals such as human performance or 曰乐’ and subsequent reading of the bottle 5G generation ι?ρ η correction code. Then the 'decoded digital data is used to adjust the transmission signal, and the receiver transmits 20 Hz H-based or infrared-transmitted optical signals. The adjustment signal 150 is switched to the connection, and the digital data is restored to the original state, discontinuous and synchronized. The bit number 50 of the receiver 260 is converted into an analog signal 250 for transmission to the transmitter 100 of the headset to the data. Transfer digital data symbol 50 q temporary storage 1 § 105. By the transmitter clock generator 135, the data input register is fresh, and the digit f symbol 5Q is synchronized. From the data input temporary storage dragon symbol 5G to the error fine and correction code circuit 11G, so that the digits, the _ bit data symbol, 曰 in 1 ^ shell, provide a certain degree of recovery. 13 Amendment 1304694 has a digital data symbol accompanying its error correction code, which is then transmitted to an interleave circuit 115. For those skilled in the art, the transmission of digital data symbols tends to be corrupted when transmitted, so adjacent digital data symbols may be damaged in a short time. In order to alleviate this problem, if the digital data symbols are to be interleaved, the digital data symbols of the same error code will not be adjacent for a short time, thus allowing any damage correction at the receiving end of the digital data symbol. The interleaved digital data symbol with the error correction code is then converted to a frame formatting circuit 120. The frame format circuit 120 successively interleaves the digital data symbols, and then generates a necessary synchronization field and a start pattern, wherein the startup mode is attached to the interleaved data symbols having the continuous error correction code, such as The five figures are shown. Each frame 160a...160n begins in a synchronization mode 163. Synchronous mode 163 is a continuous timing pulse that is used in prior art receiving devices to synchronize a phase locked loop. The sync pattern 163 is then followed by a start sequence 165 which indicates the mode ' of the signal' and 167a ··167n is followed. In the communication system, there are interdigitated data symbols 167a.... · 167η fixed number. The start sequence 165 provides a reference timing reference to the transmitter clock generator 135 of the fourth diagram. The error correction code 169 is attached at the very end to fix and restore any damaged digital data symbols during transmission. The digital data symbols formatted from the frame format circuit 120 are sent to the transmission signal conditioner 125. In an infrared transmission system, the adjustment structure is typically a four-pulse position modulation (4-ΡΡΜ) configuration, but any suitable pulse position modulation system ▲ is relevant to the purpose of the present invention. The transmitter clock generator 135 provides the necessary timing to make this four-pulse position modulation. The adjusted transmission signal is transmitted to the transmission driver 130, and the transmission driver 130 transmits the adjustment signal 150 to a transducer such as an LED transmission adjustment signal to a transmission medium such as the atmosphere or a fiber-like cable. Referring to the third figure, the adjustment signal 15 is transmitted to the receiver 2 through the transmission medium. Referring to the sixth figure, the receiver of the present invention is used. The adjustment signal 15 is passed to the converter 195. In the infrared system example, converter 195 will receive a PIN diode to receive the optical signal. In the case of a radio frequency system, converter 195 will be an antenna. The signal from converter 195 is then transmitted to a conditioning circuit 205. Amplification and Adjustment Circuits Revision 1304694 205 is responsible for recovering the amplitude of the adjustment signal, removing any external noise, and demodulating the signal to recover the digital data symbol. In the preferred embodiment, the clock is used to receive multiple factors (n) of the clock fi, sampled and adjusted signals. The receive clock f is generated by the receiver clock generator 220 and its multiple nfl, and the receiver clock generator 220 has a fundamental frequency close to the fourth picture transmitter clock generator. In the preferred embodiment, both the transmitter clock generator 135 and the receiver transmit clock generator 220 have a frequency of 12.888 +/- +/- 50 ριη. Due to the phase difference and partial tolerance between the two clock generators, the above-mentioned digital data symbols are overflowing or insufficient. The receiver generator 220 provides a higher frequency multiplier, which is used to detect the conversion of the adjustment signal, and allows the measurement of the synchronization mode 163 to adjust the activation mode 165 of the signal, as shown in the fifth figure. The amplification and adjustment circuit 205 then detects the packets 167a...·167n of the interleaved circuit symbols and extracts the packets of the interleaved digital data symbols from the adjustment signals. Among them, the multi-frequency clock nfi is ideally close to 5 nfi or 6 nfi. Other methods of sampling the mediation signal or other methods for extracting the message packets of the interleaved digital data symbols may be related to the purpose of the present invention by amplifying and modulating the circuit 205. The overall reply structure of the packet of interleaved digital data symbols is transmitted from the amplification and adjustment circuit 205 to the start/stop detection circuit 225. The start/stop detection circuit 225 interprets the synchronization mode and the startup mode to form a marker signal 3, i.e., 31) 242. The flag signal 242 is arranged to divide the timing of the start range of each message packet 167a...·167n of the interleaved digital data symbol. This timing is equivalent to the period of the fourth picture transmitter clock generator 135. The packet reconstructed by the interleaved digital data symbol is transferred from the amplification and adjustment circuit 2〇5 to the buffer control circuit 210. The buffer control circuit 210 places the message packets of the interleaved digital data symbols into the buffer 215. The buffer control circuit 210 is responsible for arranging the message packets for placing and moving the digital data symbols of the buffer 215. The buffer control circuit 210 retrieves the packet of the digital data symbol from the buffer 215 for transmission to the deinterleave and error detection and correction circuit 230. The deinterleaving and error detection and correction circuit 230 rearranges the sequence of the message symbols of the digital data symbols for the order of the 1304694. Then, the packet of the digital data symbol is checked for errors occurring during the adjustment signal transmission, and then the digital data symbol returned to the transmission is corrected. Then, the deinterleaving and correction packet of the digital information symbol is returned to the buffer 215 through the buffer control circuit 21. The message packet carrying the digital data symbol must be isochronous to ensure that the audio analog signal 250 is transmitted to the headset 260. To ensure this, the packet of the digital data symbol must be consumed at the rate at which the digital clock symbol packet is generated by the transmission clock. Because the frequency and phase of the receiver clock 220 is different from the transmitter clock 135 of the fourth map, the packet of the digital data symbol must be resynchronized to match the transmitter clock 135 to ensure that this isochronous transition to digital The message packet of the data symbol. The digital data message packet is transmitted from the buffer 215 to the jitter management unit 235 for resynchronization to the transmitter clock 135. The buffer control circuit 210 transmits the digital data symbol packet from the buffer 215 to the FIFO buffer 236. . The digital data symbol message packet is transmitted from the buffer 215 to the FIFO buffer 236 at a rate determined by the negative frequency of the receiver clock generator 220. The FIFO buffer 236 is constructed by writing a digital data symbol with one frequency (WCLK) and another frequency reading (RCLK). The receiver clock generator 220 is coupled to the write clock terminal WCLK' of the FIFO buffer to provide the timing of the transfer of the digital data symbols to the fifo buffer 236. The digital data symbols are transferred from the FIFO buffer 236 at a frequency f2 in an isochronous order to the digital analog converter 245. The digitizing analog converter 245 converts the digital data symbols into a sound analog signal 250. The sound analog signal 250 is transmitted to the mouthpiece of the headset 250. The pressure control oscillator (VCX0) 239 is coupled to the read clock terminal RCLK' of the FIFO buffer 236 to provide a frequency h to read the clock. The frequency h controls the read clock 242 as the consumer controls the FIFO buffer 236 mentioned above. The frequency f2 is controlled by the VCX0 control voltage 242. Control voltage 242 is the output of a second digital analog converter 238 that is controlled by voltage control word 243. The VC0 management circuit 237 generates a voltage control word 243 and the voltage control word 243 is associated with the FIFO level indication signal 240 and the flag signal 242. The FIFO level indication signal 240 represents the level signal of the FIFO buffer 236, so the pressure controls the adjustment of the frequency of the oscillator 239, and the VC0 management circuit 237 determines the adjustment of the consumer. In a preferred embodiment, there are seven FIFO buffers 236 level indications - empty 16 corrections 1304694 (Empty ' denoted E) 'low level 2 (L 〇 wer level 2, denoted LL2), low level 1 (Lower Levell ' is denoted as LL1), half full (denoted as % f), upper limit i (upper Limit 1, ULl), upper limit 2 (Upper Limit 2, UL2), and full (full, denoted as F). If the FIFO level indication signal 240 indicates that the FIFO buffer 236 is full (F) or empty (E), there will be an error in the synchronization of the digital data symbols. The jitter management unit must then be properly diagnosed to correct this error condition under normal operation. 11? 〇 Level Indicator Signal 240, adjusts the frequency to maintain the current number of digital data symbols in the FIF buffer, where the FIF0 buffer area is interposed between the levels indicated by the LL1 and UL1 signals. Referring to Figures 4 and 8a, there is shown an operational diagram of the conveyor 1 of the present invention. The sampling result of the 1 ' analog signal in the time period produces the first frame of the digital data symbol, and converts the sample into a digital code representing the size of the analog signal. The digital data symbol 5 is placed in the data input register 105 of the transmitter 100. In time period 2, the symbol of the frame is transmitted through the ECC generator 11 〇 error correction code ECCE 以及, and interleaved by the interleave circuit 丨15. In the same time period 2, the second frame AD1 is sampled and converted into a digital information symbol, and placed in the data input register 105. At time period 3, frame formatter 120 formats the decoded and missed material. At the same time, the second frame of the data is interleaved and decoded with the error correction code ECCE1' and the third sample result is converted into digital data. At each time period 4····, the analog signal is sampled and a new set of digital data symbols is generated and transmitted to the data input register 105. In each of the following time periods 4···.  That is, the data is decoded by the ECC generator 110 error correction code ECCEn and interleaved by the interleaving circuit j i5 . Thereafter, the time frame 4····n, the frame formatter 120 formats the decoded and interleaved data to produce a frame for transmission. During this period, the formatted frame adjusts the transmission signal by the transmission signal conditioner 125, which is used by the transmission driver 130 to transmit the adjustment signal 15 to the transmission medium. Referring to Figures 6 and 8a, the operation of the receiver of the present invention. When the adjustment signal 15() passes through the transmission medium, the delay time δ of the signal 150 is adjusted. Furthermore, the quality of the transmission medium may cause damage to the adjustment signal 15 due to attenuation and interference of the adjustment signal 150. In time period 3, the receiver 200 restores the adjustment signal 15〇 and returns the received signal, i.e., the rib symbol frame. The converter 195 measures the node from the transmission medium and converts the adjustment 1304694 = signal 150 into an electrical signal, which is applied to the amplification and adjustment circuit 2〇5. The amplification and adjustment circuit 205 re-stores, samples, and restores the digital data symbol RFR0 placed in the buffer 215 as described above. In time period 4, the received data RFR has an error correction. At the same time, the transmission signal RFT1 is received and the frame RirR 1 is recovered. At time period 5, the original data frame is placed in the buffer 236 of the jitter management unit 235. The time-of-day 5' digit data symbol is then coincident with the transmitter clock timing and applied to the digital analog converter 245' and then transmitted to the headset 260 as the audio analog signal 250. In each time period 4···· n, the adjustment signal is received and restored. Number > (the frame of the data symbol is extracted and the data digit symbol has the frame error detection and correction. Then, the digital data symbol is transmitted to the FIFO buffer 236, and the digital data symbol is synchronized in the buffer 236 to the original The isochronous transfer timing is followed by the digital analog converter 225 acting on the digital data symbol for transmission to the headset 260. The start/stop detection circuit 225 is connected to the buffer control circuit 210, so the flag signal 242 is transmitted to the buffer control circuit 21. The buffer control circuit 21. When the digital data symbol frame (e.g., frame ECCD0) has been deinterleaved and corrected and returned to the buffer 215, it is ready to be placed in the FIFO buffer 236. In the eighth figure, for each digital data symbol frame, a mark signal is generated at the end of the synchronization signal and the start signal. Since the mark occurs at the start boundary of the digital data symbol frame, the mark is synchronized with the transmitter clock. And can be used as an indication of the synchronicity of the transmitter and the receiver. In the preferred embodiment, the frame of the digital data symbol has a fixed number of signals. The timing fixed between the marker signals is the frequency of the factor of the transmitter clock. Now returning to the sixth diagram, receiving the marker signal 242, the buffer control circuit 21 starts transmitting the digital data frame to the FIFO buffer. Since there is no indication of the actual difference between the frequency of the transmission of the clock generator 135 and the frequency 6 of the receiver clock generator 220 in the third diagram, the frame transmission of the digital data symbol must occur as shown in FIG. In order to ensure such transfer, the buffer control circuit 21 starts the transfer of the digital data symbol frame, and transmits the first two digit data symbols S1 and the correction book 1304694 S2 at a relatively synchronous pace. The snubber control circuit 21 shown in FIG. 9 transmits the first two digit data symbols S1 and S2 to the FIF buffer from the buffer 215 at a relatively synchronous rate to start the digital data frame transmission. Remaining private ship (10). . . & is continuously transmitted at the frequency of the receiver clock generator 220. When the level indication signal 24 indicates that the FIF buffer is half full (3⁄4 F), the management circuit 237 causes the enable pin signal 244 to drive the VCXO 239 to provide the read clock signal 242 to the FIFO buffer 236 to begin the ninth. The digital data symbol DA0 of the figure flows to the digital analog converter 245. The digital data symbols S3 and Sn are continuously transferred to the FIFO buffer 236 until the frame is terminated. When the next flag signal 242 indicates the detection of the start mode, the first two symbols S1 and S2 of the second frame are transferred to the FIFO buffer 236. The remaining digit data symbols S3 and Sn are passed to the FIFO buffer 236 before the next subsequent marker signal. When the number of digital data symbols retained in the FIFO buffer 236 is between the lower line LU and the upper limit UL1, the digital data symbols from the FIFO buffer 236 continue to be transmitted at the frequency f2 of vcx 239. Once the number of digital data symbols exceeds the lower line LU or the upper limit ^, the FIFO level indication signal 240 is appropriately activated to indicate this level. The vc〇 management circuit 237 increments or decrements the voltage control word 243 to cause the digital analog converter 238 to increase or decrease the vco control voltage 242. After that, vcxo 239 will increase or decrease the frequency f2 of the read clock signal 241. When the existing number of digital data symbols in the FIFO buffer 236 increases causing the upper limit UL1 FIFO level indication signal 240 to be activated, the VC0 management circuit 237 increments the voltage control character 243, so the digital analog converter 238 causes the VC0 control voltage 246 to increase. , thus causing the frequency h to increase. This is a factor in the increase in the rate of consumption of digital data symbols from the FIFO buffer 236. The vco management circuit 237 monitors the activity of the FIF 〇 level indication signal 240 to determine the gradient of the number of existing digital data symbols in the FIF buffer 236. If the upper limit UL1 of the FIFO level indication signal 240 indicates that the existing number of digital data symbols in the FIFO buffer 236 still exceeds the upper limit UL1, the VC0 management circuit 237 increments the voltage control character 243 to cause the frequency h to increase again to increase the consumption. rate. On the other hand, if the upper limit UL1 of the FIFO level indication signal 240 indicates that the existing number of digital data symbols in the FIFO buffer 236 no longer exceeds the upper limit uu, but there is a startup half full finger correction, the number 1304694 indicates the flag % F, and the parameter j VC0 The management circuit 237 does not change the syndrome character 243 and the frequency f2 maintains a fixed rate of consumption. However, if the FIF 〇 指示 指示 指示 指示 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再If the existing number change gradient of the bit_data symbol is too large, the VC〇 management circuit 237 reduces the voltage control character 243 to cause the frequency h to decrease, and the FIF buffer buffer data bit symbol consumption rate to decrease. If the frequency h of the receiver clock generator 220 is greater than the frequency f2 of the read clock signal 241, the number of digital data symbols in the FIFO buffer 236 is increased, so the upper limit signal UL2 of the FIFO level indication signal 240 is activated. The VC0 management circuit 237 changes the voltage control word 243 twice as large, so the frequency of the VCX0 239 is doubled. This causes a faster rate of increase from the FIFO buffer 236 to cause the amount of digital data symbols present in the UFO buffer 236 to decrease to a level close to half full. The foot management circuit 237 monitors the degree of change in the number of existing digital data symbols in the FIFO buffer 236. If the number of digital data symbols changes too much, the VC0 management circuit 237 reduces the voltage control sub-unit 243 to cause the frequency h to decrease. This will slow down the consumption of digital data symbols from the fifo buffer 236. When the existing number of digital data symbols in the FIFO buffer 236 is reduced resulting in the lower limit LL1 FIFO level indication signal 240 being activated, the VC0 management circuit 237 reduces the voltage control word 243, so the digital analog converter 238 causes the VC0 control voltage 246 to decrease. , thus causing the frequency f2 to decrease. This is the reason for the decrease in the rate of consumption of digital data symbols from the FIFO buffer 236. The VC0 management circuit 237 monitors the activity of the FIFO level indication signal 240 to determine the gradient of the amount of digital data symbols present in the FIFO buffer 236. If the lower limit LL1 of the FIFO level indication signal 240 indicates that the existing number of digital data symbols in the FIFO buffer 236 still exceeds the lower limit 11i, the VC0 management circuit 237 reduces the control word 243 so that the frequency h is again reduced to reduce consumption. s speed. On the other hand, if the lower limit LL1 of the FIFO level indication signal 240 indicates that the existing number of digital data symbols in the FIFO buffer 236 no longer exceeds the lower limit LL1 but has the start half full indication flag % F, the VC0 management circuit 237 does not change the voltage. Control character 243 corrects this 1304694 and the frequency & keeps a fixed rate of consumption. However, if the lower limit LL1 of the FIF 〇 level indication signal 24 不再 no longer indicates that the existing number of digital data symbols in the FIFO buffer 236 does not exceed the upper limit UL1, the half full indication flag % ρ is indicated in the buffer 236. If the gradient of the existing number of digital data symbols is too large, the vc〇 management circuit 237 reduces the voltage control word 243 to cause a frequency & decrease, and the digital data symbol consumption rate in the fifo buffer 236 is reduced. If the frequency f of the receiver clock generator 220 is greater than the frequency L of the read clock signal 241, the number of digital data symbols in the FIFO buffer 236 decreases, so the lower limit signal LL2 of the FIFO level indication signal 240 is activated. The VC0 management circuit 237 changes the voltage control word 243 twice as large, so the frequency of the VCX0 239 is reduced by a factor of two. This causes a faster rate of consumption from the FIFO buffer 236 to cause the amount of digital data symbols present in the FIF buffer 236 to drop to a level close to half full. The vc〇 management circuit 237 monitors the degree of change in the number of existing digital data symbols in the FIFO buffer 236. If the number of digital data symbols changes too much, the VC0 management circuit 237 reduces the voltage control character 243 to reduce the frequency h. . This will slow down the consumption of digital data symbols from the pIF0 buffer 236. The VC0 management circuit 237 constantly monitors the FIFO level indication signal 240 to determine the amount of digital data symbols present in the FIFO buffer 236, as well as the variation gradient of the digital data symbols in the consumption. From the FIFO level indication signal 240 and the calculated gradient size, the VC0 management circuit 237 adjusts the voltage control word 243 to maintain the frequency h of the read clock signal 241 in the number of digital data symbols in the FIFO buffer 236. The bit size is close to ^. The number of bits n of the voltage control word 243 is provided to the digital analog converter 238 to determine the sensitivity of the jitter management unit 235. The preferred embodiment has voltage control word 243 having three bits that allow eight bits of control voltage 242 to be incremented from digital analog converter 238. The sensitivity is increased by selecting eight bits from the voltage control character 243 having 256 bits of the control voltage 242. Moreover, the FIFO level indication signal 240 may be incremented to provide a more accurate indication of the FIFO level indication signal 240. If the adjustment signal 150 is severely impaired, the start/stop circuit 225 cannot determine the sync field and the start mode, and the buffer control circuit 210 destroys the restored data and places a blank character in the 21304 buffer 215. When a blank character is transferred to the FIFO buffer 236, the FIF buffer 236 is cleared. The VC0 management circuit 237 interprets this as an error (indicating the indication of the empty e) and causes the VCX0 239 to stop reading the clock signal 24, thereby making the sound analog signal 250 of the digital analog converter 245 silent. When the sync field and the start mode are re-established, the digital data symbols are subsequently transmitted as described above. Referring to Figures 7a through 7d, the communication method of the digital data symbol of the present invention. For the communication method steps of the digital data symbol, at three different rates - the rate of the transmitter clock 3 ( (ft) 'receiver clock 4 〇〇 rate (f!), jitter management clock goo The generated rate (ω performs the digital data symbol. By sampling the analog signal to receive (Β〇χ305) the digital data symbol, the communication method step of transmitting the digital data symbol begins. An error detection and correction code generation (Box 310) and adding To the digital data symbol. Then interleaved the digital data symbol (Box 315) to avoid the damage of adjacent data in the digital data symbol, allowing the error and detection code to be enhanced. Continuous and formatted with error detection and correction symbols The interleaved digital data symbols are as shown in the fifth figure. The continuous and formatted digital data symbols are then adjusted to (Β〇χ 325) a transmitted signal. In the preferred embodiment, the continuous and formatted digits The data symbols are decoded using a four-pulse position modulation structure, as described above. The adjustment signal is transmitted (Β〇χ 33〇) to a transmission medium, such as atmospheric pressure for transmission to a reception. In the adjustment signal (B〇xes 3〇5-33〇), the step of transmitting the digit data symbol is synchronized by the frequency of the transmission clock 3〇〇. The adjustment signal is received (Box 405), amplified, adjusted , sampling, decoding (βοχ 41〇) to recover the digital data symbol. The sampling of the adjustment signal has a sampling rate which is 11 times the frequency of the receiver clock 400. This sampling allows the decision to be transmitted within the adjustment signal, It is then decoded to recover the digital data symbols. Thereafter, the restored digital data symbols are placed in the buffer (Box 425), which retains the digital data symbols for further processing. At the same time, the recovered digital data symbols are checked to detect the synchronized fields and are embedded in The startup mode in the restored digital data frame. Regarding the detection of the sync field and the start mode, a frame mark (Β〇χ42〇) is generated to determine the start of the digital data symbol frame. Symbols and deinterlacing (Β〇χ 43〇) to restore the correct order of the digit data symbols. Then, the deinterlaced digital data symbols have an error detection and repair 22 revisions 13046 94 Positive Process' It is used to correct errors that occur during the transmission of the mediation signal.

When the check mark signal is executed (Box 440) 〇 If there is a mark, the read address counter will start to control the frame transfer of the digital data symbol from the buffer to the FIFO buffer. The FIFO buffer detects the current state of any digital data symbols in the FIFO buffer. At the beginning of the digital data symbol transfer, there is no digital data symbol present in the FIFO buffer. The digital data symbol (Box 455) indicated by the read address counter X is transferred from the buffer to the FIFO buffer. If the FIFO buffer has reached the gatecast (ι/g full), the FIFO buffer (Box 460) is detected. If the level of the threshold is not reached, the read address counter X is incremented to point to the next address and the next digit data symbol is transferred to the HFQ buffer (Box 465). The FIFO buffer (Box 460) is then detected again. When the number of digital data symbols in the FIFO buffer reaches the threshold, the digital data symbols are then extracted from the FIF0 buffer. But at the same time, the read address counter χ (Β〇χ 480) is incremented to point to the next address and the next digit data symbol is transferred to the fif buffer (Box 470). If the number of digital data symbols of the frame is transmitted (n) to the FIF buffer, the test reads the address counter (Box 475). If all symbols are not transmitted, the read address counter x (Box 480) is incremented and the digital data symbols (B 〇 x 470) are transferred from the buffer to the FIFO buffer until the digital data symbols of all frames are transmitted. Upon receiving the next frame flag, the initial read address counter X (Box 445), and because the FIFO buffer is now not empty, the next frame of the digital data symbols is transferred from the buffer to the FIFO buffer. Since the transmit clock 300 frequency ft is not exactly equal to the period or phase of the receive clock 400 frequency, the digital data symbols of all frames must be transferred from the buffer to the FIFO buffer during the time period between the two frame marks. A preferred embodiment of this method simultaneously transfers two of the digital data symbols from the buffer to the FIFO buffer. The frequency ft of the transmit clock 300 determines the frequency of the digital data symbols transmitted simultaneously to the receive clock 400. Therefore, the number of any digital data symbols must be transmitted simultaneously and still be relevant to the present invention. When the number of existing data symbols in the FIFO buffer indicates that the number of occurrences is greater than the threshold, the read address counter y is started to indicate that the first digit of the frame is transmitted to the FIFO buffer. 23 Revision 1304694 Transfers the digital data symbols indicated by the read address counter y from the FIFO buffer. In a preferred embodiment of the invention, the digital data symbols are transmitted to a digital analog converter for conversion to a sound analog signal applied to the horn. If the existing number of digital data symbols is greater than the upper limit UL1 (Box 506) or less than the lower limit LL1 (Box 508), the amount of existing digital data symbols in the FIFO buffer is detected. If the existing number of digital data symbols in the FIFO buffer is not greater than the upper limit UL1 (Box 506) and not less than the lower limit LLKBox 508), the digital data symbols are detected from the FIFO buffer consumption vs digital data symbols to the FIFO buffer. The gradient of the supply (Box 510). If the gradient indicates that the final rate is consumed by the amount of digital data symbols present in the FIFO buffer or is supplied to the FIFO buffer. If the rate of consumption or supply is too large, the frequency of the jitter management clock 400 is increased or decreased (f2 +/- i) (Box 512) to reduce the gradient of the rate change. On the other hand, if the gradient indicates that the rate of consumption is within the boundary of the upper limit uu or the lower limit LL1, the frequency f2 of the jitter management clock 5〇〇 is fixed. If the FIFO buffer is empty, increase the read address y (B〇x 514) and detect the existing number of digital data symbols in the FIFO buffer. If the FIFO buffer is not empty, the next digital data symbol is transferred from the FIFO buffer. As long as the existing number of digital data symbols in the FIF buffer is less than the upper limit UL1 (Box 506) or greater than the lower limit LL1 (Box 508), the read address counter y (B〇x 514) and the transfer digital data symbol are added. (Box 504), until no digit data symbols are transferred from the buffer to the FΠ? buffer and the FIF0 buffer is empty. When the FIFO buffer is empty, the method returns to the process of starting the reception of the adjustment signal (Box 405). When detecting the existing number of digital data symbols in the FIFO buffer (Β〇χ 5〇6) is greater than the upper limit UL1 and If the jitter management clock 5 〇〇 has a frequency f2 that is less than the frequency ft of the transmission clock 300, the jitter management clock must be increased to increase the rate of the digital data symbols from the FIF buffer. The first to detect the number of digital data symbols in the buffer is greater than the upper limit LU2. If the number of digital data symbols is not greater than the upper limit UL2, then the gamma digit data symbol is derived from the FIFO buffer consumption vs. data symbol pair F IF buffer (Box 510) gradient (B 〇 x 520). If the gradient indicates that the rate of consumption or the rate of supply is not too large, increase the frequency of the jitter management clock 4 丨 2 to (丨2+]·) (Β〇χ 24 Amendment 1304694 522) to increase the digital data. The rate at which symbols are consumed. If the miscellaneous gradient indicates that the rate of supply is too large, the frequency of the jitter management clock 400 is increased by £2 (5 + k) (β 〇χ 524) to reduce the magnitude of the gradient change and the rate of increased consumption. ^Only, if the number of digital data symbols is greater than the upper limit, see 2, then the copper number data symbol is subtracted from the FIFO buffer consumption vs. the data symbol to the FIF buffer (Box 526). If the gradient indicates that the rate of consumption or supply is not too large, then the frequency of the second tube f is a large amount of (3) +1) (Box 528), so as to increase the consumption speed of the digital data symbol. The number of FIF 〇 buffer ϋ digit data symbols is reduced to avoid overflow. If the mixed gradient indicates that the rate of supply is too large, then increasing the frequency h of the jitter management clock 400 is still increased to (3) + / a m) (β 〇χ 53 〇) to reduce and more quickly increase the rate of consumption. When the mouth is less than the lower limit LL1 and found to be lower than LL1, it is detected that the number of existing data symbols in the buffer digits is 'the frequency of the jitter management clock_ is greater than the frequency ft of the transmission clock 3〇〇, and Must be reduced to reduce the rate of consumption of digital data symbols from the FIF buffer. First, the existing symbol of the digital data symbol in the buffer is detected to be lower than the upper limit LL2. If the number of bit data 没有 is not less than the lower limit (10), the gradient from the fifq buffer digital data f to the FIFO buffer supply, the side digital data symbol consumption. If the ladder indicates that the rate of consumption or the rate of supply is not too large, the frequency of the jitter management time slot is reduced to (fa - j) (Box 522) to reduce the rate of consumption of digital data symbols. If the consumption gradient is too fast, the fresh f2 of the jitter tube_pulse is reduced to (f2 - k) (Box 536) to lower the gradient and reduce the rate of consumption faster. Only if the number of digits is lower than the lower limit LL2, the re-debt measurement data symbol is the gradient from the FIFO buffer consumption vs. the data symbol to the FIF buffer (9) X 510). If the gradient indicates that the rate of consumption or the rate of supply is not too large, the frequency of the jitter management clock 400 is reduced to (f2 - 1) (Β〇χ 542) to reduce the consumption rate of the digital data symbols and reduce the number of digital data symbols. To avoid overflow. If the consumed gradient indicates that the rate of supply is too large, the frequency f2 of the jitter management clock 400 is reduced to (f2-m) (Box 544) to lower the gradient and reduce the consumption rate faster. See Figure 7b. If the test frame symbol (Β〇χ 44〇) and no frame symbol is tested by 25 Amendment 1304694, the received data is damaged and invalid. The buffer clears the data and the data is cleared from the FIFO buffer to eliminate corrupted data. In recording and playback applications such as audio signals, digital data symbols must flow simultaneously. To avoid distortion and unnecessary tones, the digital data symbol must be set to a value that nulls the audio signal. Once the buffer is cleared (Box 180), the next startup mode (Box 415) is detected, and the digital data symbol recovered from the adjustment signal is placed in the buffer. The process of flowing the digital data symbol continues to detect the startup mode (Box 415). ). Once the FIFO buffer is cleared (Box 180), the next startup mode (βοχ 415) and the digital data symbol placed from the adjustment signal are detected in the buffer, and the flow of the digital data symbol continues after the detection of the startup mode. . The buffer and FIFO buffer can act as a control random access memory (rand〇ffl access_〇ry) that is accessed by a group of state machines. A group of state machines perform circuit functions as described above. The arbitration circuit (arbitrat〇r circuit) resolves any inconsistencies in the RAM read and write process. For example, the state machine independently performs two simultaneous transmissions of digital data symbols within the frame, but at the same time determines with the arbitration circuit which state machine writes data to the FIFO buffer. The embodiments described above are merely illustrative of the technical spirit and characteristics of the present invention. The purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and to implement them. Equivalent changes or modifications made by the spirit of the present invention should still be included in the scope of the present invention. [Simple description of the diagram] The first diagram is a communication system diagram of the conventional technology. The first figure is a time map of the ideal transmission of digital data when the conventional technology is transmitted through the communication system. The third figure is a diagram of the communication system of the present invention. Figure 4 is a block diagram of a transmitting device of the communication system of the present invention. The fifth figure is a digital data frame structure diagram of the communication system of the present invention. Figure 6 is a block diagram of a receiving device of the communication system of the present invention. 26 Amendment 1304694 Figures 7a through 7d illustrate a method flow diagram for synchronizing data received by a receiving device to avoid the occurrence of insufficient or overflow of digital data during the transfer of digital data to the receiving device. The eighth diagram is a time diagram of the synchronization of the digital data of the communication system of the present invention. The eighth picture b is a time chart of the relationship between the mark signal, the synchronization signal and the start signal of the present invention. The ninth figure is a time chart of the transfer of the data of the present invention to the FIFO data retaining component. [Main component symbol description] 1〇transmitter 15 light-emitting diode led 20 optical signal 25 headset 30 receiver 35a, 35b remaining 40 light detector 45 person 50 digit data symbol 100 transmitter 105 register 110 error detection and correction code circuit 120 frame format circuit 130 transmission driver 135 transmitter clock generator 163 synchronization mode 165 start sequence 150 adjustment signal 195 converter 200 receiver 210 buffer control circuit 215 buffer 205 amplification and adjustment circuit 220 receiver clock generator 225 start/stop detection circuit 230 error detection and correction circuit 235 jitter management unit 236 FIFO buffer 237 VC0 management circuit 239 pressure control oscillator (VCX0) 242 mark signal 27 correction of this 1304694 243 voltage Control character 250 analog signal 260 headset 300 transmitter clock 400 receiver clock 500 jitter management clock 28

Claims (1)

1304694 Year of the Bamboo?曰μ曰 Amendment to this amendment. Scope of application: 1. A device for ensuring high-quality sound recording and playback in a wireless or wired digital sound communication system includes: & a receiver for receiving an adjustment signal Adjusting the signal, and reconstructing the symbol of the digital data from the adjustment signal and synchronizing the digital data to a first reference signal, the receiver comprising: a jitter management unit that steps the digital resource to the first reference Off, the jitter management unit comprises: - a first-in first-out hash component that receives the 4 digits (four) and the relay sync bit data to make further actuations; - a variable reference reference generator that is connected to the advanced first Generating a component to provide synchronization of the digital data by the first reference signal; and generating a device-controlled weave that receives the -mark signal extracted from the adjustment signal and communicates the FIFO data Yuan Xiangchun—occupies the signal, the age is based on the number of existing data in the FIFO data retention component, and the occupancy is controlled. To cause the reference number of touch-e, so that the first - with reference to the synchronization Bauer fed to the digital system time at which digital data to be transmitted. 2 The device for recording or reproducing sound quality in wireless or wired digital audio communication as described in the patent application specification, the receiver further includes: 雉 „ 电路 circuit, the adjusting circuit is used for receiving, re-storing and sampling The adjustment signal is _, and the reference signal is multiplied to sample the adjustment position, so in the valve system, the boundary is represented in the St. item in the wireless wire reduction communication secret. 4: 士溆二: φ々&lt The '~receiver further includes: a buffer data retention circuit that communicates two: 1 receives and retains the reconstructed digital data, and communicates the first in first out data retention component to transmit the digital data to the first in first out data retention component Read out ί ΐί ΐϊ: 17 silk or cable 姊 通 可 可 可 可 可 可 可 可 可 可 可 可 每 每 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 The audio communication secret device can ensure the quality sound recording and playback device, and the receiver further comprises: a secondary asset=correction and deinterleaving circuit, which communicates the buffer retention circuit to receive the reconstructed digital bit 22 re_the digital pie into the original The continuous bottle, from correcting any errors in the adjustment's and replacements in the buffer retention circuit within the reorganization of the 6th as applied for a special encirclement 3 depends on the silk or peach number in the audio track secret A device for ensuring quality sound recording, wherein the buffer data transmission circuit transmits the digital data to the FIFO data retention component at a speed of the second reference signal. 7 lt. The wireless or wired digital sound described in claim 3 The communication secret device can ensure two quality sound recording and playback devices, wherein the buffer data retention circuit transmits the first-in first-out data retention component until the first-in first-out data retention component has a first-to-first-in first-out data retention component to start transmitting the digital data. 8 2 If you apply for a special (4) 7-touch nuclear money peach touch ^^ secret to ensure = quality sound recording device, its cap buffer data retention circuit transmits the existing symbols of all digital data between the two marked signals to avoid Overflow. ^If you want to apply for the 2nd perch silk thread or the New Zealand (10) sound channel system to ensure the quality sound recording and playback device, the receiver further includes: a signal detecting circuit that transmits the amplifying and adjusting circuit to receive the reconstructed digital data and extracts a marking signal from the reconstructed digital side for indicating the digital data symbol demarcation and communicates the generator control circuit to provide The mark signal is sent to the generator control circuit. =· For example, the thread or the scalar audio communication secret mentioned in the first item of the Sina® can ensure the same device as the sound recording and recording device, wherein if the occupation signal is indicated The FIFO data retention component includes a second amount of digital data, and the generator control signal indicates that the generator control circuit does not adjust the second reference signal. 1". Such as the application of the 4th _@1 item in the Wucheng cable, the sound of the ship can ensure the high-quality sound recording and playback device, wherein if the occupation signal indicates that the silk first-out data retention element, contains less than the second quantity The size of the digital data, the generator control signal instructs the generation control circuit to adjust the second reference signal to increase the 1304694 corrected content of the FIFO data retention component until the content is the second quantity until. = The device for ensuring the sound recording and playback of the product I in the wireless or wired digital sound communication system as described in claim 1 or claim 1, wherein the occupation signal indicates that the first in first out data retention component contains greater than the first The two-digit digital data, the t-control device with the m-number indicates that the cover control circuit controls the second reference job to reduce the content of the FIFO data retention component until the content is The second number. 13. A device for ensuring high quality sound recording and playback in a wireless or wired digital sound communication system, the device comprising: a transmitting device comprising: a frame formatter that decodes digital data into consecutive symbols; Transmitting the frame formatter to receive the continuous symbol and transmitting an adjustment signal consisting of the continuous symbol; and a receiving device conveying the transmitting device to receive the adjustment signal and re-storing the adjustment signal And reconstructing the symbol of the digital data from the adjustment signal and synchronizing the digital data to a first reference signal, the receiving device includes: a jitter management unit that synchronizes the digital data to the first reference signal, The jitter management unit comprises: a first-in first-out data retention component, which receives the reconstructed digital data and transmits the synchronized digital data for further operation; and a variable reference signal generator connected to the county silk data Retaining to provide synchronization of the digital data by the first reference signal; and a generator control circuit, Receiving a mark signal extracted from the adjustment signal, and transmitting the FIFO data retention component to receive an occupation signal indicating the existing quantity of the digital data in the FIFO data retention component, and The occupancy signal generates a generator control signal to cause the reference signal to be adjusted such that the first reference signal synchronizes the digital data to a time when the digital data is transmitted. 14·=Application scope of the patent application 帛13, the device for ensuring two-quality sound recording and playback in a wireless or wired digital sound communication system, wherein the connection device further comprises: - amplification and (four) circuit 'the adjustment · wire reception And re-storing and sampling the adjustment signal, and sampling the adjustment signal by a multiple of the first reference signal of the reference 1304694, so in the adjustment signal, the transition between the bits representing the boundary in the digital data is detected and reconstructed. The digital data is synchronized to the second reference signal. 15) The device for ensuring quality sound recording and playback in a wireless or wired digital sound communication system according to claim 14, wherein the receiving device further comprises: a buffer data retention circuit that communicates the amplification and adjustment circuit Receiving and retaining the reconstructed digital data, and communicating the first in first out data retaining component to transmit the digital data to the first in first out data retaining component. 16. The apparatus for ensuring high quality sound recording and playback in a wireless or wired digital sound communication system according to claim 15, wherein the buffer data retention circuit has at least one buffer circuit, and each buffer circuit retains a plurality of the buffer circuits. The symbol of the digital data. 17. The apparatus for ensuring high quality sound recording and playback in a wireless or wired digital sound communication system according to claim 15, wherein the receiving apparatus further comprises: a data correction and deinterleaving circuit that communicates the buffer retention circuit Receiving the reconstructed digital data, reorganizing the digital data into an original continuous symbol, and correcting any errors generated during the adjustment signal transmission, and substituting the re-group corrected digital digits in the buffer retention circuit data. 〃18. The device for ensuring high quality sound recording and playback in a wireless or wired digital sound communication system according to claim 15, wherein the buffer data retention circuit transmits the digital data at a rate of the second reference signal to The FIFO data retention component. ° ' 19 · A device for ensuring high-quality sound recording and playback in a wireless or wired digital sound communication system as described in claim 15 wherein the buffered data (4) circuit transmits the first-in first-out data retention component Until the FIFO data retention component has a first '= FIFO data retention component to begin transmitting the digital data. "20. The device for recording high quality sound recording in wireless or wired digital voice communication as described in claim 19, wherein the buffer data retains existing symbols of all digital data between the electric numbers to avoid overflow of the recording data. (4) 21. The device for recording high quality audio in wireless or wired digital sound according to claim 14 of the patent application, wherein the receiving device further comprises: § ^ 32 Amendment 1 146 469 2nd boundary mark signal fine circuit, which conveys the Putting the A_section circuit to reconstruct the digital data from the age and reconstructing the digital signal from the reconstructed digital data age to indicate the marking signal of the digital data symbol boundary, and transmitting the generating n control circuit to supply the marking signal to the generated hybrid circuit 22·=申^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The second quantity of digital data, the generator measurement and reduction indication, the generator control circuit does not adjust the second reference signal. The device for ensuring quality sound recording and playback in a wireless or wired digital sound communication system according to Item 13 of the scope, wherein the FIFO data is confusing* the FIFO data retention 7G component contains less than the second quantity Age data, the numerator test signal indicates the generator, and the circuit is reduced by the second reference, and the content of the FIFO data retention component is increased until the content is the second quantity. 24·=Application The device for ensuring south quality sound recording and playback in a wireless or wired digital sound communication system according to Item 13 of the patent scope, wherein if the occupation signal indicates that the FIFO data is retained, the digital data larger than the second quantity is included And the generator control signal instructs the generator control circuit to adjust the second reference signal to reduce the content of the FIFO data retention component until the content is the second number. a synchronization circuit that synchronizes a digital data clock of a first reference signal period to a second reference period, the digital data synchronization The method includes: a first-in first-out data retention component, receiving digital data with the first reference signal as a clock, and transmitting the synchronized digital data in the second reference period; a variable reference signal generator, Connecting to the FIFO data retention component, synchronizing the digital data to provide a clock having the second reference period; and a generator control circuit receiving a flag signal indicating a start of a group of the digital data symbols And communicating the FIFO data retention component to receive an occupancy signal indicating the amount of digital data present in the FIFO data retention component, and the occupancy signal generating a generator control signal to cause the reference The signal is adjusted to synchronize the digital signal with the second reference period to the second reference period. 26. The digital data synchronization circuit of claim 25, wherein the digital data is transmitted 33 1304694 The correction is sent to the FIFO data retention component until the FIFO data retention component has a first number Quantity, the FIFO data retention component begins to transmit the digital data. 27. The digital data synchronizing circuit of claim 26, wherein the existing symbols of all data symbols between the two marked signals are transmitted to the buffer data retaining circuit to prevent the digital data from overflowing. The digital data synchronization circuit of claim 25, wherein if the occupation signal indicates that the FIFO data retention component comprises a second amount of digital data, the generator control signal indication generator control The circuit does not adjust the second reference signal. The digital data synchronization circuit of claim 25, wherein if the occupancy signal indicates that the FIFO data retention component contains less than the second amount of digital data, the beta 1 generator control signal indication generates The controller control circuit adjusts the second reference signal to increase the content of the FIFO data retention component until the content is the second number. 3. The digital data synchronization circuit of claim 25, wherein the generator control signal indicator generator is generated if the occupancy signal indicates that the FIFO data retention component comprises digital data greater than the second number of magnitudes The control circuit adjusts the second reference signal to reduce the content of the FIFO data retention component until its content is the second number. 31. A method for synchronizing digital data time, according to a circuit having a first period clock transition to a circuit having a second periodic clock, the steps comprising: providing a first in first out data retention component; The digital data to the FIFO data retaining component having the clock of the first period; transmitting the digital data from the FIFO data retaining component having the clock of the second period; monitoring an occupied signal, From the FIFO data retention component, indicating the number of existing data in the FIFO data retention component; monitoring a marker signal indicating a boundary between the digital data clusters; and depending on the occupancy signal and the Marking the signal, adjusting the clock of the second period to synchronize the digital data to the second clock cycle. 32. The method of synchronizing digital data time as described in claim 31, wherein the digit is transmitted to the FIFO data retaining component until the FIFO data retaining component has a first quantity, The FIFO data retention component begins to transmit the digital data. 34 1304694 A method for synchronizing the digitized data time as described in claim 31, wherein all digital data symbols existing between two marker signals are transmitted to the FIFO data retention component, During the time period between the two tags, the overflow of the digital data is avoided. 34. The method of synchronizing digital data time as described in claim 31, wherein if the occupancy signal indicates that the FIFO data retention component comprises a second amount of digital data, the second cycle is not adjusted. The clock. 35. The method of synchronizing digital data time as described in claim 31, wherein if the occupancy signal indicates that the FIFO data retaining component contains less than the second amount of digit data, the adjustment has the first The two-cycle clock causes the clock to have a second period to increase the content of the FIFO data retention component until its content is the second amount. 36. The method for synchronizing the digital data time according to claim 31 of the patent scope, wherein if the occupant signal indicates that the FIFO data retaining component contains digital data larger than the second quantity, the two weeks are suspected Lying the miscellaneous worms #帛二狮, shouting the content of the FIFO data retention component until the content is the second amount. 37. A method for receiving digital data, the digital data being transmitted at a first clock rate, the bean step comprising: 接收 receiving and re-storing the mediation signal, the adjustment signal being adjusted by the digital data; And synchronizing the symbols of the digital data from the valve signal having a first periodic clock; to the circuitry having the clock of a second period, the steps comprising: providing a first in first out data retention component Transmitting the digital data to the FIFO data retaining component having the clock of the first period; transmitting the digit (4) from the FIFO data retaining component having the clock of the second period; monitoring-occupying a signal, from the FIFO data retention component, indicating the number of existing data in the FIFO data retention component; monitoring a marker signal indicating a boundary between the digital data clusters; and depending on the occupancy signal And the mark signal, adjusting the clock of the second job to synchronize the digital data to the second clock cycle. 38. The method for receiving digital data as described in claim 37 of the patent scope includes the step of extracting the mark signal from the Lai section 35 amendment 1304694 signal. 39. The method of receiving digital data as set forth in claim 37 of the patent application, further comprising correcting an error occurring during the transmission of the adjusted signal. 40. The method of receiving digital data as recited in claim 37, further comprising the step of deinterlacing the digital data to reorganize the digital data into an original continuous symbol. 41. The method of receiving digital data according to claim 37, wherein the digital data is transmitted to the FIFO data retaining component until the FIFO data retaining component has a first quantity, from the first in first out The data retention component begins transmitting the digital data. 42. A method of receiving digital data as described in claim 37, wherein all digital data symbols present between two standard signals are transmitted to the first in first out data retention component, between the two markers Avoid the overflow of the digital data during the time period between. 43. The method for receiving digital data according to claim 37, wherein if the occupancy signal indicates that the FIFO data component comprises a second number of digits of data, the second period is not adjusted. pulse. 44. The method of claiming a location data according to claim 37, wherein if the occupation signal indicates that the FIFO data retention component contains less than the second number of digits, the adjustment has the first The second week_clock causes the clock to be the second job to increase the content of the FIFO data retention component until the content is the second amount. 45. The method of receiving digital data according to claim 37, wherein if the occupation signal indicates that the FIFO data side component contains digital data larger than the second quantity, adjusting the second job scale The clock has a second chat, shouting less of the content of the first remaining component until its content is the second amount. The method of investing in the protection of the digital data, from the _th-position to the second position, the steps include: transmitting a mediation signal mediated by the digital data, the digital data __ Synchronizing the pulse rate; and receiving the digital data, the steps comprising: receiving and re-storing the adjustment signal, reconstructing and synchronizing the digitized symbol, and transmitting the adjusted signal from the periodic clock to the device - ',,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, a first-out data retaining component; transmitting the digital data from the first-in first-out data retaining component having the clock of the second period; monitoring an occupied signal, the retaining component from the first-in first-out data, indicating that the advanced The data retains the existing quantity of the component digital data; monitors a marker signal indicating a boundary between the digital data clusters; and depends on the occupancy signal and the marker signal Adjusting the second period of the clock synchronization of the digital data to the second clock cycle. 47. The method of communicating digital data as set forth in claim 46, further comprising the step of extracting the marker signal from the adjustment signal. 48. The method of communicating digital data as set forth in claim 46, wherein the method of receiving the digital data is to transmit the digital data to the FIFO data retaining component until the FIFO data component has - The first-number 4 starts transmitting the digital data from the thief's data retention component. 49. A method of communicating digital data as set forth in claim 46, wherein all digit data symbols present between two marker signals are transmitted to the FIFO data for retention, between the two markers Time is moving to avoid overflow of the digital data. 5. The method of communicating digital data as described in claim 46 of the patent application section signals that the advanced Xianling material component comprises - the second quantity is large == the adjustment has a two weeks_clock. w stomach tt Μ Μ 不 ^ As described in the scope of patent application, the method of communicating digital data, wherein if the occupation = number refers to the thief donation data retention component contains less than the second amount of digital data, ^ adjust With the clock of Na's second, the period of the period of the shirt is expected to be the highest. 4 in and first out of the shell 37 Amendment 1304694 VII. Designated representative map: (1) The representative representative of the case is: Figure 6. (b) The symbol of the representative figure is briefly described: 150 adjustment signal 195 converter 200 receiver 210 buffer control circuit 205 amplification and adjustment circuit 215 buffer 220 receiver clock generator 225 start/stop detection circuit 230 error detection Measure and Correction Circuit 235 Jitter Management Unit 236 FIFO Buffer 237 VCO Management Circuit 238 Digital Analog Converter 242 Mark Signal 245 Digital Analog Converter 260 Headset 239 Pressure Control Oscillator (VCXO) 243 Voltage Control Character 250 Analog Signal Eight If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention: