KR20070085235A - A method and apparatus for ensuring high quality audio playback in a wireless or wired digital audio communication system - Google Patents

Abstract

A communication system synchronizes data received and recovered from a transmission medium to the data transmitted such the there is neither under-run nor overrun of the data due to differences in the transmission and reception timing. The data communication system has a transmitter and a receiver. The transmitter encodes digital data into series of symbols and transmits a modulated signal composed of the series of symbols. The receiver acquires the modulated signal, restoring the modulated signal, reconstructing the symbols of the digital data from the modulated signal and synchronizing the digital data to a first reference signal. The digital data is transferred to a buffer data retention circuit. The digital data is transferred from the buffer retention circuit to a jitter management unit. A boundary marker signal detection circuit extracts a marker signal indicating a boundary of symbols of the digital data to provide an indication of the timing of the digital data as broadcasted by the transmitter. A jitter management unit synchronizes the digital data to the first reference signal. The jitter management unit has a FIFO buffer to receive the reconstructed digital data at the rate of the first reference signal from the buffer retention circuit and transmits the synchronized digital data at a rate approximating the timing of the transmitter. The jitter management unit synchronizes the digital data by monitoring the level of the digital data present within the FIFO buffer and adjusting the consumption of the digital data from the FIFO buffer.

Description

TECHNICAL FIELD AND Apparatus for Ensuring High Quality Audio Playback in a Wireless or Wired Digital Audio Communication System {A METHOD AND APPARATUS FOR ENSURING HIGH QUALITY AUDIO PLAYBACK IN A WIRED DIGITAL AUDIO COMMUNICATION SYSTEM}

This application claims priority to US Provisional Patent Application 60 / 612,007, filed September 22, 2004, which is hereby incorporated by reference.

U.S. Preliminary Patent Application 60 / 612,008, assigned to the same assignee as the present invention and filed September 22, 2004, entitled "An Apparatus and Method for Adaptive Digital Locking and Soft Evaluation of Data Symbols in a Wireless Digital Communication System" This is a related patent application.

The present invention relates to apparatus and methods for the transmission and reception of digital data communication signals. In particular, the present invention relates to the synchronization of received digital data communication signals.

Digital data transmission and reception is relatively complex in most wireless or wired applications. However, transmitting audio reliably at the receiver and transmitting digital audio data is more difficult due to the isochronous nature of the audio requirements. Playback systems using standard sigma delta audio digital to analog converters must maintain audio clocks that require audio pulse code modulation samples periodically to maintain smooth playback. For wireless transmitters and receivers that do not perform clock recovery from the transmitted signal, the audio clock of the transmitter is different from the audio clock of the receiver and therefore the reproduction speed of digital data and consumption of digital data are problematic. The transmitter's clock can oversupply digital data at a rate faster than the receiver consumes digital or alternatingly, and the transmitter's clock lacks digital data at a slower rate, resulting in a lack of receivers of digital data symbols.

An example of a digital data communication system is a wireless infrared digital audio headphone as shown in FIG. The transmitter 10 obtains digitally encoded audio signals, which are then formatted into sync, control and error signals. The formatted encoded data modulates the transmission signal employing pulse batch modulation. The modulated signal is used to control the emission of the optical signal from the light emitting diode (LED) 15. The optical signal 20 broadcasts to the headphones 25. Headphones 25 have photodetector 40. Photodetector 40 is generally disposed on the outside of the headphones 25 to receive the optical signal 20. The detected electrical signals of photodetector 40 are passed to receiver 30 which demodulates and reformats the encoded audio signals for delivery to speakers 35a and 35b. Speakers 35a and 35b are disposed in close proximity to the ears of the person 45 wearing headphones 25.

Wireless transmission of digital data is often accomplished by transmitting sequentially formatted frames of digital data. In systems such as those listed in the May 2001 Infrared Data Association (IrDA) "Serial Infrared Physical Layer Specification", Version 1.4, the frame shown in section 5.4.2 is a specialized field (PA), a start flag field (FA). , A data field DD, and a stop flag field STO. The receiver uses specialized fields to synchronize the receiver's clocking system to incoming messages. In general, a phase lock loop oscillator is used to synchronize the receiver to a specialized field.

Once the full field is detected and the receiver is synchronized, the receiver starts to detect the start flag field to establish symbol synchronization. If the start flag field is correct, the receiver will begin interpreting the data symbols of the data field and continue to interpret the data symbols until the stop flag field is received.

An example of an ideal transmission of digitized data is shown in FIG. During time period τ ₁ , a first frame AD0 of digital data symbols is generated by converting sampling and samples of the audio analog signal into digital coding representing the magnitude of the analog signal. The symbols of the frame are interleaved and encoded with an error correction code ECCE0 for a time period τ ₂ . At the same time τ ₂ , the second frame AD1 is sampled and converted into symbols of digital data. During the time period τ ₃ , a frame of interleaved and encoded data is used to modulate the transmission signal RF T0, which is transmitted by the LED 15 from the transmitter 10 through the atmosphere via the headphones ( Broadcast to the photodiode 40 of FIG. Ideally this occurs momentarily for a time τ ₃ . The receiver recovers the transmitted signal and recovers the frames of symbols of the received data RF R0. At the same time, the second frame of data is interleaved and encoded with error correction codes ECCE1 and the third sampling AD2 is converted to digital data. During the fourth time τ ₄ , the received data RF RO is deinterleaved and has error correction and detection applied to the received to recover the frames of symbols of the original digital data ECCD0. At the same time, the interleaved and encoded frames of data ECCE1 modulate the transmitted transmission signal RF T1. The transmitted signal RF T1 is received and the frames RF R1 are recovered. At the same time, the third frames of symbols are interleaved and encoded for error correction and detection to form frames ECCE2 and the fourth sampling of the analog signal is in frames of symbols AD0 of the second group of frames. Is converted. Frames of symbols of the original data ECCD0 are converted into an analog signal AD0 for application to the speakers 35a and 35b for a time τ ₅ . As shown in the process of obtaining digital data by sampling an analog signal; Interleaving and encoding digital data with error correction codes; Modulating and transmitting digital data; Receiving and recovering digital data; Deinterleaving the digital data and detecting and correcting any errors in the digital data; And converting the digital data into an analog signal for transmission to the speakers 35a and 35b continues sequentially during the respective time periods τ ₅ ..., Τ _n .

The "Serial Infrared Physical Layer Specification" details the encoding of data in section 5.4.1. Digital data is transmitted using 4-pulse position modulation. In this example, the double bit data structure is encoded by placing one pulse in the symbol. The symbol is divided into four time positions of the duration of the symbol using each position representing the coding of the double bit data structure. The full field, start flag field, and stop flag field are each unique codes with symbol streams in which the four pulse position modulation of the dual bit data structure cannot be confused.

The synchronization of a receiver employing a phase lock loop is affected by jitter in obtaining the frequency of the local receiver to match the transmitted data frequency. In addition, any drift in the local oscillator causes the local oscillator to relock periodically. Without periodic relocking of the local oscillator to the signal, there may be errors in data reception. In addition, multipath reception problems cause the received timing data to vary due to the delay difference of the paths.

It is known that clock recovery methods are not complete. In a wireless environment, when the receiver cannot receive the digital data stream due to transmission path interference, the phase lock loop is no longer synchronized to the transmit clock, which generates a clock that causes corruption or loss of digital data. Certain muting techniques are employed to alleviate the loss of digital data symbols and thus the clock synchronization problem.

U.S. Patent 5,457,718 (Anderson, et al.) Discloses a compact phase recovery method using digital circuits. Phase recovery circuits are essentially fully integrated digital filters, which interact with a phase comparator to provide phase lock loop and data retiming functions. The digital filter provides a data retiming function by sending a 4-bit counter output to a digital delay element disposed between the data signal input and the input to the phase comparator. When the data is out of phase with respect to the local clock, the digital filter determines the required phase correction polarity from the multiple binary phase determinations and feeds it back to the delay element. The delay element then adjusts the incoming data phase with respect to the local clock phase.

U.S. Patent 5,887,040 (Jung, et al.) Provides a high speed digital data retiming apparatus wherein the binary data has a static skew due to the delay difference between the retiming clock pulses and the data and with time and temperature Due to the characteristic change, even if dynamic skew exists, it can be retimed in a stable manner. The external clock pulses are delayed by the delay section so that system performance is independent of the data pattern. If the data phases exhibit a continuous difference (deviation) for more than a certain period of time, the flexible buffer absorbs the deviation and therefore no data is lost.

US Pat. No. 5,886,552 (Chai, et al.) Describes a data retiming circuit that can more effectively retime externally input data by using multiple clocks from a voltage controlled oscillator in a phase locking loop.

U.S. Patent 5,608,357 (Ta et al.) Discloses a data retiming system for incoming data retiming and jitter removal. The data retiming system includes a local clock; A phase aligner for receiving incoming data, forming a clock recovered from the incoming data, and forming the retimed incoming data by retiming the incoming data with the recovered clock; And a buffer memory for removing jitter from the retimed incoming data by storing incoming data retimed in the buffer memory according to the recovered clock and reading the stored data from the buffer memory according to the local clock. Data retiming systems provide reliable operation even at very high data rates.

“Low-Latency Plesiochronous Data Retiming” by Dennison et al., procedure of the March 1995 VLSI Convergence 1995 Advanced Research, found February 4, 2002 at www.mit.edu/pub/cva/plesio.ps.Z. Retime the received data by delaying the data so that it can be captured by the receiver clock. The delay is varied to allow a difference from the transmitted clock and the received clock of the data.

"Rational Clocking" by IEEE Computer Design International Conference Procedure, Sarmenta et al., October 1995, maintains a known phase relationship between clocks whose frequencies are related by rational factors, and algorithmically time-communicates without competing runtime adjustments. Describes the use of predictiveness of relative phases for

It is an object of the present invention to provide a communication system for synchronizing data received and recovered from a transmission medium with data transmitted to the transmission medium.

Another object of the present invention is to provide a communication system in which data received and recovered from a transmission medium does not have under-run or overrun of data due to a difference in transmission clocking and reception clocking.

To achieve at least one of these and other purposes, a data communication system has a transmitter and a receiver. The transmitter includes a frame formatter and a transmission device. The frame formatter encodes digital data into a series of symbols. Encoding of digital data includes interleaving the digital data and providing error detection and correction codes to the digital data. The transmitting device communicates with a frame formatter to receive the series of symbols and to transmit a modulated signal consisting of the series of symbols.

The receiver communicates with the transmitter to obtain a modulated signal, to recover the modulated signal, to reconstruct the symbols of the digital data from the modulated signal, and to synchronize the digital data with respect to the first reference signal. The receiver has an amplification and conditioning circuit connected to receive, recover and sample the modulated signal. The modulated signal is sampled in multiples of the first reference signal such that transitions indicative of boundaries between bits of digital data in the modulated signal are detected and the digital data is reconstructed and synchronized to the second reference signal. Once the amplification and adjustment circuit is reconfigured and synchronized with the digital data, the digital data is transferred to a buffer data preservation circuit where the reconstructed digital data is preserved. The buffer holding circuit has at least one buffer circuit for storing groups of symbols.

The digital data is passed from the buffer holding circuit to the data modification and deinterleaving circuit for reconstructing the digital data into the original sequence of symbols. The data correction and deinterleaving circuits further correct any errors generated in the transmission of the modulated signal. Reconstructed and corrected digital data during the deinterleaving and correction of the digital data is replaced in the buffer retention circuit.

The boundary marker signal detection circuit is in communication with the amplification and conditioning circuit to receive the reconstructed digital data. From the reconstructed digital data, the boundary marker signal detection circuit extracts a marker signal representing the boundary of the symbols of the digital data. The marker signal provides a timing indication of the digital data as broadcast by the transmitter.

The receiver has a jitter management unit for synchronizing digital data with respect to the first reference signal. The jitter management unit receives the reconstructed digital data from the buffer holding circuit at the speed of the first reference signal and transmits the synchronized digital data for further processing at a rate similar to the second reference signal close to the timing of the digital data in the transmitter. It has a FIFO data storage device.

The jitter management unit has a variable reference signal generator connected to the FIFO data storage device for providing a second reference signal for synchronization of digital data. The buffer data storage circuit delivers digital data to the FIFO data storage device until the FIFO data storage device contains a first amount of digital data (approximately 1/2 of the capacity of the FIFO data storage device). Start sending digital data. In addition, the buffer data preservation circuit must convey all symbols of digital data existing between two marker signals to prevent overrun of the digital data. In order to achieve full transfer of all symbols between the two markers, the buffer data preservation apparatus essentially transfers the first and second symbols of the frame between the two markers essentially simultaneously. This prevents any overrun of data passed to the FIFO data preservation circuit.

The jitter management unit has a generator control circuit connected to receive a marker signal extracted from the signal modulated by the boundary marker signal detection circuit. The generator control circuitry also communicates with the FIFO data preservation apparatus to receive an occupation signal indicative of the amount of digital data present in the FIFO data preservation apparatus. From the marker signal and the occupancy signal, the generator control circuit generates a generator control signal to cause adjustment of the variable reference signal generator such that the second reference signal synchronizes the digital data at the timing at which the digital data is transmitted.

The generator control signal of the generator control circuit indicates that the occupied signal includes the second amount of digital data (approximately half of the FIFO data saver capacity) by the variable reference signal generator, if the occupied signal indicates that the FIFO data saver contains. Indicates no adjustment. However, if the occupying signal indicates that the FIFO data preservation device contains less than a second amount of digital data, the generator control circuitry sets the generator control signals to include the content of the FIFO data preservation device until it contains a second amount of digital data. Adjust for the second reference signal by means of the variable reference signal generator to increase Δ. Optionally, if the occupancy signal indicates that the FIFO data saver contains more than the second amount of digital data, the generator control circuitry may reduce the content of the FIFO data saver until it contains the second amount of digital data. And indicate that the generator control signal adjusts to the second reference signal of the variable reference signal generator.

1 is a prior art communication system.

2 is a timing diagram illustrating ideal transmission of digital data over a prior art communication system.

3 is a communication system of the present invention.

4 is a block diagram of a transmitter of the communication system of the present invention.

5 is a frame structure diagram of digital data in a communication system of the present invention.

6 is a block diagram of a receiver of the communication system of the present invention.

7A-7D are flow diagrams illustrating a method for synchronizing data received by a receiver to prevent overrun or underrun of the digital data during transmission of the digital data to the receiver of the present invention.

8A is a timing diagram illustrating synchronization of digital data in the communication system of the present invention.

8B is a timing diagram showing a relationship between a marker signal having a synchronization signal and a start signal of the communication system of the present invention.

Fig. 9 is a timing diagram illustrating the transfer of data to the FIFO data storage device of the present invention.

The communication system of the present invention is applicable to wired or wireless digital audio communication and provides isochronous timing of digital data for high quality audio reproduction. Both the transmitter and receiver will use their local clocks for communication. In addition, the receiver includes a jitter management unit consisting of a first-in first-out (FIFO) data preservation device or buffer, a standard VCXO (voltage controlled crystal oscillator) and a VCXO control logic unit. This jitter management unit is simple to implement or integrate into any digital audio system that tracks the transmitter's audio clock and separates playback from the source by using only the FIFO buffer state.

The FIFO buffer is similar to a container and the producer (receiver) emits digital data symbols of an analog audio signal at the same rate as the clock period of the receiver. This container is empty at startup and the consumer (player) does not start until the digital data symbols have reached a threshold level. Once the digital data symbols reach the threshold level, the consumer begins to consume the digital data symbols. In theory, if producers and consumers run at the same speed, the level of the FIFO buffer or container will always be at the threshold level because it will get and discharge at the same speed.

However, if the producer is faster, the digital data symbols are delivered to the FIFO buffer faster and the consumer extracts the digital data at a slower rate, the level of the container or FIFO buffer is increased. As this increase in FIFO buffer level continues, the FIFO buffer will overflow and overrun of digital data symbols will result in digital data loss. Optionally, if the producer is slower than the consumer and the digital data symbols are delivered slower in the FIFO buffer and the consumer extracts the digital data at a faster rate, the level of the container or FIFO buffer is reduced. As this decrease in the level of the FIFO buffer continues, the FIFO buffer will be empty and the underrun of the digital data symbols will cause playback to stop until the producer provides more digital data symbols, thereby reproducing isochronous digital data symbols. Distortion occurs.

If the FIFO buffer has indicators that distinguish regions representing level digital data symbols present in the FIFO buffer, the consumer can adjust the rate at which digital data symbols are removed from the FIFO buffer. If the middle region between the upper and lower limits indicates a "stable zone", the consumer does not change the rate at which digital samples are removed from the FIFO buffer. However, when the level of the amount of data present in the FIFO buffer exceeds the upper or lower limit, the consumer must increase or decrease the rate of consumption of digital data symbols from the FIFO buffer.

For example, if the producer provides digital data symbols to the FIFO buffer faster than the consumer can extract these digital data symbols, the FIFO buffer exceeds the upper limit and the amount of digital data symbols in the FIFO buffer is more in the "stable area". It's not over. To prevent the container from overcharging and losing digital data symbols, the consumer increases the consumption rate to match the producer's transfer rate and attempts to regain access to the stable zone in the amount of digital data symbols present in the FIFO buffer. The consumer increases the rate of transfer from the FIFO buffer while monitoring the level of the amount of digital data present in the FIFO buffer at periodic intervals. The consumer gradually increases the rate of consumption of the digital data to a stage where the amount of data present in the FIFO buffer begins to fall, and then the consumer stops increasing the transfer rate and the level of the amount of digital data symbols in the FIFO buffer Wait to enter the stable zone. However, if a producer delivers digital data at a rate much faster than the consumer expects, the FIFO buffer can enter a high area that is unbearable. Once the amount of digital data symbols present in the FIFO buffer enters the upper region, which is difficult to withstand, the consumer must increase the transfer rate faster. This acceleration and deceleration of the delivery speed by the consumer will bring the consumer's speed closer to the producer's speed.

The consumption rate of digital data symbols from the FIFO buffer by the consumer will not be exactly the same as the producer's transfer rate and the consumer will ultimately have a consumption rate in the soft or stable region and there will be little acceleration or deceleration of the consumption rate.

It is clear that the same principle can be applied initially to producers delivering digital data symbols to a FIFO buffer at a slower rate than consumer consumption. The consumer slows down the consumption until the amount of digital data symbols in the FIFO buffer reaches the stable region.

Reference is made to FIG. 3 for a discussion of the communication system of the present invention. Analog signals, such as human language or music, are sampled and converted into digital data symbols 50 representing samples of the analog signal. Digital data symbols 50 are passed to transmitter 100 to serialize and format digital data symbols and provide error detection and correction codes. Encoded digital data symbols are used to modulate a transmission signal such as an optical signal during the fundamental frequency or infrared transmission for RF wireless transmission. The modulated signal 150 is passed to a receiver 200 that recovers, reconstructs, deserializes, and synchronizes digital data symbols. Receiver 200 further converts digital data symbols into analog signal 250 for delivery to speakers of headphones 260.

The transmitter 100 of the present invention is shown in FIG. Digital data symbols 50 are passed to data input register 105. The digital data register 105 synchronizes digital data symbols with the data clock provided by the transmitter clock generator 135. Digital data symbols are passed from data input register 105 to error detection and correction coding circuit 110, where the digital data symbols are error detection and correction code to provide a recovery level for potential tampering of transmitted digital data symbols. Encoded as

Digital data symbols with incidental error correction codes are passed to the interleaved circuit 115. As is known in the art, the transmission of digital data symbols has a corruption of transmission that occurs such that temporally adjacent digital data symbols can be corrupted. To alleviate this problem, the digital data symbols are interleaved so that the same error correction code is no longer contiguous in time, thus correcting any corruption at the receiver of the digital data symbols. Symbols of interleaved digital data with error correction codes are passed to the frame formatting circuit 120. The frame formatting circuit serializes the interleaved digital data symbols and serializes using additional error correction codes as shown in FIG. 5 to generate the necessary sync field and start pattern added to the interleaved digital data symbols.

Each frame 160a, ..., 160n starts with a sync pattern 163. The sync pattern 163 is a unique series of timing pulses used to synchronize the phase locking loop in a prior art receiver. The next sync pattern 163 is a start sequence 165 indicating that the pattern of the following signals represent packets 167a,..., 167n digital data symbols. In a communication system in which frames have a fixed number of packets 167a, ..., 167n of interleaved digital data symbols, the start sequence 165 provides a reference timing referenced to the transmitter clock 135 of FIG. do. Attached to the end of the frame is an error correction code 169 used to repair and recover any digital data symbols that are corrupted in transmission.

The formatted digital data symbols are passed from frame formatter 120 to transmit signal modulator 125. In an infrared transmission system, the modulation method is generally a four pulse position modulation method, but any suitable modulation method can maintain the intent of the present invention. Transmitter clock generator 135 provides the timing necessary to generate four pulse position modulation. The modulated transmit signal is transmitted to a transmit driver 130 that transmits a modulated signal 150 to a transducer, such as an LED, that transmits the modulated signal to a transmission medium such as an atmosphere or a cabling such as an optical fiber cable.

See FIG. 3 again. The modulated signal 150 is transmitted to the receiver 200 via a transmission medium. See FIG. 6 to discuss the receiver of the present invention. The modulated signal impinges on transducer 195. In the case of an infrared system, the transducer 195 is a PIN diode that receives an optical signal. For an RF system, the radio frequency pie and the transducer 195 is an antenna. The electrical signal developed by the transducer 195 is transmitted to the amplification and conditioning circuit 205. Amplification and conditioning circuitry 205 demodulates the signal to recover the amplitude of the modulated signal, remove any extraneous noise, and recover digital data symbols.

In a preferred embodiment, the recovered and adjusted modulated signal is sampled using a clock that is a multiplication factor n of the received clock f ₁ . Receiver clock f ₁ and its multiples nf ₁ are generated by receiver clock generator 220 having a fundamental frequency that reaches the frequency of transmitter clock generator 135 of FIG. 4. For example, the transmitter clock generator 135 and receiver clock generator 220 each have a frequency of 12.288 MHz +/- 50 ppm in the implementation of the preferred embodiment. The frequency difference due to the tolerance and the phase difference between the two clock generators causes overruns and underruns of the digital data symbols as described above.

The higher frequency multiplier nf ₁ provided by the receiver clock generator 220 is used to detect transitions of the modulated signal and the synchronization pattern 163 and the start pattern 165 of the modulated signal as shown in FIG. 5. Let's decide. Amplification and conditioning circuit 205 then detects packets 167a,... 167n of interleaved digital data symbols and extracts packets of interleaved digital data symbols from the modulated signal. The multiple n of the multi-frequency clock nf ₁ is approximately 5-6 times the frequency of the receiver clock f ₁ at optimal time. Other methods for extracting packets of other frequency or interleaved digital data symbols that sample the modulated signal may be employed by the amplification and conditioning circuit 205 and still maintain the intent of the present invention.

The fully recovered frame of interleaved digital data symbols packets is passed from the amplification and adjustment circuit 205 to the start / stop detection circuit 225. The start / stop detection circuit 225 interprets the sync pattern and the start pattern to know the marker signal 242. The marker signal 242 is timed to distinguish the starting boundaries of each frame of the packets of interleaved digital data symbols 167a,..., 167n. This timing is the same as the periodicity of the transmitter clock generator 135 of FIG.

The recovered packets of interleaved digital data symbols are passed from the amplification and conditioning circuit 205 to the buffer control circuit 210. The buffer control circuit 210 places the packets of digital data symbols interleaved in the buffer 215. The buffer control circuit 210 commands the placement and removal of digital data symbol packets into and out of the buffer 215.

The buffer control circuit 210 extracts packets of interleaved digital data symbols from the buffer 215 for delivery to the deinterleave and error detection and correction circuit 230. Deinterleave and error detection and correction circuitry 230 rearranges the order of packets of digital data symbols in their original order. The packets of digital data symbols are then corrected for testing errors that may occur during transmission of the modulated signal and then restoring the transmitted digital data symbols. Deinterleaved and corrected packets of digital data symbols are returned to the buffer 215 by the buffer control circuit 210.

Packets of digital data symbols must be delivered isochronously to ensure that audio analog signal 250 is provided to headphones 260. To ensure this, packets of digital data symbols must be consumed at the rate at which they are generated using the clock on which they are transmitted. Because the frequency and phase of the receiver clock 220 vary from the transmitter clock 135 of FIG. 4, the packets of digital data symbols are resynchronized to match the transmitter clock to ensure isochronous delivery of packets of digital data symbols. Should be. Packets of digital data symbols are passed from buffer 215 to jitter management unit 235 to resynchronize with the transmitter clock.

The buffer control circuit 210 transfers packets of digital data symbols from the buffer 215 to the FIFO buffer 236. Packets of digital data symbols are transferred from buffer 215 to FIFO buffer 236 at a rate determined by frequency f ₁ of receiver clock generator 220. The FIFO buffer 236 is configured to have digital data symbols written at one frequency WCLK and read at another frequency RCLK. Receiver clock generator 220 is connected to write clock terminal WCLK of FIFO buffer 236 to provide timing for the transfer of digital data symbols to FIFO buffer 236.

Digital data symbols are delivered in isochronous order from FIFO buffer 236 to digital-to-analog converter 245 at frequency f ₂ . Digital data symbols are converted into an audio analog signal 250 by a digital to analog converter 245. The audio analog signal 250 is transmitted to the speakers of the headphones 260.

The voltage controlled oscillator (VCXO) 239 is connected to the read clock terminal RCLK of the FIFO buffer 236 to provide a frequency f ₂ to the read clock 242. Read clock RCLK as controlled by frequency f ₂ acts as a consumer control for FIFO buffer 236 as described above. The frequency f ₂ is controlled via the VCXO by the control voltage 242. Control voltage 242 is the output of second digital to analog converter 238 controlled by voltage control word 243. The voltage control word 243 is generated by the VCO management circuitry 237 and follows the FIFO level indication signals 240 and the marker signal 242.

FIFO level indication signals 240 provide a signal indicative of the level of FIFO 236 such that consumer adjustment by frequency adjustment of VCXO 239 can be determined by VCO management circuitry 237. In the preferred embodiment, there are seven indications 240 at the level of the FIFO 236-empty (E), lower level 2 (LL2), lower level LL1, hamf full (1/2 F). , Upper limit 1 (UL1), upper limit 2 (UL2), full (F).

If the FIFO level indication signals 240 indicate that the FIFO buffer 236 is full (F) or empty (E), there is an error in synchronization of digital data symbols. The jitter management unit 235 must perform appropriate diagnostics to correct the error condition. In normal operation, the FIFO level indication signals 240, the frequency f ₂ , are the digital data symbols present in the FIFO buffer in the region between the levels indicated by the lower level LL1 and upper limit 1 (UL1) signals. It is adjusted to maintain the amount.

Reference is made to FIGS. 4 and 8A to discuss the operation of the transmitter 100 of the present invention. During the time period tau ₁ , a first frame AD0 of digital data symbols is generated by sampling of the analog signal and converting the samples into digital coding representing the magnitude of the analog signal. The digital data symbols 50 are then placed in the data input register 105 of the transmitter 100. The symbols of the frame are encoded by the ECC generator 110 into an error correction code ECCE0 and interleaved by the interleaving circuit 115 for a time period τ ₂ . At the same time τ ₂ , the second frame AD1 is sampled and converted into symbols of digital data and placed in the data input register 105. During time period τ ₃ , frame formatter 120 formats a frame of encoded and interleaved data. At this time, the second frame of data is interleaved and encoded using the error correction codes ECCE1, and the third sampling AD2 is converted into digital data. In each of the time periods τ ₄ ,... Τ _n , an analog signal is sampled and a new set of digital data symbols is generated and passed to the data input register 105. In each next time period τ ₄ ,..., Τ _n , the data is encoded by the ECC generator 110 using the error correction code ECCEn and interleaved by the interleave circuit 115. Then at a later time period τ ₄ , .., τ _n , the frame formatter 120 formats the encoded and interleaved data to generate frames for transmission. During this time period, the formatted frames modulate the transmission signal in a transmission signal modulator 125 used by the transmission driver 130 to deliver the modulated signal 150 to the transmission medium.

) 만큼 지연된다. 추가로 전송 매체의 품질은 변조된 신호(150)가 변조된 신호(150)의 훼손을 유발하게 감쇠 및 간섭될 수 있다. 수신기(200)는 변조된 신호를 복구하고 시간 기간(τ₃) 동안 수신된 데이터(RF R0)의 심볼들의 프레임들을 복원한다. 트랜스듀서(195)는 전송 매체로부터 변조된 신호(150)를 얻고, 변조된 신호(150)를 증폭 및 조절 회로(205)에 제공된 전기 신호로 변환한다. 상기된 바와같이 증폭 및 조절 회로(205)는 버퍼(215)에 배치된 디지털 데이터 심볼들(RF R0)을 복원, 샘플링 및 복구한다.See Figures 6 and 8A for a discussion of the receiver operation of the present invention. When the modulated signal 150 passes through the transmission medium, the modulated signal has a time amount (

Delayed by). In addition, the quality of the transmission medium may be attenuated and interfered with such that the modulated signal 150 causes damage to the modulated signal 150. The receiver 200 recovers the modulated signal and recovers the frames of the symbols of the data RF R0 received during the time period τ ₃ . Transducer 195 obtains a modulated signal 150 from a transmission medium and converts the modulated signal 150 into an electrical signal provided to an amplification and conditioning circuit 205. As described above, the amplification and adjustment circuit 205 recovers, samples, and recovers the digital data symbols RF R0 disposed in the buffer 215.

During the fourth time period τ ₄ , the received data RF R0 has an applied error correction and detection and deinterleaves and error detection and correction circuit 230 to recover the frames of the symbols of the original digital data ECCD0. Deinterleaved by At this time, the transmitted signal RF T1 is received and the frames RF R1 are recovered. Frames of symbols of the original data ECCDO are placed in the FIFO buffer 236 of the jitter management unit 235 for a time period tau ₅ . The digital data symbols are then synchronized to the timing of the transmitter clock and provided to the digital to analog converter 245 for a time period τ ₅ and then transmitted to the headphones 260 as an audio analog signal 250.

In each of the time periods τ ₄ ,... Τ _n , the modulated signal is obtained and the transmitted signal is recovered. Frames of digital data symbols are extracted and the digital data symbols have error detection and correction applied thereto. Digital data symbols are then passed to the FIFO buffer 236 where it is synchronized to the original isochronous transmission timing. Digital data symbols are applied to the digital to analog converter 245 for transmission to the headphones 260.

The start / stop detection circuit 225 is connected to the buffer control circuit 210 such that the marker signal 242 is sent to the buffer control circuit 210. The buffer 210 is composed of multiple frames such that one frame is placed upon receipt and recovery of frames of digital data symbols. When a frame of digital data symbols (eg ECCD0) is deinterleaved, corrected and returned to buffer 215, it is ready to be placed in FIFO buffer 236.

Referring to FIG. 8B, a marker signal is generated upon completion of the sync signal and start signal for each frame of digital data symbols. Since the marker occurs at the start boundary of the frame of digital data symbols, the marker is synchronized to the transmitter clock and can be used as an indication of the concurrency of the transmitter and receiver clocks. In a preferred embodiment, the frames of digital data symbols have a fixed number of frames, the timing between the marker signals is also fixed and locked to a frequency that is a sub-multiple of the transmitter clock.

Referring again to FIG. 6, after receiving the marker signal 242, the buffer control circuit 210 begins to deliver a frame of digital data symbols to the FIFO buffer 236. Since there is no actual indication or control of the difference between the frequency of the transmitter clock generator 135 of FIG. 3 and the frequency f ₁ of the receiver clock generator 220, the transfer of frames of digital data symbols is shown in FIG. 8B. Likewise, it should occur between two marker signals 242. To ensure this transfer, the buffer control circuit 210 transfers the first two digital data symbols S1 and S2 at the same time from the buffer 215 to the FIFO buffer 236 as shown in FIG. 9. Start of transmission of the digital data symbols frame. The remaining digital data symbols S3,..., Sn in the frame are passed in series at the frequency f ₁ of the receiver clock generator 220. When the level indicator signal 240 indicates that the FIFO buffer 236 is half full (half full indicator 1/2 F is active), the VCO management circuitry 237 connects the digital to analog converter 245 of FIG. Activate start VCO signal 244 to start VCXO 239 to provide read clock signal 242 to FIFO buffer 236 to begin streaming of digital data symbols DA0.

Digital data symbols S3 and Sn continue to be delivered to the FIFO buffer 236 until the completion of the frame. When the next marker signal 242 indicates detection of the start pattern, the first two symbols S1 and S2 of the second frame are transferred to the FIFO buffer 236. The remaining digital data symbols S3 and Sn are then passed to the FIFO buffer 236 before the next later marker signal 242.

The transfer of digital data symbols from the FIFO buffer 236 results in a frequency f of the VCXO 239, with the amount of digital data symbols held in the FIFO buffer 236 remaining between the lower level LL1 and the upper limit 1 UL1. ₂ ) can be continued without change. Once the amount of digital data symbols exceeds the upper limit UL1 or the lower limit LL1, the FIFO indicator signals 240 are appropriately activated to indicate the level. The VCO management circuit 237 increases or decreases the voltage control word 243 to cause the digital to analog converter 238 to increase or decrease the VCO control voltage 242. The VCXO 239 will increase or decrease the frequency f ₂ of the read clock signal 241.

When the increase in the amount of digital data symbols present in the FIFO causes the upper (UL1) FIFO indicator signal 240 to be activated, the VCO management circuit 237 causes the VCO control voltage 246 to increase due to the digital to analog converter. Increase the voltage control word 243 to cause the frequency f ₂ to increase. This causes the rate of consumption of digital data symbols from the FIFO buffer 236 to increase. The VCO management circuit 237 monitors the activity of the FIFO indicator signals 240 to determine the slope of the change in the amount of digital data symbols present in the FIFO buffer 236. If the upper limit UL1 of the FIFO indicator signals 240 indicates that the amount of data present in the FIFO buffer 236 is still above the upper limit UL1, then the VCO management circuit 237 has a frequency f ₂ . Increase the voltage control word 243 to increase the consumption rate again. Optionally, the amount of data present in the FIFO buffer 236 no longer exceeds the upper limit UL1, but the upper limit UL1 of the FIFO indicator signals 240 indicates that the half full indicator 1/2 F is activated. Denotes, the VCO management circuit 237 does not change the voltage control word 243 and the frequency f ₂ maintains a constant rate of consumption. However, the upper limit UL1 of the FIFO indicator signals 240 is no longer activated to indicate that the amount of data present in the FIFO buffer 236 does not exceed the upper limit UL1, and the FIFO buffer 236 is no longer active. If the half full indicator (1/2 F) indicates that the decrease slope of the amount of data present in the < RTI ID = 0.0 > is too large < / RTI &_gt; Reduce the voltage control word 243 to reduce the rate of consumption.

If the amount of digital data symbols in the FIFO buffer 236 rises so that the difference between the frequency f ₁ of the receiver clock generator 220 is activated so that the upper limit signal UL2 of the FIFO indicator signals 240 is activated, the read clock signal ( If greater than the frequency f ₂ of 241, the VCO management circuit 237 changes the voltage control word 243 by a double factor such that the frequency f ₂ of the VCXO 239 increases by a twofold increase. This causes the consumption from the FIFO buffer 236 to increase at a faster rate so that the amount of digital data symbols present in the FIFO buffer 236 falls towards the half full level. VCO management circuitry 237 monitors the slope of the change in the amount of digital data symbols present in FIFO buffer 236. If the change slope of the amount of digital data symbols is too large, the VCO management circuit 237 reduces the voltage control word 243 to cause the frequency f ₂ to decrease. This reduces the rate of consumption of digital data symbols from the FIFO buffer 236.

When the lower limit (LL1) FIFO indicator signal 240 is activated by a decrease in the amount of digital data symbols present in the FIFO buffer 236, the VCO management circuit 237 causes the VCO control voltage 246 due to the digital to analog converter. Decreases the voltage control word 243, thus causing a decrease in frequency f ₂ . This causes the consumption rate of the digital data symbols from the FIFO buffer 236 to drop. The VCO management circuit 237 monitors the activity of the FIFO indicator signals 240 to determine the slope of the change in the amount of digital data symbols present in the FIFO buffer 236. If the lower limit LL1 of the FIFO indicator signals 240 indicates that the amount of data present in the FIFO buffer 236 is still above the lower limit LL1, then the VCO management circuit 237 displays the frequency f ₂ . Decreases the voltage control word 243 causing the consumption rate to decrease again. Optionally, the lower limit LL1 of the FIFO indicator signals 240 indicates that the amount of data present in the FIFO buffer 236 does not exceed the lower limit LL1, and when the half full indicator 1/2 F is activated. The VCO management circuit 237 does not change the voltage control word 243 and the frequency f ₂ maintains a constant rate of consumption. However, the lower limit LL1 of the FIFO indicator signals 240 is no longer activated to indicate that the amount of data present in the FIFO buffer 236 does not exceed the lower limit LL1, and the FIFO buffer 236 is no longer active. If the half full indicator (1/2 F) indicates that the reduction slope of the amount of data present within is too large, the VCO management circuit 237 may reduce the rate of consumption of digital data symbols from the FIFO buffer 236 at frequency f. Reduce the voltage control word 234 to allow ₂ ) to decrease.

If the difference between the frequency f ₁ of the receiver clock generator 220 decreases the amount of digital data symbols in the FIFO buffer 236 so that the lower limit signal LL2 of the FIFO indicator signals 240 is activated, the read clock signal ( If greater than the frequency f ₂ of 241, the VCO management circuit 237 changes the voltage control word 243 by a double factor such that the frequency f ₂ of the VCXO 239 decreases by a two-fold decrease. This allows the consumption from the FIFO buffer 236 to decrease at a faster rate that causes the amount of digital data symbols present in the FIFO buffer 236 to drop towards half full level. VCO management circuitry 237 monitors the slope of the change in the amount of digital data symbols present in FIFO buffer 236. If the change slope of the amount of digital data symbols is too large, the VCO management circuit 237 reduces the voltage control word 243 to cause the frequency f ₂ to decrease. This reduces the rate of consumption of digital data symbols from the FIFO buffer 236.

The VCO management circuitry 237 always monitors the FIFO indicator signals 240 to determine the amount of digital data symbols present in the FIFO buffer 236 and the slope of the change in consumption of the digital data symbols. From the FIFO indicator signals 240 and the calculated slope, the VCO management circuitry 237 causes the frequency f ₂ of the read clock 241 to enter the FIFO buffer 236 at approximately half full level (1/2 F). Adjust voltage control word 243 to maintain both levels of digital data symbols.

The number n of bits of the voltage control word 243 provided to the digital to analog converter 238 essentially determines the sensitivity of the jitter management unit 235. In an implementation of the preferred embodiment, the voltage control word 238 has three bits that allow eight increments of the control voltage 242 from the digital to analog converter 238. Sensitivity is improved by selecting 8 bits for the voltage control word 238 with 256 increments of the control voltage 242. In addition, the number of FIFO level indication signals 240 may be increased to provide fine indication of the FIFO level indication signals 240.

If the modulated signal 150 is so severely damaged that the start / stop circuit 225 cannot determine the sync field and start pattern, the buffer control circuit 210 may recover the recovered data in the buffer 215 and the appropriate null placed therein. (null) Destroy the characters. Null characters when passed to the FIFO buffer 236 operate to overflow the FIFO buffer 236. The VCO management circuit 237 interprets this as an error (empty indicator E is active) and the digital-to-analog converter 245 causes the VCXO 239 to stop the read clock 241 so that the audio analog signal 250 is muted. ) Is disabled. When the sync field and start pattern are reset, the digital data symbols are transferred as described above.

See FIGS. 7A-7D for a discussion of the method of communication of digital data symbols of the present invention. The communication method steps for the digital data symbols are essentially performed at three different speeds-the speed f _t set by the transmitter clock 300, the speed f ₁ set by the receiver clock 400, And a rate f ₂ set by the jitter management clock 500. The digital data symbol transmission steps of the communication method begin by sampling an analog signal to obtain digital data symbols (box 305). Error detection and correction code is generated (box 310) and appended to the digital data symbols. Digital data symbols are interleaved (box 315) such that error and detection codes are enhanced by preventing corruption of adjacent data in the digital data symbols. Interleaved digital data symbols with incidental error detection and correction codes are serialized and formatted (box 320) as described in FIG. 5. Serialized and formatted digital data symbols modulate the transmission signal (box 325). In a preferred embodiment, the serialized and formatted digital data symbols are encoded using the four pulse position modulation method as described above. The modulated signal is transmitted (box 330) to a transmission medium such as an atmosphere for transport to the receiver. The steps (boxes 305-330) for transmitting digital data symbols in the modulated signal are all synchronized by the frequency f _t of the transmit clock 300.

The modulated signal is received (box 405), amplified, adjusted, sampled and decoded (box 410) to recover digital data symbols. Sampling of the modulated signal has a sampling rate that is a factor n times the receiver clock 400 frequency f ₂ . This sampling allows determination of transitions in the modulated signal, which is then decoded to recover digital data symbols. The recovered digital data symbols are placed in a buffer (box 425), which holds the digital data symbols for further processing. At the same time, the recovered digital data symbols are tested to detect a start pattern (box 415) and a sync field embedded within the frame of recovered digital data symbols. During detection of the sync field and the start pattern, a frame marker is created (box 420) to identify the beginning of the digital data symbols frame.

Digital data symbols are extracted from the buffer and deinterleaved (box 430) to recover the correct order of the digital data symbols. The deinterleaved digital data symbols have an error detection and correction process (box 435) applied to correct any errors that may occur during transmission of the modulated signal.

A check for the generation of the frame marker signal is performed (box 440). If there is a marker, a read address counter (x) is started to control the transfer of digital data symbols frames from the buffer to the FIFO buffer (box 445). The FIFO buffer is checked (box 450) for the presence of any digital data symbols in the FIFO buffer. At the start of delivery of digital data symbols, there are no digital data symbols present in the FIFO buffer. Digital data symbols to be pointed to by the read address counter (x) are passed from the buffer to the FIFO buffer (box 455). The FIFO buffer is checked (box 460) if the FIFO buffer reaches a threshold (1/2 full). If the threshold level is not reached, the read address counter x is incremented to point to the next address (box 465) and the next digital data symbol is passed to the FIFO buffer (box 465). The FIFO buffer is checked again (box 460).

When the amount of digital data symbols in the FIFO buffer reaches a threshold, the digital data symbols are extracted from the FIFO. At the same time, however, the read address counter x is incremented to point to the next address (box 480) and the next digital data symbol is passed to the FIFO buffer (box 470). The read address counter is checked (box 475) if the total number n of digital data symbols of the frame is passed to the FIFO buffer. If all symbols are not transferred, the read address counter x is incremented (box 480) and the digital data symbols are passed from the buffer to the FIFO buffer (box 470) until all digital data symbols in the frame have been transferred.

Upon receipt of the next frame marker, the read address counter x is initialized (box 445) and the next frame of digital data symbols is transferred from the buffer to the FIFO buffer since the FIFO buffer is now empty. Since the frequency f _t of the transmit clock 300 is not exactly the same in terms of duration or phase with the frequency f ₁ of the receive clock 400, all digital data symbols in the frame are time periods between two frame markers. Must be passed from the buffer to the FIFO buffer. In a preferred embodiment of this method, two digital data symbols are essentially transferred from the buffer to the FIFO buffer at the same time. The number of digital data symbols to be transmitted simultaneously is determined by the frequency f _t of the transmit clock 300 versus the frequency f ₁ of the receive clock 400. Therefore, any number of digital data symbols are probably transmitted simultaneously and maintain the intent of the present invention.

When a check (box 460) for the amount of digital data symbols present in the FIFO buffer indicates that the amount of digital data symbols present in the FIFO buffer is greater than the threshold, the read address counter y is used to determine the number of frames passed to the FIFO buffer. Start to point to the first digital data symbol (box 502). The digital data symbols pointed to by the read address counter y are passed from the FIFO buffer (box 504). In a preferred embodiment of the invention, the digital data symbols are passed to a digital to analog converter for conversion into an audio analog signal provided to the speakers.

It is checked whether the amount of digital data symbols present in the FIFO buffer is greater than upper limit 1 (UL1) (box 506) or less than lower limit 1 (LL1) (box 508). If the amount of digital data symbols present in the FIFO buffer is neither greater than upper limit 1 (UL1) (box 506) or lower than lower limit 1 (LL1) (box 508), then the consumption of digital data symbols from the FIFO buffer to the FIFO buffer. The slope of the supply of digital data symbols in is checked (box 510). If the slope represents the final rate, the amount of digital data symbols present in the FIFO buffer is consumed or fed to the FIFO buffer. If the consumption rate or feed rate is too large, the frequency f ₂ of the jitter management clock 400 is incrementally increased or decreased (f ₂ +/− i) (box 512) to reduce the slope. On the other hand, if the slope indicates that the consumption rate is within the boundary of the upper limit 1 (UL1) (box 506) or the lower limit 1 (LL1), the frequency f ₂ of the jitter management clock 500 remains constant.

The read address y is incremented (box 514) and the amount of digital data symbols present in the FIFO buffer is checked if the FIFO buffer is empty (box 516). If not empty, the next set of digital data symbols is passed from the FIFO buffer (box 504). If the amount of digital data symbols present in the FIFO buffer is below upper limit 1 (UL1) (box 506) or above lower limit 1 (LL1) (box 508), the read address counter y is incremented (box 514) and the digital data symbols Are passed (box 504) until the digital data symbols are not passed from the buffer to the FIFO buffer and the FIFO buffer is empty. When the FIFO buffer is empty, the method returns to begin processing the reception of the modulated signal (box 405).

When it is checked that the amount of digital data symbols present in the FIFO buffer is greater than the upper limit 1 (UL1) (box 506) and if it is found to be larger than the upper limit, the jitter management clock 500 is the frequency f _t of the transmission clock 300 It has a frequency f _{2 below} ) and must be raised to increase the rate of consumption of digital data symbols from the FIFO buffer. The amount of digital data symbols present in the buffer is first checked (box 518) to be greater than upper bound 2 (UL2). If the amount of digital data symbols is not greater than the upper limit 2 (UL2), the consumption slope of the digital data symbols from the FIFO buffer to the supply slope of the digital data symbols from the FIFO buffer to the FIFO buffer is checked (box 520). If the slope indicates that the consumption rate or feed rate is not too large, the frequency f ₂ of the jitter management clock 400 is increased (f ₂ + j) (box 522) to increase the consumption rate of the digital data symbols. . If the consumption slope indicates that the supply speed is too large, the frequency f ₂ of the jitter management clock 400 is increased by a larger increase (f ₂ + k) (box 524) to reduce the slope and increase the consumption speed more quickly. Is increased by.

However, if the amount of digital data symbols is greater than upper limit 2 (UL2), the consumption slope of the digital data symbols from the FIFO buffer to the supply slope of the digital data symbols from the FIFO buffer to the FIFO buffer is again checked (box 526). If the slope indicates that either the consumption rate or the feed rate is not too large, the frequency f ₂ of the jitter management clock 400 is determined by the amount of digital data symbols to greatly reduce the amount of digital data symbols in the FIFO buffer to prevent overruns. Increased by a larger increase f ₂ + I (box 528) to increase the consumption rate. If the consumption slope indicates that the feed rate is too large, the frequency f ₂ of the jitter management clock 400 is greater (f ₂ +/- m) (box to reduce the slope and even increase the consumption rate faster). 530) is increased.

If the amount of digital data symbols present in the FIFO buffer is checked to be less than the lower limit 1 (LL1) (box 508) and if it is found to be less than the lower limit, the jitter management clock 500 is greater than the frequency f _t of the transmit clock 300. It has a large frequency f ₂ and must be lowered to reduce the rate of consumption of digital data symbols from the FIFO buffer. The amount of digital data symbols present in the buffer is first checked (box 532) to be less than the lower limit 2 (LL2). If the amount of digital data symbols is not less than the lower limit 2 (LL2), then the slope of the supply of digital data symbols from the FIFO buffer to the FIFO buffer is checked (box 534). If the slope indicates that the consumption rate or feed rate is not too large, the frequency f ₂ of the jitter management clock 400 is greatly reduced (f ₂ -j) (box 522) to reduce the consumption rate of the digital data symbols. do. If the consumption slope indicates that the feed rate is too large, the frequency f ₂ of the jitter management clock 400 is increased by a larger increase (f ₂ -k) (box 536) to reduce the slope and reduce the consumption rate more quickly. Is reduced by.

However, if the amount of digital data symbols is below the lower limit 2 (LL2), the consumption slope of the digital data symbols from the FIFO buffer to the supply slope of the digital data symbols from the FIFO buffer to the FIFO buffer is again checked (box 540). If the slope indicates that either the consumption rate or the feed rate is not too large, the frequency f ₂ of the jitter management clock 400 is increased in order to further reduce the amount of digital data symbols in the FIFO buffer to prevent overruns. Even by a larger increase (f ₂ -I) (box 542) to reduce their consumption rate. If the consumption slope indicates that the feed rate is too large, the frequency f ₂ of the jitter management clock 400 is reduced larger (f ₂ -m) (box 544) to reduce the slope and reduce the consumption rate faster. .

See FIG. 7B again. If the frame marker is checked (box 440) and no frame marker is detected, the received data is corrupted and invalidated. The buffer is flushed from the FIFO buffer to remove data and the data is discarded (box 480). In applications such as the reproduction of audio signals, digital data symbols must be streamed isochronously. To prevent distortion and undesirable tones, digital data symbols should be set to values that make the audio signal null. Once the FIFO is overflowed (box 180), the next start pattern is detected (box 415) and the digital data symbols recovered from the modulated signal are placed in a buffer (box 425) and the process of streaming digital data symbols detects the start pattern. Continue at (box 415).

Buffers and FIFO buffers as described are implemented as random access memory using access control provided by a group of state machines. The group of state machines implements the circuit functions as described above. An arbitrator circuit resolves any simultaneous races of access to write to and read from random access memory. For example, the simultaneous delivery of two sets of data symbols in a frame is achieved by two state machines operating essentially simultaneously but independent of the arbitration circuitry that the state machine determines to write data to the FIFO buffer.

While the invention has been shown and described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Claims (51)

A receiver for obtaining modulated signals, reconstructing the modulated signal, reconstructing symbols of digital data from the modulated signal, and synchronizing the digital data to a first reference signal, A jitter management unit for synchronizing digital data to the first reference signal, the jitter management unit comprising: A FIFO data preservation device for receiving the reconstructed digital data and transmitting the synchronized digital data for further processing; A variable reference signal generator coupled to the FIFO data preservation apparatus to provide the first reference signal to synchronize the digital data; And Generator control connected to receive a marker signal extracted from the modulated signal and in communication with a FIFO data preservation device to receive an occupancy signal indicative of the amount of digital data from the marker signal present in the FIFO data preservation device. And circuitry, wherein the occupancy signal generates a generator control signal for adjusting the reference signal such that the first reference signal is synchronized with the digital data at a timing at which the digital data is transmitted. 2. The apparatus of claim 1, further comprising amplification and conditioning circuitry coupled to receive, reconstruct, and sample a modulated signal, wherein the modulated signal divides a boundary between the digital data bits in the modulated signal. Transitions representing are detected and sampled in multiples of a second reference signal such that the digital data is reconstructed and synchronized to a second reference signal. 3. The buffer data preservation method as recited in claim 2, wherein said buffer data preservation is in communication with said amplification and conditioning circuit for receiving and retaining said reconstructed digital data and in communication with said FIFO data preservation device for delivering said digital data to said FIFO data preservation device. And further comprising a circuit. 4. The receiver of claim 3 wherein the buffer data retention circuit has at least one buffer circuit, each buffer circuit holding a group of digital data symbols. 4. The method of claim 3, wherein the reconstructed digital data is received and the digital data is reorganized in an original sequence of symbols, any errors generated in the transmission of the modulated signal are corrected, the reorganization and And a data modification and deinterleaving circuit in communication with the buffer retention circuit to replace modified digital data. 4. The receiver of claim 3 wherein the buffer data preservation circuit delivers the digital data to the FIFO data preservation device at a rate of a second reference signal. 4. The apparatus of claim 3, wherein the buffer data preserving circuit delivers the digital data to a FIFO data preserving apparatus until the FIFO data preserving apparatus includes a first amount, so that the FIFO data preserving apparatus performs the digital data. To start transmitting, the receiver. 8. The receiver of claim 7, wherein the buffer data preservation circuit conveys all symbols of digital data present between two marker signals to prevent overrun of the digital data. 3. The apparatus of claim 2, wherein the reconstructed digital data is received, and in communication with the amplification and adjustment circuit to extract a marker signal representing a boundary of symbols of the digital data from the reconstructed digital data. And a boundary marker signal detection circuit in communication with the generator control circuit for providing a marker signal. The receiver of claim 1, wherein if the occupancy signal indicates that the FIFO data preservation device comprises a second amount of digital data, the generator control signal indicates that the generator control circuit does not adjust to a second reference signal. . The content of the FIFO data preservation apparatus of claim 1, wherein if the occupancy signal indicates that the FIFO data preservation apparatus contains less than a second amount of digital data, the generator control signal is less than the second amount of digital data. Indicating that the generator control circuit adjusts with respect to a second reference signal to increase. 2. The apparatus of claim 1, wherein if the occupancy signal indicates that the FIFO data preservation device comprises an amount greater than a second amount of digital data, the generator control signal until the generator control signal includes the second amount. Indicating that the generator control circuit adjusts with respect to a second reference signal to reduce the content of the second reference signal. As a data communication system: A frame formatter for encoding digital data into a series of symbols, A transmitter comprising a transmitter in communication with a frame formatter to receive the series of symbols and to transmit a modulated signal consisting of the series of symbols; And A receiving device in communication with the transmitting device for obtaining a modulated signal, reconstructing the modulated signal, reconstructing the symbols of digital data from the modulated signal, and synchronizing the digital data to a first reference signal; , The receiving device includes a jitter management unit for synchronizing digital data with respect to a first reference signal, The jitter management unit is: A FIFO data preservation device for receiving reconstructed digital data and transmitting synchronized digital data for further processing A variable reference signal generator connected to a FIFO data preservation device for providing said first reference signal for synchronization of said digital data, and A generator control circuit in communication with a FIFO data preservation device to receive a marker signal extracted from the modulated signal and to receive an occupancy signal indicative of the amount of digital data from the marker signal present in the FIFO data preservation device; The occupancy signal generates a generator control signal that adjusts the reference signal such that the first reference signal synchronizes the digital data at a timing at which the digital data is transmitted. 14. The apparatus of claim 13, wherein the receiving device further comprises an amplification and conditioning circuit connected to receive, recover, and sample a modulated signal, the modulated signal being between bits of the digital data in the modulated signal. Transitions indicative of a boundary are detected and sampled in multiples of a second reference signal such that the digital data is reconstructed and synchronized to a second reference signal. 15. The apparatus of claim 14, wherein the receiving device is in communication with the amplifying and regulating circuit to receive and maintain the reconstructed digital data, and the FIFO data preserving device to deliver the digital data to the FIFO data preserving device. And a buffer data preserving circuit for communicating. 16. The system of claim 15 wherein the buffer data preserving circuit has at least one buffer circuit, each buffer circuit holding a group of symbols of the digital data. The method of claim 15, wherein the receiving device, Receive the reconstructed digital data and reorganize the digital data into an original sequence of symbols, correct any errors generated in the transmission of the modulated signal, and replace the reorganized and modified digital data in the buffer retention circuit. Further comprising data modification and deinterleaving circuitry in communication with the buffer retention circuitry. The data communication system of claim 15, wherein the buffer data preservation circuit delivers the digital data to the FIFO data preservation device at a rate of a second reference signal. 16. The apparatus of claim 15, wherein the buffer data preservation circuit delivers the digital data to the FIFO data preservation apparatus until the FIFO data preservation apparatus includes a first amount, so that the FIFO data preservation apparatus transmits the digital data. Data communication system. 20. The data communication system according to claim 19, wherein said buffer data preservation circuit carries all symbols of digital data existing between two marker signals to prevent overrun of said digital data. The method of claim 14, wherein the receiving device, Receive the reconstructed digital data, communicate with an amplification and conditioning circuit to extract a marker signal representing a boundary of the digital data symbols from the reconstructed digital data, and provide the marker signal to the generator control circuit. And a boundary marker signal detection circuit in communication with the generator control circuit. The generator control signal of claim 13, wherein if the occupancy signal indicates that the FIFO data preservation device comprises a second amount of digital data, the generator control signal indicates that the generator control circuit does not adjust to a second reference signal. Data communication system. 15. The method of claim 13, wherein if the occupancy signal indicates that the FIFO data preservation device is less than a second amount of digital data, the generator control signal is to increase the content of the FIFO data preservation device until it includes a second amount. A data communication system indicating that a generator control circuit adjusts for said second reference signal. 15. The apparatus of claim 13, wherein if the occupancy signal indicates that the FIFO data preservation device comprises a quantity greater than a second amount of digital data, the generator control signal until the generator control signal includes the second amount. Indicating that the generator control circuitry adjusts to a second reference signal to reduce content. A digital data synchronization circuit for synchronizing digital data clocked in a first reference period to be clocked in a second reference period, the receiver comprising: A FIFO data preservation apparatus for receiving digital data clocked in a first reference period and transmitting digital data synchronized in a second reference period; A variable reference signal generator connected to a FIFO data preservation apparatus to provide a clock having a second reference period for synchronization of the digital data; And Connected to receive a marker signal indicative of the beginning of a group of symbols of the digital data and in communication with a FIFO data preserver to receive an occupancy signal indicative of the amount of digital data from the marker signal present in the FIFO data preserver. A generator control circuit, wherein the occupancy signal generates a generator control signal that adjusts the reference signal such that the clock signal having a second reference period synchronizes the digital data in a second reference period. . 26. The digital data synchronization as claimed in claim 25, wherein the digital data is delivered to a FIFO data storage device until the FIFO data storage device contains a first amount, such that the FIFO data storage device begins to transmit the digital data. Circuit. 27. The digital data synchronization circuit as claimed in claim 26, wherein all symbols of digital data present between two marker signals are passed to a FIFO data preservation device to prevent overrun of the digital data. 26. The apparatus of claim 25, wherein if the occupancy signal indicates that the FIFO data preservation device comprises a second amount of digital data, the generator control signal indicates that the generator control circuit does not adjust to the second reference signal. Data synchronization circuit. 26. The apparatus of claim 25, wherein if the occupancy signal indicates that the FIFO data preservation device contains less than a second amount of digital data, the generator control signal is further configured to retrieve the contents of the FIFO data preservation device until it includes the second amount. Indicating that the generator control circuit adjusts to a second reference signal to increase. 27. The apparatus of claim 25, wherein if the occupancy signal indicates that the FIFO data preservation device comprises an amount greater than a second amount of digital data, then a generator control signal is generated until the FIFO data preservation device includes the second amount. And the generator control circuitry adjusts to a second reference signal to reduce content. A method of synchronizing digital data timed by a clock having a first period delivered to a circuit having a clock having a second period, the method comprising: Providing a FIFO data preservation apparatus; Delivering the digital data to the FIFO data preservation apparatus having a clock having a first period of time; Transferring the digital data from the FIFO data preservation apparatus having a clock having a second period of time; Monitoring an occupancy signal from the FIFO data preservation device, the amount of digital data present in the FIFO data preservation device; Monitoring a marker signal indicative of a boundary between the digital data groups; And Adjusting the clock of the second period to synchronize the digital data in the second clock period, in accordance with the occupancy signal and the marker signal. 32. The method of claim 31, wherein delivering the digital data to the FIFO data preserving device occurs until the FIFO data preserving device includes a first amount, thereby transferring the digital data from the FIFO data preserving device. Is initiated, digital data synchronization method. 32. The digital data of claim 31 wherein all symbols of digital data present between two marker signals are passed to a FIFO data preservation device in a time period between the two markers to prevent overrun of the digital data. Motive method. 32. The method of claim 31, wherein if the occupied signal indicates that the FIFO data preservation device includes a second amount of digital data, then no clock adjustment with a second period is made. 32. The apparatus of claim 31, wherein if the occupying signal indicates that the FIFO data preservation device contains less than a second amount of digital data, the clock with a second period until the second amount includes the second amount of the FIFO data preservation device. Adjusting a clock having a second period to increase the content of the digital data synchronization method. 32. The method of claim 31, wherein if the occupancy signal indicates that the FIFO data preservation device includes a greater amount than the second amount of digital data, reducing the content of the FIFO data preservation device until the second amount is included. Adjusting the clock of the second period to adjust for a clock having a second period of time. A method of receiving digital data transmitted at a first clock speed, the method comprising: Obtaining and restoring modulated signals, wherein the modulated signals are modulated by the digital data; Reconstructing and synchronizing symbols of digital data from the modulated signal with a clock having a first period of time; And Provide FIFO data preservation device, Deliver the digital data to the FIFO data preservation device with a clock having a first period of time, Transfer the digital data from the FIFO data preservation device to a clock having a second period of time, Monitor an occupancy signal from the FIFO data saver, the amount of digital data present in the FIFO data saver, Monitor marker signals indicative of boundaries between the digital data groups, and According to the occupancy signal and the marker signal, adjusting the clock of the second period to synchronize the digital data with respect to the second clock period, the symbol being provided in a circuit with a clock having a second period. And transmitting the data. 38. The method of claim 37, further comprising extracting a marker signal from the modulated signal. 38. The method of claim 37, further comprising correcting errors that occur during transmission of the modulated signal. 38. The method of claim 37, further comprising deinterleaving the digital data to reorganize the digital data in an original sequence of symbols. 38. The method of claim 37, wherein delivering the digital data to a FIFO data preserving device occurs until the FIFO data preserving device includes a first amount, thereby transferring the digital data from the FIFO data preserving device. Started digital data reception method. 38. The digital data reception of claim 37, wherein all symbols of digital data present between two marker signals are transferred to a FIFO data preservation device in a time period between the two markers to prevent overrun of the digital data. Way. 38. The method of claim 37, wherein if the occupancy signal indicates that the FIFO data preservation device comprises a second amount of digital data, then the clock having the second period is not adjusted. 38. The apparatus of claim 37, wherein if the occupying signal indicates that the FIFO data preservation device contains less than a second amount of digital data, the clock with a second period until the second amount includes the second amount of the FIFO data preservation device. Adjusting a clock having a second period to increase the content of the digital data. 38. The method of claim 37, wherein if the occupying signal indicates that the FIFO data preservation device includes an amount greater than a second amount of digital data, the clock with a second period until the second amount is included retains the FIFO data. Adjusting the clock with the second period of time to reduce the content of the device. A method for communicating digital data from a first location to a second location, comprising: Transmitting a modulated signal modulated by the digital data synchronized at a first clock rate; And Receiving the digital data, Receiving the data includes: Obtaining and restoring modulated signals; Reconstructing and synchronizing symbols of digital data from the modulated signal with a clock having a first period of time; And Executed by transferring said symbol to a circuit having a clock having a second period of time, Passing the symbols includes: Providing a FIFO data preservation apparatus; Delivering the digital data to the FIFO data preservation apparatus at a clock having a first period of time; Transferring the digital data from the FIFO data preservation apparatus to a clock having a second period of time; Monitoring an occupancy signal from the FIFO data preservation device indicative of the amount of digital data present in the FIFO data preservation device; Monitoring a marker signal indicative of a boundary between the group of digital data; And Adjusting the clock of the second period to synchronize the digital data with the second clock period in accordance with the occupancy signal and the marker signal. 47. The method of claim 46, wherein receiving digital data further comprises extracting a marker signal from the modulated signal. 47. The digital data of claim 46, wherein the digital data transfer to a FIFO data preservation apparatus occurs until the FIFO data preservation apparatus includes a first amount, such that the digital data transfer from the FIFO data preservation apparatus begins. Communication method. 47. The digital data communication of claim 46, wherein all symbols of digital data present between two marker signals are transferred to a FIFO data preservation device in a time period between the two markers to prevent overrun of the digital data. Way. 47. The method of claim 46, wherein if the occupancy signal indicates that the FIFO data preservation device comprises a second amount of digital data, then the clock with the second period is not adjusted. 47. The apparatus of claim 46, wherein if the occupying signal indicates that the FIFO data preservation device is less than a second amount of digital data, then a clock with a second period until the second amount includes the second amount is configured to retrieve content of the FIFO data preservation device. Adjusting a clock with a second period of time to increase.

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