1298542 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種薄膜電晶體及其製造方法，且特 別是有關於-種使用此薄膜陣列基板之顯示面板。 【先前技術】 近年來光電相關技術不斷推陳出新，加上數位化時代 的到來，進而推動了液晶顯示器市場的蓬勃發展。液晶顯 示器（Liquid Crystal Displayer ; LCD)具有高晝質、體積小、 重董輕、低電壓驅動、低消耗功率及應用範圍廣等優點， 因此被廣泛地應用於可攜式電視、行動電話、筆記型電腦 以及桌上型顯示器等消費性電子或電腦產品，並逐漸取代 陰極射線管（Cathode Ray Tube ; CRT)成為顯示器的主流。 液晶顯不器之所以能夠較傳統之陰極射線管顯示器在 尺寸及重量上更具有彈性，是因為液晶顯示器的大部分元 件都疋平板狀，例如驅動顯示器的薄膜電晶體（Thin_Film Transistor ; TFT)陣列基板，與決定晝素明暗狀態的彩色濾 光片（color filter)基板。因此，可視應用需求將這些元件切 割成大小適中的尺寸，且在重量上也比具有龐大立體外形 的陰極射線管來得輕巧許多。 眾所皆知光罩的價格昂貴，且曝光顯影的步驟又相當 費時，所以減少光罩數目除了可降低成本之外，還可以加 速產出速度’以提南產品的競爭力。因此，許多廠商莫不 努力於減少光罩的使用次數。一種半透光罩（half t〇ne mask) 即發展來節省製程中所需光罩的數目。 6 1298542 在現今薄膜電晶體陣列基板的製程中，光罩的使用數 目已可縮減到五道或四道光罩製程。以一般四道光罩製程 為例，請參照第1圖，係繪示習知製作薄膜電晶體之結構 示意圖。在第1圖中，在玻璃基板100上形成閘極1〇2之 後，依序形成絕緣層104、半導體層1〇6、歐姆接觸層1〇8 與金屬層110於玻璃基板100與閘極1〇2之上。接著，在 塗佈光阻層（未繪示於圖上）於金屬層11〇上之後，以半透光 罩來進行曝光顯影的步驟以形成光阻層112。其中，光阻層 112係位於閘極102的上方預形成源/汲極及通道區的區二 成U字型狀，且光阻層112在預定形成通道區的位置具有 一較小的厚度ηι，而光阻層112其他部分的區域具有一較 大的厚度H2。 接著，以光阻層112為罩幕，蝕刻未為光阻層112所 覆蓋之金屬層110。再移除部分之光阻層112，以暴露出位 於通道區上方之金屬層110。然後，選擇性蝕刻金屬層110、 歐姆接觸層H)8及半導體層，以定義线/㈣與通道 區。隨後，再依序於玻璃基板刚上形成保護層與透明導 電層，以完成薄膜電晶體與畫素電極之電性連接。 請參照第2圖’係繪示習知製作薄膜電晶體餘刻金屬 層之後之剖面示意圖。由第2圖可看出，由於在習知钱刻 金屬層110的姓刻係採用濕式姓刻製程，在以光阻層山 為罩幕對金制110進行濕式㈣時，由於濕式^係為 一均向㈣，所以在光阻層112兩側底下之部分金屬層11〇 也曰被蝴掉，而產生底切（undereut)。此時，如第2圖所 示’敍刻後的金屬| 11〇之側壁會呈現近似垂直的輪廓 7 1298542 (profile)且已退至光阻層112之下方内側，故在後續蝕刻半 導體層106及歐姆接觸層1〇8的非均向蝕刻製程中，金屬 層110則無法再蝕刻出一較為平緩的輪廓。因此，金屬層 11〇之側壁仍然具有一接近90。之傾斜角度（taper angie)。 第3圖係繪示完成半導體層、歐姆接觸層與金屬層蝕 刻並形成透明導電層後之剖面示意圖。然而，由於金屬層 11〇之側壁的傾斜角度接近90。，所以形成於金屬層11〇之 側壁上之保濩層118則會產生突懸（overhang)，故在後續利 用濺鍍法來形成於保護層118上的透明導電層12〇則無法 完整地沉積於保護層118之上，而會發生導線斷裂的現象。 如此一來，不僅造成薄膜電晶體與畫素電極之電性連接失 敗的問題，更使得生產良率降低，並同時增加製造成本。 因此，有必要提供一種新的薄膜電晶體的製造方法， 以解決上述之問題。 【發明内容】 因此本發明的目的就是在提供一種薄膜電晶體及其製 造方法，用以減少薄膜電晶體與畫素電極之電性連接失敗 的問題。 本發明的另一目的是在提供一種薄膜電晶體及其製造 方法，以提高產品良率並降低製造成本。 根據本發明之目的，提出一種薄膜電晶體之製造方 法。根據本發明之一較佳實施例，係先於基板上形成閘極。 接著，在基板及閘極上方依序沉積絕緣層、半導體層、歐 姆接觸層與金屬層。再於金屬層上塗佈光阻，並利用改良 8 1298542 之半調式光罩對光阻曝光顯影，而形成圖案化光阻層。 上述之圖案化光阻層具有至少一第一部份、至少一第 、口p伤與至少一第三部份。其中，第一部份係位於預定形 成通道區的上方，第二部份係位於預定形成源/汲極的上 方，而第三部份係位於部分第二部分之一側且遠離第一部 份。 接著’利用過餘刻製程移除未為圖案化光阻層所覆蓋 之金屬層。然後’移除部分之圖案化光阻層直至通道區上 方之金屬層暴露出為止。以金屬層為罩幕移除未為金屬層 所覆蓋之歐姆接觸層與半導體層，直至絕緣層暴露出來為 止。 後刻未為光阻層所覆蓋之金屬層、歐姆接觸層 與部分閘極上方的半導體層，以定義出源/汲極與通道區。 此時’在與後續將形成之畫素電極相鄰之源/汲極的一侧會 形成一傾斜側邊。接著，剝除殘留於金屬層上之光阻層， 以形成薄膜電晶體。最後，在完成薄膜電晶體之後，接著 形成保護層與透明導電層於金屬層與基板之上，以完成薄 膜電晶體與晝素電極之電性連接。 或者’依照本發明之另一較佳實施例，更可以在對金 屬層進行過蝕刻製程之後，先以圖案化光阻層為罩幕蝕刻 未為圖案化光阻層所覆蓋之歐姆接觸層與半導體層，直至 絕緣層暴露出來為止。然後，移除部分之圖案化光阻層直 至通道區上方之金屬層暴露出為止。 隨後’再蚀刻未為光阻層所覆蓋之金屬層、歐姆接觸 層與部分閘極上方的半導體層，以定義出源/汲極與通道 9 1298542 區。接著’剝除殘留於金屬層上之光阻層，以形成薄膜電 晶體。最後，形成保護層與透明導電層於金屬層與基板之 上，以完成薄膜電晶體與畫素電極之電性連接。 由上述可知，應用本發明之方法可以在與後續將形成 之晝素電極相鄰之源/汲極的一侧之侧壁上蝕刻出一較為 平緩的輪廓，以降低在後續畫素電極之形成時的階梯覆蓋 困難度’進而降低薄膜電晶體與畫素電極之電性連接失敗 的問題。除此之外，應用本發明之方法更可以提高產品良 率，且同時降低製造成本。 本發明並不僅限於應用在液晶顯示器中薄膜電晶體之 製程中’任何於基板上形成薄膜電晶體之製造技術，例如 應用於有機電激發光顯示器（organic electro-luminescence display ; OELD)上，都可運用本發明所揭露的方法來解決 沉積材料層以覆蓋薄膜電晶體時產生之階梯覆蓋性不佳的 問題。 【實施方式】 本發明提出一種能降低在後續畫素電極之形成時的階 梯覆蓋困難度之方法，進而降低薄膜電晶體與畫素電極之 電性連接失敗的問題。以下將以圖示及詳細說明來清楚闡 述本發明之精神，如熟悉此技術之人員在瞭解本發明之較 佳實施例後，當可由本發明所揭示之技術，加以改變及修 飾’其並不脫離本發明之精神與範圍。 睛參照第4圖，其係繪示依照本發明一較佳實施例之 於基板上形成閘極、絕緣層、半導體層、歐姆接觸層與金 1298542 ’，儿積導體層（未繪示）於基板2〇〇[Technical Field] The present invention relates to a thin film transistor and a method of manufacturing the same, and in particular to a display panel using the film array substrate. [Prior Art] In recent years, the optoelectronic related technology has been continuously updated, and the arrival of the digital era has promoted the vigorous development of the liquid crystal display market. Liquid crystal display (LCD) is widely used in portable TVs, mobile phones, and notebooks because of its high quality, small size, light weight, low voltage drive, low power consumption, and wide application range. Consumer electronics or computer products such as computers and desktop displays have gradually replaced cathode ray tubes (CRTs) as the mainstream of displays. The reason why the liquid crystal display device is more flexible in size and weight than the conventional cathode ray tube display is that most of the components of the liquid crystal display are flat, such as a thin film transistor (TFT) array for driving the display. The substrate, and a color filter substrate that determines the brightness of the halogen. Therefore, these components can be cut to a moderately sized size for visual application requirements and are much lighter in weight than cathode ray tubes having a large three-dimensional shape. It is well known that photomasks are expensive and the steps of exposure and development are quite time consuming. Therefore, in addition to reducing the number of masks, the speed of output can be increased to increase the competitiveness of the products. Therefore, many manufacturers do not strive to reduce the number of times the mask is used. A half-transparent mask is developed to save the number of masks required in the process. 6 1298542 In the current process of thin film transistor array substrates, the number of masks can be reduced to five or four mask processes. Taking a general four-mask process as an example, please refer to Fig. 1, which is a schematic view showing the structure of a conventional thin film transistor. In FIG. 1, after the gate electrode 1 is formed on the glass substrate 100, the insulating layer 104, the semiconductor layer 1〇6, the ohmic contact layer 1〇8, and the metal layer 110 are sequentially formed on the glass substrate 100 and the gate 1 Above 〇2. Next, after applying a photoresist layer (not shown) on the metal layer 11A, a step of exposure development is performed with a semi-transmissive cover to form the photoresist layer 112. Wherein, the photoresist layer 112 is located above the gate 102 and pre-forms the source/drain and the channel region into a U-shape, and the photoresist layer 112 has a small thickness ηι at a position where the channel region is predetermined to be formed. The region of the other portion of the photoresist layer 112 has a large thickness H2. Next, the photoresist layer 112 is used as a mask to etch the metal layer 110 not covered by the photoresist layer 112. A portion of the photoresist layer 112 is removed to expose the metal layer 110 above the channel region. Then, the metal layer 110, the ohmic contact layer H) 8 and the semiconductor layer are selectively etched to define a line/(iv) and a channel region. Subsequently, a protective layer and a transparent conductive layer are formed on the glass substrate in order to complete the electrical connection between the thin film transistor and the pixel electrode. Referring to Fig. 2, a schematic cross-sectional view showing a conventional metal film of a thin film transistor is shown. It can be seen from Fig. 2 that since the surname of the metal layer 110 is a wet type engraving process, when the gold 110 is wet-typed (four) with the photoresist layer mountain as a mask, due to the wet type ^ is a uniform (4), so part of the metal layer 11 underneath the photoresist layer 112 is also bounced off, resulting in an undercut. At this time, as shown in FIG. 2, the sidewall of the metal after the engraving will exhibit an approximately vertical profile 7 1298542 profile and has retreated to the lower inner side of the photoresist layer 112, so that the semiconductor layer 106 is subsequently etched. In the non-uniform etching process of the ohmic contact layer 1〇8, the metal layer 110 can no longer etch a relatively flat profile. Therefore, the side walls of the metal layer 11 have a close to 90. The angle of inclination (taper angie). Fig. 3 is a schematic cross-sectional view showing completion of etching of the semiconductor layer, the ohmic contact layer and the metal layer and forming a transparent conductive layer. However, since the inclination angle of the side wall of the metal layer 11 is close to 90. Therefore, the protective layer 118 formed on the sidewall of the metal layer 11 is overhanged, so that the transparent conductive layer 12 formed on the protective layer 118 by sputtering is not completely deposited. Above the layer 118, a phenomenon of wire breakage occurs. As a result, not only the problem of the electrical connection between the thin film transistor and the pixel electrode is lost, but also the production yield is lowered, and at the same time, the manufacturing cost is increased. Therefore, it is necessary to provide a new method of manufacturing a thin film transistor to solve the above problems. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a thin film transistor and a method of fabricating the same that are used to reduce the problem of failure of electrical connection between a thin film transistor and a pixel electrode. Another object of the present invention is to provide a thin film transistor and a method of manufacturing the same to improve product yield and reduce manufacturing cost. According to the purpose of the present invention, a method of manufacturing a thin film transistor is proposed. In accordance with a preferred embodiment of the present invention, a gate is formed prior to the substrate. Next, an insulating layer, a semiconductor layer, an ohmic contact layer, and a metal layer are sequentially deposited over the substrate and the gate. A photoresist is then coated on the metal layer, and the photoresist is exposed and developed using a modified halftone mask of 12 1298542 to form a patterned photoresist layer. The patterned photoresist layer has at least a first portion, at least one of the first and second ports, and at least a third portion. Wherein the first portion is located above the predetermined channel region, the second portion is located above the predetermined source/drain, and the third portion is located on one side of the second portion and away from the first portion . The metal layer not covered by the patterned photoresist layer is then removed using a residual process. A portion of the patterned photoresist layer is then removed until the metal layer above the channel region is exposed. The ohmic contact layer and the semiconductor layer not covered by the metal layer are removed by the metal layer as a mask until the insulating layer is exposed. The metal layer overlying the photoresist layer, the ohmic contact layer and the semiconductor layer above the gate are not defined to define the source/drain and channel regions. At this time, an inclined side is formed on the side of the source/drain which is adjacent to the pixel electrode to be formed later. Next, the photoresist layer remaining on the metal layer is stripped to form a thin film transistor. Finally, after the thin film transistor is completed, a protective layer and a transparent conductive layer are formed on the metal layer and the substrate to complete electrical connection between the thin film transistor and the halogen electrode. Or, according to another preferred embodiment of the present invention, after the over-etching process of the metal layer, the ohmic contact layer not covered by the patterned photoresist layer is etched by using the patterned photoresist layer as a mask. The semiconductor layer until the insulating layer is exposed. Then, a portion of the patterned photoresist layer is removed until the metal layer above the channel region is exposed. The metal layer overlying the photoresist layer, the ohmic contact layer and the semiconductor layer over the portion of the gate are then etched back to define the source/drain and channel 9 1298542 regions. Next, the photoresist layer remaining on the metal layer is stripped to form a thin film transistor. Finally, a protective layer and a transparent conductive layer are formed on the metal layer and the substrate to complete electrical connection between the thin film transistor and the pixel electrode. It can be seen from the above that the method of the present invention can etch a relatively gentle profile on the sidewall of the side of the source/drain adjacent to the subsequently formed halogen electrode to reduce the formation of subsequent pixel electrodes. The step coverage difficulty of the time' further reduces the problem of failure of the electrical connection between the thin film transistor and the pixel electrode. In addition to this, the application of the method of the present invention can further improve product yield while reducing manufacturing costs. The present invention is not limited to the manufacturing process of forming a thin film transistor on a substrate in a process of a thin film transistor in a liquid crystal display, for example, applied to an organic electro-luminescence display (OELD). The method disclosed in the present invention solves the problem of poor step coverage when depositing a material layer to cover a thin film transistor. [Embodiment] The present invention proposes a method for reducing the difficulty of step coverage in the formation of a subsequent pixel electrode, thereby reducing the problem of failure in electrical connection between the thin film transistor and the pixel electrode. The spirit and scope of the present invention will be apparent from the following description of the preferred embodiments of the invention. It is within the spirit and scope of the invention. Referring to FIG. 4, a gate, an insulating layer, a semiconductor layer, an ohmic contact layer and a gold 1298542' are formed on a substrate according to a preferred embodiment of the present invention, and a conductor layer (not shown) is disposed on the substrate. Substrate 2〇〇
鈦、銀或上述材質之任意組合， 屬層之剖面示意圖。首先， 上，再以第一道光罩製寇定 丨圭材質是銷、銘、銅、鉻、 且導體層可以是上述材質 所形成之單層或多層結構。 接著，於基板·與閘極2G2上方依序沉積絕緣層 204、半導體層206、歐姆接觸層2〇8與金屬層其中， 上述之絕緣層204的較佳材質是氮化梦、氮氧化妙、氧化 矽或上述材質所形成之單層或多層結構。半導體層之 較佳材質是非晶石夕、多晶石夕、微晶㈣上述任^合所形 成之群組。上述之歐姆接觸層2〇8之摻雜材質較佳可為n 型摻雜或P型摻雜。金屬層210的較佳材質是鉬、鋁、銅、 鉻、鈦、銀或上述材質之任意組合所形成之合金或多層金 屬層所組成之群組。 為了降低在後續晝素電極之形成時的階梯覆蓋困難 度，本發明之一較佳實施例係利用一改良之半調式光罩， 以於曝光顯影後形成不同厚度之圖案化光阻層。請參照第5 圖，係繪示依據本發明之一較佳實施例之一種光罩之設計 圖。在第二道光罩製程中所使用的光罩400之設計圖上， 除了在預形成源/没極與通道區的區域設計圖案光罩41〇a 之外，更於預形成源/汲極與畫素電極連接處增加了圖案光 罩410b，以於多階曝光之後形成不同厚度的圖案化光阻 層。且，本較佳實施例係以U型圖案光罩410a及L型圖案 罩410b為範例，分別當作預形成源/汲極與通道區的區域 11 1298542 之圖案光罩，以及預形成源/汲極與晝素電極連接處之圖案 光罩。其中，上述之光罩較佳係採半透光罩（half-tone mask) '灰階光罩（gray level mask)或柵狀圖案光罩（siit pattern mask)。Titanium, silver or any combination of the above materials, is a schematic cross-sectional view of the layer. First, the upper layer is made of the first mask. The material is pin, inscription, copper, and chrome, and the conductor layer may be a single layer or a multilayer structure formed by the above materials. Next, an insulating layer 204, a semiconductor layer 206, an ohmic contact layer 2〇8, and a metal layer are sequentially deposited over the substrate and the gate 2G2. The preferred material of the insulating layer 204 is a nitrided, nitrous oxide, A single layer or a multilayer structure formed of cerium oxide or the above materials. A preferred material of the semiconductor layer is a group formed by the above-mentioned any combination of amorphous rock, polycrystalline stone, and microcrystalline (4). The doping material of the ohmic contact layer 2〇8 described above may preferably be an n-type doping or a P-type doping. The preferred material of the metal layer 210 is a group of alloys or a plurality of metal layers formed of molybdenum, aluminum, copper, chromium, titanium, silver or any combination of the above materials. In order to reduce the difficulty of step coverage in the formation of subsequent halogen electrodes, a preferred embodiment of the present invention utilizes a modified halftone mask to form patterned photoresist layers of different thicknesses after exposure and development. Referring to Figure 5, there is shown a plan view of a reticle in accordance with a preferred embodiment of the present invention. In the design of the reticle 400 used in the second mask process, in addition to designing the pattern mask 41〇a in the region where the source/dipole and channel regions are pre-formed, the source/drain is further formed. A pattern mask 410b is added to the pixel electrode junction to form a patterned photoresist layer of different thickness after the multi-step exposure. Moreover, the preferred embodiment is exemplified by a U-shaped pattern mask 410a and an L-shaped pattern cover 410b, respectively, as a pattern mask for pre-forming the source/drainage and channel region 11 1298542, and a pre-formed source/ A pattern mask at the junction of the bungee and the halogen electrode. Preferably, the photomask described above adopts a half-tone mask 'gray level mask' or a siit pattern mask.
請參照第6圖，係繪示依據本發明之一較佳實施例之 形成圖案化光阻層於金屬層上之剖面示意圖。於塗佈光阻 層（未繪示）於金屬層210上之後，利用第5圖中之光罩400 對光阻層（未繪示）曝光顯影’以於閘極202與遠離閘極202 一側上方之金屬層210上形成圖案化光阻層212。 其中，上述之圖案化光阻層212具有第一部份212a、 第二部份212b與第三部份212c。第一部份212a係位於預 定形成通道區的上方，且第一部份212a之厚度為h卜第二 部份212b係位於預定形成源/汲極的上方，且第二部份21沘 之厚度為h2。第三部份212c係位於部分之第二部份2nb 之-側遠離第-㈣212a，且第三部份2以 h3。其中’第二部份212b之厚度h2係分別大於第一部份 21^厚㈣與第三部份仙之厚度b而第-部份212a 可以大於等於或小於第三部份2i2c之厚度h3。 在本發明之一較佳實施例中，第一 大於第三部份仙之厚度…&212a之厚度㈣ 接：’請參照第7 ，係繪示依據本發明 把例之姓刻金屬層後之剖面示意圖。在第7圖中 實 過钱刻製程，以移除未為圖案化光阻層212所覆蓋之= 層2U)。其中，上述之祕程較佳m 於對金屬層2Π)所進行的蝴製程係程由 1298542 所以在圖案化光阻層212下方之金屬層210會被蝕刻掉， 而產生底切（undercut)。此時，蝕刻後的金屬層210之侧壁 會呈現近似垂直的輪廓（pr〇file)且已退至圖案化光阻層212 下方内側。 請參照第8A至8E圖，係繪示依據本發明之一較佳實 施例之一種製造薄膜電晶體之製程步驟的結榛示意圖。在 苐8A圖中’藉由一灰化製程（Ashing process )移除部分 之圖案化光阻層212直至通道區上方之金屬層210暴露出 為止。由於圖案化光阻層212具有不同厚度，所以在此步 驟中厚度小於第二部份212b之第一部份212a與第三部份 212c會先被移除掉，而暴露出預形成通道區上方之金屬層 210與部分位於閘極202 —側上方之金屬層210。在本較佳 實施例中，係以氧氣為蝕刻劑的蝕刻製程來移除部分的圖 案化光阻層212，但亦不以此為限。 接著，如第8B圖所示，以金屬層210為罩幕，利用乾 #刻製私來移除未為金羼層210所覆蓋之歐姆接觸層208 與半導體層206,直至絕緣層204暴露出來為止。其中，上 述之乾蝕刻製程較佳係以SFVC12為蝕刻劑的電漿蝕刻製 程。 隨後，如第8C圖所示，蝕刻未為光阻層212a所覆蓋 之金屬層210、歐姆接觸層208與部分的半導體層2〇6，以 定義出源/汲極207a、207b與通道區209。此時，在與後續 將形成之晝素電極相鄰之源/汲極207b的一側會形成具有 第一斜角之側邊214,且在該處之部分半導體層2〇6合 一階梯狀的側邊。 θ 13 1298542 接著，剝除殘留於金屬層210上之圖案化光阻層 212a，以形成如第8D圖所示之薄膜電晶體結構。此時，除 了在與後續將形成之畫素電極相鄰之源/汲極207b的一側 會形成具有第一斜角之侧邊214之外，且位於薄膜電晶體 另側的源/汲極207b之外側具有第二斜角之侧邊216(如第9 圖所示’係緣示依據本發明之一較佳實施例之一種薄膜電 晶體之俯視圖，且第8A至8E圖係沿著第9圖中之1-1，切 線之製程步驟之剖面示意圖。），具有第二斜角之侧邊係相 鄰於第一斜角侧邊214。根據本發明之較佳實施例，上述之 第二斜角之角度係大於第一斜角之角度。 最後，如第8E圖所示（請同時參照第9圖），先於金屬 層210與基板200上形成絕緣的保護層218。再以第三道光 罩製程微影钱刻保護層218，以於源/没極207a、207b上方 形成接觸窗220。隨後，形成透明導電層22〇於保護層218 上，並填滿源/没極207a、207b上之接觸窗220。再以第四 道光罩製程對透明導電層220進行微影及蝕刻製程，移除 位於通道區209上方之透明導電層220以定義出畫素電 極。如此一來，即可完成薄膜電晶體與畫素電極之電性連 接。其中，上述之透明導電層222的材質可以為銦錫氧化 物、銦鋅氧化物、鋁鋅氧化物、氧化銦或是氧化錫。 參照第10圖，其繪示依照本發明一較佳實施例之一種 製造薄膜電晶體的流程示意圖（請同時參照第4至8E圖）。 步驟304中，依序沉積絕緣層、半導體層、歐姆接觸層與 金屬層於基板及閘極上。接著，在形成圖案化光阻層於金 屬層之上（步驟306)之後，對金屬層進行一過蝕刻製程（步 1298542 驟308)。然後，在移除部分之圖案化光阻層（步驟31〇)之 後，蝕刻歐姆接觸層與半導體層（步驟312)。隨後，在蝕刻 金屬層、歐姆接觸層與半導體層（步驟3 14)之後，移除圖案 化光阻層（步驟316)。最後，依序形成保護層與透明導電層 於基板上（步驟318)。 印參照弟11A至11D圖，其緣示依照本發明之另一較 佳實施例之一種製作薄膜電晶體之製程流程的剖面示意圖 (請同時參照第10圖）。首先，如同上述之一較佳實施例， 依序沉積絕緣層204、半導體層206、歐姆接觸層208與金 屬層210於基板200及閘極202上（步驟304)。接著，形成 圖案化光阻層212於金屬層210之上（步驟306)。接著，對 金屬層210進行一過蝕刻製程（步驟3〇8)以移除未為圖案 化光阻層212所覆蓋之金屬層21〇。由於在圖案化光阻層 下方之金屬層210會被姓刻掉，而產生底切（uncjercut)， 所以蝕刻後的金屬層210之側壁也會呈現近似垂直的輪廓 (profile)且已退至圖案化光阻層212下方内側。 然而’不同於上述之一較佳實施例係為，在以灰化製 程移除部分光阻層（步驟310)之前，先蝕刻歐姆接觸層2〇8 與半導體層206(步驟312)直至絕緣層204暴露出來為止， 如第11A圖所示。然後，如第11B圖所示，再以灰化製程 移除部分之圖案化光阻層212a(步驟310)，直至通道區上方 之金屬層210暴露出來為止。 接著’如第11C圖所示，餘刻金屬層210、歐姆接觸 層208與半導體層206(步驟314)，以定義出源/汲極207a、 207b與通道區2〇9。然後，再移除殘留於金屬層上之圖案 15 1298542 化光阻層212a(步驟316)。此時，在與後續將形成之畫素電 極相鄰之源/汲極207b的一側也會形成一具有斜角的傾斜 側邊214,且在該處之部分半導體層2〇6也會形成一階梯狀 的側邊。最後，如第11D圖所示，再依序形成保護層218 與透明導電層222於基板200上（步驟3 18)，以完成完成薄 膜電晶體與晝素電極之電性連接。 由上述可知，應用本發明之方法可以於與後續將形成 之畫素電極相鄰之源/：?及極的一側之側壁上餘刻出一較為 平緩的輪廓’以降低在後續畫素電極之形成時的階梯覆蓋 困難度，進而降低薄膜電晶體與晝素電極之電性連接失敗 的問題。且本發明之方法係提供一種改良之半調式光罩， 以形成不同厚度之圖案化光阻層。除此之外，應用本發明 之方法更可以提高產品良率，且同時降低製造成本。 本發明並不僅限於應用在液晶顯示器中薄膜電晶體之 製程中，任何於基板上形成薄膜電晶體之製造技術，例如 應用於有機電激發光顯示器（organic electr〇-luminescence display ; OELD)上，都可運用本發明所揭露的方法來解決 沉積材料層以覆蓋薄膜電晶體時產生之階梯覆蓋性不佳的 問題。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 16 1298542 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之詳細說明如下： 第1圖，係繪示習知製作薄膜電晶體之流程示意圖。 第2圖，係繪示習知製作薄膜電晶體蝕刻金屬層之後 之剖面不意圖。 第3圖係繪示完成半導體層、歐姆接觸層與金屬層蝕 刻並形成透明導電層後之剖面示意圖。 第4圖’其係繪示依照本發明一較佳實施例之於基板 上形成閘極、絕緣層、半導體層、歐姆接觸層與金屬層之 剖示意圖。 第5圖，係繪示依據本發明之一較佳實施例之一種第 二道光罩之設計圖。 第6圖，係繪示依據本發明之一較佳實施例之形成圖 案化光阻層於金屬層上之剖面示意圖。 第7圖，係繪示依據本發明之一較佳實施例之蝕刻金 屬層後之剖面示意圖。 第8A至8E圖，係繪示依據本發明之一較佳實施例之 一種製造薄膜電晶體之製程步驟的結構示意圖。 第9圖，係繪示依據本發明之一較佳實施例之一種薄 膜電晶體之俯視圖。 第10圖，其繪示依照本發明一較佳實施例之一種製造 薄膜電晶體的流程示意圖。 晴參照第11A至11D圖，其繪示依照本發明之另一較 佳實施例之一種製作薄膜電晶體之製程流程的剖面示意 圖0 17 1298542 【主要元件符號說明】 100、200 :基板 104、204 :絕緣層 108、208 :歐姆接觸層 112、212、212a、212b、212c 212b’ ：圖案化光阻層 214 :第一斜角側邊 218 :保護層 hi〜h3 :厚度 410b : L字型圖案光罩 304〜318 :步驟 102、202 :閘極 106、206 :半導體層 110、210 :金屬層 207a、207b :源/汲極 209 :通道區 216 :第二斜角侧邊 220 :接觸窗 222 :透明導電層 410a : U字型圖案光罩Referring to Figure 6, there is shown a cross-sectional view of a patterned photoresist layer formed on a metal layer in accordance with a preferred embodiment of the present invention. After the photoresist layer (not shown) is coated on the metal layer 210, the photoresist layer (not shown) is exposed and developed by the photomask 400 in FIG. 5 to form the gate 202 and the gate 202 away from the gate 202. A patterned photoresist layer 212 is formed on the metal layer 210 on the upper side. The patterned photoresist layer 212 has a first portion 212a, a second portion 212b and a third portion 212c. The first portion 212a is located above the predetermined channel region, and the thickness of the first portion 212a is h. The second portion 212b is located above the predetermined source/drain, and the thickness of the second portion 21 For h2. The third portion 212c is located on the side of the second portion 2nb of the portion away from the -(four) 212a, and the third portion 2 is at h3. Wherein the thickness h2 of the second portion 212b is greater than the thickness b of the first portion 21^th (four) and the third portion, respectively, and the first portion 212a may be greater than or less than the thickness h3 of the third portion 2i2c. In a preferred embodiment of the present invention, the thickness of the first portion greater than the third portion is equal to the thickness of the second portion (4): "Please refer to the seventh section, which is based on the invention. Schematic diagram of the section. In Fig. 7, the process is performed to remove the layer 2U which is not covered by the patterned photoresist layer 212. Wherein, the above-mentioned secret process is preferably performed on the metal layer 2) by the 1298542. Therefore, the metal layer 210 under the patterned photoresist layer 212 is etched away to produce an undercut. At this time, the sidewall of the etched metal layer 210 exhibits an approximately vertical profile and has retreated to the inner side of the patterned photoresist layer 212. Referring to Figures 8A through 8E, there are shown schematic views of a process for fabricating a thin film transistor in accordance with a preferred embodiment of the present invention. In the Figure 8A, a portion of the patterned photoresist layer 212 is removed by an Ashing process until the metal layer 210 above the channel region is exposed. Since the patterned photoresist layer 212 has different thicknesses, the first portion 212a and the third portion 212c having a thickness smaller than the second portion 212b in this step are removed first, and the pre-formed channel region is exposed. The metal layer 210 and the metal layer 210 partially located on the side of the gate 202. In the preferred embodiment, a portion of the patterned photoresist layer 212 is removed by an etching process using oxygen as an etchant, but is not limited thereto. Next, as shown in FIG. 8B, the ohmic contact layer 208 and the semiconductor layer 206 not covered by the metal layer 210 are removed by using the metal layer 210 as a mask, until the insulating layer 204 is exposed. until. Preferably, the dry etching process described above is a plasma etching process using SFVC12 as an etchant. Subsequently, as shown in FIG. 8C, the metal layer 210, the ohmic contact layer 208, and a portion of the semiconductor layer 2〇6 not covered by the photoresist layer 212a are etched to define the source/drain electrodes 207a, 207b and the channel region 209. . At this time, a side 214 having a first oblique angle is formed on a side of the source/drain 207b adjacent to the subsequently formed halogen element electrode, and a portion of the semiconductor layer 2〇6 is stepped at a portion thereof. Side of the side. θ 13 1298542 Next, the patterned photoresist layer 212a remaining on the metal layer 210 is stripped to form a thin film transistor structure as shown in Fig. 8D. At this time, except for the side 214 having the first oblique angle formed on the side of the source/drain 207b adjacent to the pixel electrode to be formed later, and the source/drain on the other side of the thin film transistor a side 216 having a second oblique angle on the outer side of 207b (as shown in FIG. 9 is a top view of a thin film transistor according to a preferred embodiment of the present invention, and FIGS. 8A to 8E are along the first 1-1, a cross-sectional view of the process steps of the tangential line.), the side edge having the second bevel angle is adjacent to the first bevel side edge 214. According to a preferred embodiment of the invention, the angle of the second bevel angle is greater than the angle of the first bevel. Finally, as shown in Fig. 8E (please refer to Fig. 9 at the same time), an insulating protective layer 218 is formed on the metal layer 210 and the substrate 200. The protective layer 218 is then etched by a third mask process to form a contact window 220 over the source/dot poles 207a, 207b. Subsequently, a transparent conductive layer 22 is formed over the protective layer 218 and fills the contact window 220 on the source/dot poles 207a, 207b. The transparent conductive layer 220 is then subjected to a lithography and etching process by a fourth mask process to remove the transparent conductive layer 220 above the channel region 209 to define a pixel electrode. In this way, the electrical connection between the thin film transistor and the pixel electrode can be completed. The material of the transparent conductive layer 222 may be indium tin oxide, indium zinc oxide, aluminum zinc oxide, indium oxide or tin oxide. Referring to Figure 10, there is shown a flow diagram of a method of fabricating a thin film transistor in accordance with a preferred embodiment of the present invention (see also Figures 4 through 8E). In step 304, an insulating layer, a semiconductor layer, an ohmic contact layer and a metal layer are sequentially deposited on the substrate and the gate. Next, after forming the patterned photoresist layer over the metal layer (step 306), the metal layer is subjected to an overetch process (step 1298542). Then, after removing portions of the patterned photoresist layer (step 31A), the ohmic contact layer and the semiconductor layer are etched (step 312). Subsequently, after etching the metal layer, the ohmic contact layer and the semiconductor layer (step 314), the patterned photoresist layer is removed (step 316). Finally, a protective layer and a transparent conductive layer are sequentially formed on the substrate (step 318). Referring to Figures 11A through 11D, there is shown a cross-sectional view of a process for fabricating a thin film transistor in accordance with another preferred embodiment of the present invention (please also refer to Fig. 10). First, as in one of the preferred embodiments described above, the insulating layer 204, the semiconductor layer 206, the ohmic contact layer 208, and the metal layer 210 are sequentially deposited on the substrate 200 and the gate 202 (step 304). Next, a patterned photoresist layer 212 is formed over the metal layer 210 (step 306). Next, an over-etching process (step 3〇8) is performed on the metal layer 210 to remove the metal layer 21〇 not covered by the patterned photoresist layer 212. Since the metal layer 210 under the patterned photoresist layer is erased by the surname to produce an uncjercut, the sidewall of the etched metal layer 210 also exhibits an approximately vertical profile and has been retracted to the pattern. The inner side of the photoresist layer 212 is below. However, 'a preferred embodiment from the above is to etch the ohmic contact layer 2〇8 and the semiconductor layer 206 (step 312) until the insulating layer is removed before the partial photoresist layer is removed by the ashing process (step 310). 204 is exposed as shown in Figure 11A. Then, as shown in Fig. 11B, a portion of the patterned photoresist layer 212a is removed by an ashing process (step 310) until the metal layer 210 above the channel region is exposed. Next, as shown in Fig. 11C, the metal layer 210, the ohmic contact layer 208 and the semiconductor layer 206 are left (step 314) to define the source/drain electrodes 207a, 207b and the channel region 2〇9. Then, the pattern 15 1298542 photoresist layer 212a remaining on the metal layer is removed (step 316). At this time, an inclined side 214 having an oblique angle is also formed on the side of the source/drain 207b adjacent to the pixel electrode to be formed later, and a part of the semiconductor layer 2〇6 is also formed there. a stepped side. Finally, as shown in FIG. 11D, the protective layer 218 and the transparent conductive layer 222 are sequentially formed on the substrate 200 (step 3 18) to complete the electrical connection between the thin film transistor and the halogen electrode. It can be seen from the above that the method of the present invention can engrave a relatively gentle profile on the side wall of the source/side and the side adjacent to the pixel electrode to be subsequently formed to lower the subsequent pixel electrode. The step coverage during formation is difficult, and the problem of failure of electrical connection between the thin film transistor and the halogen electrode is reduced. Moreover, the method of the present invention provides an improved halftone mask to form patterned photoresist layers of different thicknesses. In addition to this, the application of the method of the present invention can further improve the yield of the product while reducing the manufacturing cost. The present invention is not limited to the manufacturing process of forming a thin film transistor on a substrate in a process of a thin film transistor in a liquid crystal display, for example, applied to an organic electrified-luminescence display (OELD). The method disclosed in the present invention can be used to solve the problem of poor coverage of the deposited material layer to cover the thin film transistor. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Schematic diagram of the transistor. Fig. 2 is a schematic cross-sectional view showing a conventional method of fabricating a thin film transistor to etch a metal layer. Fig. 3 is a schematic cross-sectional view showing completion of etching of the semiconductor layer, the ohmic contact layer and the metal layer and forming a transparent conductive layer. Fig. 4 is a cross-sectional view showing the formation of a gate electrode, an insulating layer, a semiconductor layer, an ohmic contact layer and a metal layer on a substrate in accordance with a preferred embodiment of the present invention. Figure 5 is a diagram showing the design of a second reticle in accordance with a preferred embodiment of the present invention. Figure 6 is a cross-sectional view showing the formation of a patterned photoresist layer on a metal layer in accordance with a preferred embodiment of the present invention. Figure 7 is a cross-sectional view showing the etching of a metal layer in accordance with a preferred embodiment of the present invention. 8A to 8E are views showing the structure of a process for fabricating a thin film transistor according to a preferred embodiment of the present invention. Figure 9 is a plan view showing a thin film transistor in accordance with a preferred embodiment of the present invention. Figure 10 is a flow chart showing the manufacture of a thin film transistor in accordance with a preferred embodiment of the present invention. FIG. 11A to FIG. 11D are cross-sectional views showing a process flow for fabricating a thin film transistor according to another preferred embodiment of the present invention. 0 17 1298542 [Explanation of main components] 100, 200: substrates 104, 204 : insulating layers 108, 208: ohmic contact layers 112, 212, 212a, 212b, 212c 212b': patterned photoresist layer 214: first beveled side 218: protective layer hi ~ h3: thickness 410b: L-shaped pattern Photomasks 304 to 318: Steps 102, 202: Gates 106, 206: Semiconductor layers 110, 210: Metal layers 207a, 207b: Source/drain 209: Channel region 216: Second oblique side 220: Contact window 222 : Transparent conductive layer 410a : U-shaped pattern mask
1818