1281244 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種半導體晶片封裝架構，特別是關於一種 將部分表面黏著技術中之焊墊移至晶片承載墊下方，可大幅減 少封裝體面積的相關技術。 【先前技術】 • 晶片封裝是在建立ic元件的保護與組織架構，其目的主 要是提供晶片承載與架構保護的功能，以防止在取置的過程中 外力或其他物理性質的破壞和化學性質的侵餘、確保能量的傳 遞路徑與晶片的訊號分佈、避免訊號延遲的產生而影響系統運 作及提供散熱的途徑。由於目前各種高效能的電子產品不斷推 陳出新，且產品的外型設計均走向小且薄的趨勢，例如：網路 通訊產品（mobile phone，PHS，GPS)、訊息產品（PDA，攜帶 式IA，電子書）、消費性電子（電子字典，掌上型電子遊戲機， 股票機，讀卡機）、甚至化學醫療產品或汽車電子工業都朝向 φ 體積小之系統。因此電子封裝的技術也須隨之朝輕、薄、短、 小的方向發展。 就晶片封裝的技術而言，每一顆由晶圓切割所形成的裸晶 片（die)，例如以導線接合(wire bonding)或覆晶接合(flip chip bonding)等模式配置於一承載具（carrier)的表面，其中承載具例 - 如導線架（lead frame)或基板（substrate)，而晶片之主動表面 (active surface)則具有多個接合焊墊(pad)使得晶片得以經由承 載具之傳輸線路及接點而與外部之電子裝置形成電性連通。之 _ 後’再形成一封膠材料將晶片及導線加以包覆’如此即完成一 晶片封裝架構。 1281244 參照第一圖，承載具，例如導線架，係一金屬板經過光阻 ' 塗佈後藉微影蝕刻製程所定義出其上之圖案化線路110，之後 於圖案化線路110上進行表面處理，例如鍍錫、銀或鎳金層 111。參照第二圖，多層壓合板之基材架構，利用上下兩層金 屬板中夾一絕緣層、玻璃預浸布或多層板之内層結構222壓合 而成，將上下兩層金屬板經過微影蝕刻製程定義出圖案化線路 210後，進行表面處理形成鍍錫、銀或鎳金層211後，在各線 路間形成保護層221，再於鍍錫、銀或鎳金層211上形成導電 球220，例如錫球。第三圖所示係利用導線架作為承載具的封 φ 裝結構。圖案化線路110上包含金屬座330，於金屬座330先 後設置黏著層333與晶片335，晶片335藉由導線332電性連 接至圖案化線路110上，再覆以塑封材料334。圖案化線路110 的另一側則是暴露於塑封材料334外，且進行表面處理，例如 鍍錫、銀或鎳金層331。第四圖所示係利用多層板作為承載具 的封裝結構，黏著層433設置於保護層221上，晶片435再設 置於黏著層433上，晶片435藉由導線432電性連接至多層板 結構上。圖案化線路210的另一側之鍍銀或鎳金層211上則設 置導電球220。由上述結構所塑封完成之封裝成品，由其二維 • .平面之上向下俯視，其構造為圖案化線路外露於晶片承載墊之 外，並間隔著晶片藉由導線電性連接至圖案化線路之間距。 雖然傳統利用金屬導線架進行晶片安裝及打線的封裝製 程具有價格低廉及散熱良好的優點，而以多層壓合板輔以其底 _ 部呈陣列式排列之錫球作為引腳，具有在相同尺寸面積下，引 - 腳數可以變多封裝面積可較為縮小的優點。但因現今之電子零 件皆朝向製作體積小、高密度發展，因此傳統以導線架與多層 壓合板為基材進行晶片安裝，受限于其基材的組成使整體封裝 的體積在縮小化的過程仍有其限制。 6 1281244 【發明内容】 本發明目的之一在於提供-種半導體晶片封裝載板芊 於晶片承載塾下，大幅減少封裝部份内縮 寸封裝（wafer level package)之面積 /、迫近晶圓晶片尺 本發明之目的之-係提供一種半導體晶片封裝架構，係依 照現有的導線架基板之封裝流程製作，可於同_批流程中声得 較多的單位封裝產出量，並節省製作成本。 又 為了達到上述目的，-種晶片封褒基板，相對的兩個導電 連接塾之間的-距離小於-晶片承載墊的—邊長。絕緣層覆蓋 於母-導電連接墊上且暴露出導電連接墊的—部分表面，由位 於絕緣層中的導電焊墊覆蓋。如此藉以縮短晶片上電性接點至 焊線墊之間距，以達到晶圓封裝薄小化之目的。 【實施方式】 下面係藉由數個不同的實施例來說明本發明 架構，及利用此載板所製作完成的晶片封裝元件。衣土板 參照第五A ，以習知適當方式製作的導線架基板且有 若干導電連接墊，例如金屬引腳墊50,絕緣層52位於金屬引 :墊50之間以及金屬引腳墊5〇之部分第一表面5〇ι上。於此 實施例中，被絕緣層52暴露出的金屬引腳墊5〇之第一表面 5〇1係位於金屬引腳墊50之一側，且由導電焊墊5ι所覆蓋， 以作為電性傳遞之接點，再者，位於金屬引腳墊5〇之另一側 的第二表面502係暴露於外。可以選擇的，參照第五B圖，與 第五A圖相異之處在於絕緣層52包圍導電焊墊51，即導電^ 墊51的位置挪向金屬引腳墊5〇内側。 參知、第六A圖為根據本發明之另一種封裝載板之實施例 °兒明。與第五圖A相異之處在於金屬引腳墊5〇的第二表面 1281244BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package architecture, and more particularly to a method for moving a pad in a partial surface adhesion technique under a wafer carrier pad to substantially reduce the package area. Related technology. [Prior Art] • Chip package is the protection and organization structure of the ic component. Its purpose is to provide the function of wafer bearing and structure protection to prevent damage and chemical properties of external force or other physical properties during the process of taking. Residual, ensuring the transmission path of energy and the signal distribution of the chip, avoiding the generation of signal delays, affecting system operation and providing heat dissipation. Due to the continuous innovation of various high-performance electronic products, the appearance of the products is trending toward small and thin, such as: mobile phone (PHS, GPS), messaging products (PDA, portable IA, electronic Books), consumer electronics (electronic dictionaries, handheld video game consoles, stock machines, card readers), and even chemical medical products or the automotive electronics industry are all oriented toward φ small systems. Therefore, the technology of electronic packaging must also develop in a light, thin, short, and small direction. In the art of chip packaging, each die formed by wafer dicing is disposed on a carrier (carrier), for example, by wire bonding or flip chip bonding. The surface of the substrate, such as a lead frame or substrate, and the active surface of the wafer has a plurality of bonding pads such that the wafer can be transported via the carrier. And the contacts are in electrical communication with the external electronic device. After the _, a plastic material is formed to coat the wafer and the wires. Thus, a chip package structure is completed. 1281244 Referring to the first figure, a carrier, such as a lead frame, is a metal plate that has been patterned by a photoresist after coating by a photoresist etch process, and then surface-treated on the patterned line 110. For example, tin, silver or nickel gold layer 111. Referring to the second figure, the substrate structure of the multi-laminate ply is formed by pressing the inner layer structure 222 of the upper and lower metal plates with an insulating layer, a glass prepreg or a multi-layer board, and the upper and lower metal plates are subjected to lithography. After the etching process defines the patterned circuit 210, after surface treatment to form a tin-plated, silver or nickel-gold layer 211, a protective layer 221 is formed between the lines, and a conductive ball 220 is formed on the tin-plated, silver or nickel-gold layer 211. , for example, solder balls. The third figure shows the use of a lead frame as the sealing structure of the carrier. The patterned circuit 110 includes a metal holder 330. The metal holder 330 is provided with an adhesive layer 333 and a wafer 335. The wafer 335 is electrically connected to the patterned circuit 110 by a wire 332, and is covered with a molding material 334. The other side of the patterned line 110 is exposed to the outside of the molding compound 334 and is surface treated, such as a tin, silver or nickel gold layer 331. The fourth figure shows a package structure using a multi-layer board as a carrier. The adhesive layer 433 is disposed on the protective layer 221, and the wafer 435 is disposed on the adhesive layer 433. The wafer 435 is electrically connected to the multi-layer board structure by wires 432. . A conductive ball 220 is disposed on the silver-plated or nickel-gold layer 211 on the other side of the patterned line 210. The packaged product finished by the above structure is viewed from above the two-dimensional plane. The patterned circuit is exposed outside the wafer carrier pad, and the wafer is electrically connected to the pattern by wires. The distance between the lines. Although the conventional method of using a metal lead frame for wafer mounting and wire bonding has the advantages of low cost and good heat dissipation, the multi-ply plywood is supplemented by a solder ball whose bottom is arranged in an array, having the same size area. Underneath, the number of pins can be increased by the fact that the package area can be reduced. However, since today's electronic components are oriented toward small size and high density, the conventional wafer mounting with leadframes and multi-laminates is limited by the composition of the substrate, which reduces the volume of the overall package. There are still restrictions. 6 1281244 SUMMARY OF THE INVENTION One object of the present invention is to provide a semiconductor chip package carrier under the wafer carrier, which greatly reduces the area of the wafer level package, and approaches the wafer wafer size. The object of the present invention is to provide a semiconductor chip package structure which is fabricated according to the packaging process of the existing lead frame substrate, which can generate a larger amount of unit package output in the same batch process and save manufacturing costs. In order to achieve the above object, the wafer is sealed on the substrate, and the distance between the opposite two conductive pads is smaller than the length of the side of the wafer carrier pad. The insulating layer covers the mother-conductive connection pad and exposes a portion of the surface of the conductive connection pad, covered by a conductive pad located in the insulating layer. In this way, the distance between the power-on contacts of the wafer and the bonding pads is shortened to achieve the purpose of thinning the package. [Embodiment] The structure of the present invention and the chip package components fabricated by using the carrier are explained by a plurality of different embodiments. Referring to the fifth A, the dressing plate is made of a lead frame substrate prepared in a suitable manner and has a plurality of conductive connecting pads, such as a metal lead pad 50, and the insulating layer 52 is located between the metal lead: pad 50 and the metal pin pad 5〇. Part of the first surface is 5 〇. In this embodiment, the first surface 5〇1 of the metal pin pad 5 exposed by the insulating layer 52 is located on one side of the metal pin pad 50, and is covered by the conductive pad 5ι as electrical property. The junction is transferred, and further, the second surface 502 on the other side of the metal pin pad 5 is exposed to the outside. Alternatively, referring to FIG. 5B, the difference from FIG. 5A is that the insulating layer 52 surrounds the conductive pad 51, that is, the position of the conductive pad 51 is moved to the inside of the metal pin pad 5〇. Reference is made to Figure 6A, which is an embodiment of another package carrier in accordance with the present invention. The difference from the fifth figure A is the second surface of the metal pin pad 5〇 1281244
If 502，即不與絕緣層52及導電焊墊51相銜接之面形成表面金 屬層72，例如鍍錫、銀或鎳金等，作為封裝元件對外傳輸電 性之接點。另一實施例中，參照第六B圖，則是將第六A圖 中的導電焊墊51往金屬引腳墊50内侧放置。 第七A圖為根據本發明之實施例說明另一種封裝載板之 剖面示意圖。參照第七A圖，與第五A圖相異之處，首先在 於導線架基板具有金屬座71位於金屬引腳墊5 〇之間，作此金 屬座71的尺寸小於後續需承載的晶片，也就是說，兩端之金 屬引腳墊50之間的距離小於一晶片承載墊的一邊長。其次， 修 絕緣層52於金屬座71之對應上方的第三表面703，設置開口 空穴暴露出金屬座71，開口空穴之大小亦可小於金屬座71。 另一實施例中，參照第七B圖，則是將第七A圖中的導電焊 墊51往金屬引腳墊50内側放置。 參妝第八A圖為根據本發明之另一實施例說明之承載具 剖面不意圖。與第七A圖相異之處在於金屬引腳墊5〇於另一 表面，即不與絕緣層52及導電焊墊51相銜接之表面，形成表 面金屬層72,作為封裝元件對外傳輸電性之接點。參照第八b 圖，則是將第人A目中的導電焊墊5U主金屬引腳塾5 • 放置。 立第九圖係應用第六A圖之承載具形成的封裝結構剖面示 忍圖。參照第九圖，除了第六A圖中之承載具外，尚包含一 黏著層933，例如導電膠或絕緣谬，置於晶片935與絕緣層 之間、導電連接線932電性連接晶片935與導電焊墊51、以 J封材料934包覆上述結構。第十圖為另一實施例，應用於 :種CMOS感測器晶片，除了第九圖的構造外，肖包含一黏 f層1002位於塑封材料934與上蓋基板1〇〇3，例如玻璃、陶 ，或金屬之間其中因應感測器晶片所需，可不設置 私除或私除於晶片935對應之上方位置的塑封材料934與黏著 1281244 層^)02，/形成-空穴麵。根據上述，晶片935與金屬引 二5〇:呈上下部分重疊的一位置關係，即金屬引腳墊50之 於晶片承載墊的一邊長。第十一圖為應用於一種廢 力感測晶片的實施例，除了第十圖的結構外，於晶片％ 於上蓋基板1003的表面上設置一膠體層11〇1。可以理的了 上述各實施例的承載具亦可使用第五A、第五b 、岡 中所示之無金屬座的封裝基板以及第七A、第七b、第二A ; 與第八B ®中具有金屬座的封裝基板，於此不再費述。 1第十二圖係應用第六B圖之承載具形成的封結構剖面 不思圖。參照第忙圖，係應用於覆晶晶片的封裝結構，於此 實施例中，晶片935與絕緣層52之間不需黏著層，以導電球 1220，例如錫球，固定晶片935且電性連接至導電焊塾Μ， 再以塑封材料934包覆上述結構。第十三圖為另一實施例，盘 第十二圖所述之結構不同之處在於其塑封材料934僅包覆至 與晶片935之背面1301齊平，使晶片背面13〇1外露。可以理 解的，上述實施例之承載具亦可利用第五A、第五B或第六A 圖中所示之無金屬座的封裝基板以及第七A、第七B、第八A 圖與第八B圖中具有金屬座的封裝基板，於此不再贅述。 一立第十四圖係應用第六B圖之承載具形成的封裝結構剖面 不思圖。與第十二圖相異之處在於以導電凸塊14〇1，例如金 凸塊，取代第十二圖中的導電球122〇。可以理解的，此形式 的連接結構亦可應用於如第十三圖之封裝結構，或是利用第五 A、第五B或第六A圖中所示之無金屬座的封裝基板以及第七 A、第七B、第八A圖與第八B圖中具有金屬座的封裝基板， 於此不再贅述。 第十五A、B圖所示係依照本發明之一實施例封裝基材架 構的正面示意圖。兩端或四周設置金屬引腳墊50，複數個金 屬引腳塾50彼此則是間隔設置，兩端之兩個金屬引腳墊5〇之 1281244 間的一距離小於一晶片或晶片承載墊1501大小的一邊長。換 句話說，晶片與每一金屬引腳墊50係呈上下部分重疊的一位 置關係。再者，當一金屬座（圖上未示）欲隔離地設置於導電連 接墊對之間的情形時，可以理解的，金屬座的尺寸會小於晶片 1501大小。If 502, that is, a surface that does not interface with the insulating layer 52 and the conductive pad 51, a surface metal layer 72, such as tin, silver or nickel gold, is formed as a contact point for electrical transmission of the package component. In another embodiment, referring to Figure 6B, the conductive pad 51 of Figure 6A is placed inside the metal pin pad 50. Figure 7A is a cross-sectional view showing another package carrier in accordance with an embodiment of the present invention. Referring to FIG. 7A, the difference from the fifth A diagram is that the lead frame substrate has a metal seat 71 between the metal pin pads 5 ,, and the metal seat 71 is smaller in size than the subsequent wafer to be carried. That is, the distance between the metal pin pads 50 at both ends is less than the length of one side of a wafer carrier pad. Next, the insulating layer 52 is disposed on the corresponding third surface 703 of the metal seat 71, and an opening is provided to expose the metal seat 71. The size of the opening cavity may be smaller than that of the metal seat 71. In another embodiment, referring to FIG. 7B, the conductive pad 51 of FIG. 7A is placed inside the metal pad 50. Fig. 8A is a cross-sectional view of a carrier according to another embodiment of the present invention. The difference from the seventh A is that the metal lead pad 5 is disposed on the other surface, that is, the surface not engaging the insulating layer 52 and the conductive pad 51, and the surface metal layer 72 is formed to transmit electrical properties as a package component. The junction. Referring to the eighth b diagram, the conductive metal pad 5U main metal pin 塾5 • in the first object is placed. The ninth diagram is a cross-sectional view of the package structure formed by the carrier of the sixth drawing. Referring to the ninth figure, in addition to the carrier of FIG. A, an adhesive layer 933, such as a conductive paste or an insulating layer, is disposed between the wafer 935 and the insulating layer, and the conductive connecting line 932 is electrically connected to the wafer 935. The conductive pad 51 is covered with the J sealing material 934. The eleventh embodiment is another embodiment applied to: a CMOS sensor wafer. In addition to the configuration of the ninth figure, the Shaw includes a layer of adhesive layer 1024 located on the molding material 934 and the upper cover substrate 1〇〇3, such as glass and ceramic. Or, between the metals, in response to the sensor wafer, the molding material 934 and the bonding layer 128244 layer/) 02, which are privately or privately disposed at the upper position corresponding to the wafer 935, may not be disposed. According to the above, the wafer 935 and the metal lead are in a positional relationship in which the upper and lower portions are overlapped, that is, the metal pin pad 50 is long on one side of the wafer carrying pad. The eleventh embodiment is an embodiment applied to a waste sensing wafer. Except for the structure of the tenth figure, a colloid layer 11?1 is disposed on the surface of the wafer upper substrate 1003. It can be understood that the carrier of the above embodiments can also use the metal-free package substrate shown in the fifth A, fifth b, and the metal, and the seventh, seventh, second, and second A; The package substrate with a metal seat in ® is not mentioned here. 1 twelfth figure is a cross-section of the sealing structure formed by the carrier of the sixth drawing B. Referring to the first busy diagram, the package structure is applied to a flip chip. In this embodiment, an adhesive layer is not required between the wafer 935 and the insulating layer 52, and the conductive ball 1220, such as a solder ball, is fixed to the wafer 935 and electrically connected. To the conductive pad, the above structure is covered with a molding material 934. The thirteenth embodiment is another embodiment, and the structure described in the twelfth embodiment differs in that the molding material 934 is only coated to be flush with the back surface 1301 of the wafer 935 to expose the wafer back surface 13〇1. It can be understood that the carrier of the above embodiment can also utilize the metal-free package substrate shown in the fifth A, fifth B or sixth A and the seventh, seventh, eighth, and eighth A and A package substrate having a metal seat in FIG. 8B, which will not be described herein. The fourteenth figure is a section of the package structure formed by the carrier of the sixth figure B. The difference from the twelfth figure is that the conductive bumps 14〇1, such as gold bumps, are substituted for the conductive balls 122〇 in the twelfth figure. It can be understood that the connection structure of this form can also be applied to the package structure as in the thirteenth diagram, or the package substrate without the metal seat shown in the fifth A, fifth B or sixth A and the seventh The package substrate having the metal seat in the A, the seventh B, the eighth A, and the eighth B is not described herein. Fifteenth A and B are schematic front views of a package substrate structure in accordance with an embodiment of the present invention. A metal pin pad 50 is disposed at both ends or around, and a plurality of metal pins 塾 50 are spaced apart from each other, and a distance between two metal pin pads 5 1281244 at both ends is smaller than a wafer or wafer carrier pad 1501. One side is long. In other words, the wafer and each of the metal pin pads 50 are in a positional relationship in which the upper and lower portions overlap. Moreover, when a metal seat (not shown) is to be disposed in isolation between the pair of conductive pads, it will be understood that the size of the metal seat will be smaller than the size of the wafer 1501.
根據上述，本發明的特徵之一在於提供一封裝基板架構， 其僅由一金屬板及絕緣層所組成，晶片可直接置於表面黏著技 術中之焊墊上，藉以縮短晶片上電性接點至焊墊之間距，以縮 小封裝體積。 以上所述之實施例僅係為說明本發明之技術思想及特 點，而並非用以限訂本發明之實施可能性，敘述特需細節的目 的，乃是為了使本發明被詳盡的了解，當不能以之限定本發明 之專利範圍。然而，熟習此項技藝之人士當知此並非唯一的解 法在;又有运方創作的精神或所揭露的本質特徵之下，上述的 實施例可以其他的特殊形式呈現，即大凡依本發明所揭示之精 神所作之均等變化祕飾，仍應涵蓋在本發明之專利範圍内。 【圖式簡單說明】 第-圖為習知以導線架封裝的基材結構示意圖。 第二圖為習知以多層基板封裝的基材結構示意圖。 f三圖為習知以第—圖實施晶片封裝的結構示意圖。 習：以第二圖實施晶片封裝的結構示意圖。 明概令，之Γ B圖、第六A圖及第六B圖為根據本發 月概心只施之承載具剖面示意圖。 第七A圖、第七b圖、第 明概令實施之結Me 目弟B®為根據本發 概之具金屬座之承載具剖面示意圖。 弟九圖為根據第六A 夕其从參 圖。 弟、A圖之基材實施晶片封袭的結構示意 10 1281244 弟十圖為根據第六A圖之基材實施CMOS感測晶片封裝 的結構示意圖。 第十一圖為根據第六A圖之基材實施壓力感測晶片封装 的結構示意圖。 第十二圖為根據第六B圖之基材實施晶片封裝以導點球 作為電性連結，晶背不外露型的結構示意圖。 、弟十二圖為根據第/、B圖之基材實施晶片封裝以導點球 作為電性連結，晶背外露型的結構示意圖。 ’According to the above, one of the features of the present invention is to provide a package substrate structure which is composed only of a metal plate and an insulating layer. The wafer can be directly placed on the pad in the surface adhesion technology, thereby shortening the electrical contact on the wafer to The distance between the pads to reduce the package size. The embodiments described above are merely illustrative of the technical idea and the features of the present invention, and are not intended to limit the implementation possibilities of the present invention. The purpose of describing the specific details is to enable the invention to be fully understood. The scope of the invention is defined by the scope of the invention. However, those skilled in the art know that this is not the only solution; and that the spirit of the player's creation or the revealed essential features, the above embodiments can be presented in other special forms, that is, according to the present invention. The secret of the equal change made by the spirit of the disclosure should still be covered by the patent of the present invention. [Simple Description of the Drawings] The first figure is a schematic view of the structure of a substrate packaged by a lead frame. The second figure is a schematic view of a substrate structure which is conventionally packaged in a multi-layer substrate. f is a schematic view of the structure of the chip package implemented by the first embodiment. Xi: A schematic diagram of the structure of a chip package implemented in the second figure. The outline of the plan, the second picture, the sixth picture A and the sixth picture B are schematic diagrams of the carrier only according to the present month. Figure 7A, Figure VII, and the implementation of the stipulations of the stipulations of the singularity of the singularity of the pedestal of the metal pedestal according to the present invention. The nine figures are based on the sixth A eve of the reference. Structure of the wafer encapsulation of the substrate of the A diagram is shown in FIG. 10 1281244. FIG. 10 is a schematic structural diagram of implementing a CMOS sensing wafer package according to the substrate of FIG. Figure 11 is a schematic view showing the structure of a pressure sensing wafer package according to the substrate of Figure 6A. Fig. 12 is a schematic view showing the structure of the wafer package according to the sixth drawing, in which the wafer is packaged with a lead ball as an electrical connection, and the crystal back is not exposed. The Twelfth figure is a schematic view showing the structure of the crystal-backed exposed type by performing chip bonding on the substrate according to the drawings of Figs. ’
第十四圖為根據第六B圖之基材實施晶片封裝以金 塊作為電性連結，晶背不外露型的結構示意圖。 ” 示意圖料五A、B圖為本發明之—實施例封裝基板架構的正面 【主要元件符號說明】 110 圖案化線路 in 金屬表面處理 210 圖案化線路 211 金屬表面處理 220 導電球 221 保護層 222 内層結構 330 金屬座 331 金屬表面處理 332 導線 333 黏著層 334 塑封材料 335 晶片 432 導線 11 1281244Fig. 14 is a schematic view showing the structure in which the wafer package is electrically connected according to the substrate of Fig. B, and the crystal back is not exposed. Illustrated material 5A, B is the front view of the package substrate structure of the present invention. [Main component symbol description] 110 patterned circuit in metal surface treatment 210 patterned circuit 211 metal surface treatment 220 conductive ball 221 protective layer 222 inner layer Structure 330 Metal Block 331 Metal Finishing 332 Wire 333 Adhesive Layer 334 Molding Material 335 Wafer 432 Wire 11 1281244
433 黏著層 434 塑封材料 435 晶片 50 金屬引腳墊 501 第一表面 502 第二表面 51 導電焊墊 52 絕緣層 71 金屬座 703 第三表面 72 表面金屬層 932 導電連接線 933 黏著層 934 塑封材料 935 晶片 1001 空穴 1002 黏著層 1003 上蓋基板 1101 膠體層 1220 導電球 1301 晶片背面 1401 導電凸塊 1501 晶片或晶片承載墊 12433 Adhesive layer 434 Molding material 435 Wafer 50 Metal pin pad 501 First surface 502 Second surface 51 Conductive pad 52 Insulation layer 71 Metal seat 703 Third surface 72 Surface metal layer 932 Conductive connection line 933 Adhesive layer 934 Plastic sealing material 935 Wafer 1001 Hole 1002 Adhesive Layer 1003 Upper Cover Substrate 1101 Colloidal Layer 1220 Conductive Ball 1301 Wafer Back 1401 Conductive Bump 1501 Wafer or Wafer Carrier Pad 12