twf.doc/g 1259471 16310 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種移位暫存器，且特別是有關於一 種了以降低電晶體數目之移位暫存器電路。 【先前技術】 ★曰請參關卜其繪示係f知技術巾，—種應用於低溫 複日日矽(Low Temperature Pl〇y Silicon，LTPS)技術並實現於 玻璃基板上的CMOS移位暫存n電路，此移位暫存器電路 2要是由多級的栓鎖電路1G1與邏輯電路1()3串接組合而 々、一其、^ 每—級栓鎖電路1G1需要六個電晶體構成，而 力邏輯私路1〇3則需要四個電晶體，因此當此移位暫 】二二路所串接的栓鎖電路1()1與邏輯電路1。 其所需要的佈局面積也更大。 了 設計路：需的佈局面積，因此不斷地有新的 電路，此移位暫存器電路同樣是串接多 移位暫存器單元只需二：部電:圖’而此 以進行工作。 私日日脰與一組反相器即可 XCK，第_源/没^曰肢2的間極端接收一反相時脈訊號 (N-l)OUT 〇 、而M〇S兩級移位暫存器單元的輸出端 訊號CK，第- 電晶體Q2的第一源/汲極端接收時脈 弟—源/沒端是此移位暫存器單元的輸出端 1259471 16310twf.doc/g =二輸出自身所必需輸出的輸出訊號。另外， ==)=端則是输下-級移位暫_ 導通ίΓ??1峨孤為高電壓準位時，電晶體Q1為 二；;位=一級的輸出訊號為罐準位，則此 下-級—i a輸出時脈訊號ck的準位至 -級心好暫存鮮70。此外，電晶體Q4可以藉由下 體Q4m^f的輸出訊號來決定導通與否，當電晶 位。此外1 士大恶下’輸出端(n)〇ut則會輸出低電壓準 i單=1的輸人端係触至前—級移位暫存 ;(N-1)0UT，當輸出導”⑽為低電壓 晶^二的輸出端會輸出高驢準位以導通電 =Q3，叹輸㈣_υτ可以保持在低電壓準位的狀 輸出妒mnm 其中，圖不中之0UT1〜〇UT3分別表示 ttlL Γ^ίΝ)ουτ 5 ^a(n+i)〇ut 〇 同(因為端點A 2，端點Α與輸出訊號〇UTl會幾乎相 庫），而杰η 士笔壓還必需考慮到電晶體Q1的做效 i ^ TfE XCK ^ t Q1 態，而^ W點A的電壓為浮接的高電壓準位狀 壓备持碎^Γ 授時脈訊號CK的訊號，端點A的電 曰持、，的增加’亦使得_υτ所輸出 1259471 l63l〇twf.doc/g έ持績推持在南電壓準位。 =上的敘述可知’此種設計方式的移位暫存哭你 、級移位暫存器單元可以將輸入訊號延遲-：ί 二’再將减傳送至下—級移位暫存器單元之中 至^號傳送的功能，而每—級移位暫存器單元只需 ίΓ::Φ器201需兩個電晶體組成)，雖然已經比圖1 ΐ •巧要串接多級移位暫存器單元時， •上以此種方式設計電路時，每一級移再力口 授下一級移位暫存器單元的輪出雜 才能夠正常的動作，這將增加電路佈局： 【發明内容】 本發明的目的就是在提供一種移位 ，暫存器電路_每-組移位暫存器單二移 | 夕的電晶體數量，執行相同的功能。 ’、J用更 本發明提出一種移位暫存器電路， ^串接多數組移位暫存器單元所組成，“每電路 收時脈訊號與反相時脈訊號 體、體、第，體、第三‘ 號心二接收輸人訊 第—源/汲極端接收時脈訊號，而其間極:‘ %曰曰 1259471 16310twf.doc/g 另外，第二電晶 體的弟二源/汲極端 ，…· ---❸日a肢叫示一挪、/攻極端 輸出-輪出訊號。上述之第三電晶體的第—源/汲極端 第一電晶體的第二源/没極端，而第三電晶體的第二源 極端，至JCC(電源端)。上述之反相器的輸入端耦接第 -電晶體㈣二源後極端’而其輸出端祕至 之閘極端。 电日日肢 依照本發明的較佳實施例所述，上述之移位暫存器带 路中更包括-電容，此電容的第—端 ^ 路中:較，所述，上述之移位暫存器電 J Ϊ—;:Γ紅電晶體，係可以是M〇s電晶體。 /、甲弟電日日體〜弟三電晶體可以是P型M〇s +曰 與N型M0S電晶體二者之一。 毛日日肽 —依照本發明的較佳實施例所述，上述之 j的第二電晶體若為漏電晶體時，上述早 ❿ 疋弟一電晶體中，閘源極之間的閘源極寄生電容Γ谷以 依照本發明的較佳實施例所述， = 路中的反相哭，4 、上通之移位暫存器電 述之第四電晶體：第與第五電晶體。其中，前 :…豆的弟二源/汲極端則輪：原弟 號。上述之第五電曰邮 、所棱及的輸出訊 的輪入訊號’而第五電晶體的第:源提及 本發明所採用的移位暫位器單元，其=妾=電晶 ^259471 l63l〇tWf.d〇c/g 二的縮減’因此整體電路的:局== 易懂他目的、特徵和優點能更明顯 明如下y文特編土貝施例，並配合所附圖式，作詳細說 【實施方式】 本發明所提出之移位暫存器電路， 器電:内的每-級移位暫存器單 位暫二移位暫存器電路在串接多級移 降低，;=面編數目會_ 計的複雜度。相對地細小’同時減低佈局設 哭示係依照本發明所提出之移位暫存 二一^中—級移位暫存器單元的内部電路圖。如圖 容C。 乐—兒日日脰405、反相态407,以及降壓電 _ J :=一電晶體401之第一源/沒極端接收—輸入訊 此私位暫存器單元_在移位暫存器電路中為 =-級時’此第-源/汲極端係接收由外部所輸人的資料訊 ^。*此第—電晶體401 *此移位暫存器電路中並非第 '及％•，此第一源/汲極端係接收由上一級移位暫存器單元 l6310twf.d〇c/g 所輪出的訊號。此外，第一電晶體401之閘極端接收一反 相時脈訊號XCK。 在本實施例中，第二電晶體403之第一源/汲極端接收 、日守脈訊號ck，閘極端耦接至第一電晶體4〇1的第二源/ =極端，而此第二電晶體4G3之第二源/祕端係輸出一輸 =訊號011丁。其中，f此移位暫存器單元_在移位暫存 裔電路中為最後一級時，此第二電晶體4〇3之第二源产及極 =所輸出的輸出訊號QUT即是此移位暫存器電路最後所 ，出的訊號’而當此移位暫存器單元在此移位暫存器 ϊίΐ並非最第一級時，此第二電晶體403之第二源/汲： ^所輪出之輸出訊號㈤Τ，則為下—級移位暫存器單元所 接收的輸入訊號。 另外’在此實施例中，第三電晶體4〇5之第一源/沒極 二電晶體403的第二源/汲極端，而第二源/沒極 $接至地。降壓電容C的第—端祕至第二電晶體他 ^-源/祕端，第二端_至第二電晶體彻的間極 401°^在電路中的反相器、4〇7，其輸入端減第一電晶體Twf.doc/g 1259471 16310 IX. Description of the Invention: [Technical Field] The present invention relates to a shift register, and more particularly to a shift register circuit for reducing the number of transistors . [Prior Art] ★Please refer to the description of the technology, which is applied to the low temperature Pl〇y Silicon (LTPS) technology and realize the CMOS shift on the glass substrate. In the n-circuit, the shift register circuit 2 is composed of a multi-stage latch circuit 1G1 and a logic circuit 1 () 3 connected in series, and one, each of the - level latch circuit 1G1 requires six transistors. The configuration, while the force logic private circuit 1〇3 requires four transistors, so when this shift is temporarily two or two lines of the latch circuit 1 () 1 and logic circuit 1. The layout area required is also larger. The design road: the required layout area, so there is a new circuit constantly, this shift register circuit is also a series of multiple shift register unit only two: part of the: Figure 'and work. Private day and day with a set of inverters can be XCK, the first source / no ^ limb 2 extreme receiving an inversion clock signal (Nl) OUT 〇, and M 〇 S two-stage shift register The output signal CK of the unit, the first source/汲 terminal of the first transistor Q2 receives the clock source-source/end is the output terminal of the shift register unit 1259471 16310twf.doc/g = two outputs themselves The output signal that must be output. In addition, the ==)= terminal is the input-level shift temporary _ conduction Γ Γ ? ? 峨 峨 峨 峨 峨 峨 峨 峨 峨 峨 峨 峨 峨 峨 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电This lower-level-ia output clock signal ck level to - level heart good temporary storage fresh 70. In addition, the transistor Q4 can be turned on or off by the output signal of the lower body Q4m^f, when it is electrically crystallized. In addition, the output of the low-voltage quasi-i-single=1 touches the front-stage shift temporary storage; (N-1)0UT, when the output is "" (10) For the output of the low-voltage crystal, the output of the high-voltage crystal will be output to the power-on = Q3, and the output of the sigh (4)_υτ can be maintained at the low-voltage level 妒mnm. Among them, 0UT1~〇UT3 respectively represent ttlL. Γ^ίΝ)ουτ 5 ^a(n+i)〇ut is the same (because the endpoint A 2, the endpoint Α and the output signal 〇UTl will be almost the same), and the pen pressure must also take into account the transistor The effect of Q1 is i ^ TfE XCK ^ t Q1 state, and the voltage of ^ W point A is the floating high voltage level of the voltage reserve, and the signal of the pulse signal CK is given, and the power of the terminal A is held, The increase of 'also makes _υτ output 1259451 l63l〇twf.doc/g έ performance is pushed at the south voltage level. = The above description shows that this type of design shifts the temporary memory crying, level shift The register unit can delay the input signal by -: ί 2' and then transfer the subtraction to the lower-level shift register unit to the ^ number transfer function, and each-level shift register unit only needs Γ ::Φ2 01 requires two transistors to form), although it is already more than the multi-level shift register unit in Figure 1. When designing the circuit in this way, each stage shifts the next level shift. The rotation of the register unit can be normally operated, which will increase the circuit layout: [Disclosure] The object of the present invention is to provide a shift, register circuit _ per-group shift register Move the number of transistors on the eve, perform the same function. ', J uses the invention to provide a shift register circuit, ^ serially connected to multiple array shift register units, "each circuit receives the pulse signal And the inversion clock signal body, body, body, body, and third 'heart two receive the input signal source-source/汲 terminal receive the clock signal, and the pole: '%曰曰1259471 16310twf.doc/g , the second transistor of the second transistor / 汲 extreme, ... · --- the next day a limb called a move, / attack extreme output - turn out the signal. The first source/deuterium terminal of the third transistor described above has a second source/no terminal of the first transistor, and a second source terminal of the third transistor, to the JCC (power supply terminal). The input end of the above-mentioned inverter is coupled to the -electrode (4) two-source post-end' and its output terminal is secreted to the gate terminal. According to a preferred embodiment of the present invention, the shift register has a -capacitor, and the first end of the capacitor is: Device J Ϊ—;: Γ red transistor, which can be M〇s transistor. /, A younger brother, the Japanese body, the younger crystal can be one of the P-type M〇s + 曰 and the N-type MOS transistor. Hair Day Peptide - According to a preferred embodiment of the present invention, if the second transistor of the above j is a leakage crystal, the gate source between the gate and the source is parasitic in the above-mentioned early transistor Capacitor valleys are described in accordance with a preferred embodiment of the present invention, = inverting in the path, 4, the fourth transistor in the upper shift register: the fifth and fourth transistors. Among them, the former: ... the brother of the second source / 汲 extreme wheel: the original brother. The fifth electric signal of the above-mentioned fifth e-mail, the edge of the output signal and the fifth source of the fifth transistor refer to the shift terminator unit used in the present invention, which = 妾 = electro-crystal ^ 259471 l63l〇tWf.d〇c/g The reduction of 'therefore the whole circuit: the bureau == easy to understand his purpose, characteristics and advantages can be more clearly as follows y Wen special edited the shell example, and with the drawing, DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment] The shift register circuit of the present invention is provided, and the per-stage shift register unit in the internal shift register circuit is reduced in series multi-step shift; = The number of facets will be _ the complexity of the meter. Relatively small 'while reducing the layout setting. The crying system is an internal circuit diagram of the shift temporary storage unit according to the present invention. Figure C. Le-child day and night 405, inverting state 407, and step-down power _ J : = a first source of a transistor 401 / no extreme reception - input this private bit register unit _ in the shift register When the circuit is =-level, 'this first-source/汲 extreme receives the data from the external input. *This first - transistor 401 * This shift register circuit is not the '% and %•, this first source / 汲 extreme is received by the previous stage shift register unit l6310twf.d 〇 c / g The signal. In addition, the gate terminal of the first transistor 401 receives an inverted phase pulse signal XCK. In this embodiment, the first source/汲 terminal of the second transistor 403 receives the day pulse signal ck, and the gate terminal is coupled to the second source /= terminal of the first transistor 4〇1, and the second The second source/secret of the transistor 4G3 outputs a signal = signal 011. Wherein, when the shift register unit _ is the last stage in the shift temporary circuit, the second source of the second transistor 4〇3 and the output signal QTT output is the shift The last signal of the bit register circuit is 'when the shift register unit is not the first stage when the shift register unit is not the first stage, the second source/汲 of the second transistor 403: ^ The output signal (5) that is rotated is the input signal received by the lower-level shift register unit. In addition, in this embodiment, the first source/no-pole transistor 403 of the third transistor 4〇5 has a second source/汲 terminal, and the second source/no-pole is connected to the ground. The first end of the step-down capacitor C is to the second transistor, the source/secret, the second end _ to the second transistor, the inter-electrode 401°, the inverter in the circuit, 4〇7, The input terminal is subtracted from the first transistor
勺弟—源/沒極端，輸出端耦接至第三電晶體405的閉 極端。 J 如11 5Α中所示，其綠示係依照本發明所提出之移位 曰存器電路中，其中—級移位暫存器單元中之反相器的電 圖如圖中所示，此反相器是由兩組電晶體，第四電曰 體训與第五電晶體如所组成，在本實施例中，第= 晶體501與第五電晶體5〇3係Ν型M〇s電晶體。％ 1259471 163l〇twf.doc/g 至電源％ Ξ Γ 及極端與間極端輕接 電:ί 40二 極端則是減至上述所說明的第： 电曰曰體405的閘極端。而第五電晶體5〇 = 耦接至第四雷曰雕ςηι > a 弟源//及極端 屯日日脰501之弟二源/汲極端，閘極端則是 說明之第-電晶體偏㈣/沒極:= 妾 二源/f峨接至地。當VX端的糊 亦然 守vy端的輸出訊號則為低電壓準位，反之 之如圖5B中所示，其繪示係依照本發明所提出 中，另一種移位暫存器單元㈣ 六带曰Lot所示，此反相器亦是由兩組電晶體，第 笛二體505與第七電晶體5〇7所組成，而在本實施例中， ％晶體巧與第七電晶體5。7係P型M〇s電晶體。 其中，第六電晶體5〇5之第一源/没極端祕至電源 一郎’、而閘極端輕接至上述所說明之第一電晶體401的第 -原Λ及極，第二源/沒極端則是輕接至上述所說明的第 == = =而第七，^ 弟，、屯日日體505之弟二源/汲極端，閘極端則是耦 #弟七電晶體5〇7之第二源/汲極端，而第七電晶體5〇7 之第二源/汲極端耦接至地。 同樣的，當VX端的訊號為高電壓準位時，νγ俨 輸出。fl遗則為低電壓準位，反之亦然。由於在本實施例中、， 此^相态407旨在提供一反相訊號，因此除了前述所說明 的電路外，亦可以使用其它任何型式所組成的反相器電路 11 ⑧ 1259471 I63l〇twf.d〇c/g 來取代。 第二！實施例中’上述所提及的第-電晶體·、 μ-电咖4G3，以及第三電晶體德，係p型m〇 月此^㈣存器單Μ的第二電晶體他為Mi Γ月的降壓電容C ’除了可以使用外加 、勺木〜(Lump)電谷外，也可以利用第二電晶體4〇 /原極寄生電容Cgd取代。 碼 〜請參照圖6,其繪示係舰本剌所提出之移位 中4級移位暫存器單元串接後的内部電路圖。如 二中所不’此圖中係繪示兩組移位暫存器、單元彻 的串接情形’而雖然此圖示中只繪示出兩存 :的串接方式’但本發明所提出之移位暫存器電^ $同類型電路的規格要求，依據如圖6中崎示的方式 串接更多級的移位暫存器單元。 =照圖7 ’其繪示係圖6中之移位暫存器單元働 喊的時脈變化圖，以下配合圖6中所緣示的 屯仃5兒明。如圖6中所示，此移位暫存器電路中，每 -級移位暫存器單元㈣接相同的時脈訊號ck與反相時 XCK ’其中，時脈訊號CK與反相時脈訊號 二：：反的時脈訊號’以下分為三個周期詳細說明訊號 的變化過程。 在周期A中，反相時脈訊號XCK為低電壓準位 (1^0、時脈訊號CK為高電壓準位(High)，而輸入訊號 轉恶為低電壓準位(Low)，由於第一電晶體4〇la為導通狀 1259471 1631 Otwf.doc/g 悲，輸入訊號INI的低電壓準位會由第一電晶體術的第 =/汲極端傳送至第二源/汲極端，因此第二私沒極端的 电壓VX1會被拉至一相對低電壓準位(L〇w+vth)，導致 j晶體403a也會為導通狀態，此時，時脈訊號CK的高 笔壓準位會由第二電晶體侧a的第一源/沒極端傳送至第 -源Λ及極端。而由於反相器術的輸入端電壓νχι是低 電壓準位，所以其輸出端_輕νγι會轉態為高電壓準 位三使得第三電晶體她的閘極端同樣是高電壓準位，因 此第三電晶體403a會為關閉的狀態，最後移位暫存 彻的輪出端oim所輸出的訊號會是一高電壓準位°。 在周期B巾，輸入訊號IN1回復到正常的高電 xH第—電晶體4G1 a之閘極端所純的反相時脈訊號 同時轉態，所以第—電晶體_係關閉的狀態： =弟-¾晶體403a由於在源-間極間另外触一降壓電 谷C，在此周期3中，第二電晶體4〇3a之第一 時脈訊號CK為低電壓準位，導致祕端的電^ 运再被拉低至更低的低電壓準位(L〇w+Vth-Av)，其 _ AV之值為時脈訊號CK之高低電壓差再乘上降屙+ 二;與相鄰各電晶體寄生電容之比例，此Λν之計算二二The scoop-source/no extreme, the output is coupled to the closed terminal of the third transistor 405. J, as shown in FIG. 1 ,, the green display is in the shift register circuit according to the present invention, wherein the electric diagram of the inverter in the level shift register unit is as shown in the figure, The inverter is composed of two sets of transistors, and the fourth electric body is composed of a fifth electromagnet and the fifth electromagnet. In this embodiment, the third crystal 501 and the fifth electromagnet 5〇3 are Ν-type M〇s electric. Crystal. % 1259471 163l〇twf.doc/g to power supply % Ξ Γ and extreme and light connection: 40 40 2 The extreme is reduced to the above described: the gate terminal of the electric body 405. And the fifth transistor 5〇=coupled to the fourth Thunder 曰 ςιι> a brother source // and the extreme 屯 脰 脰 脰 二 二 二 二 二 二 , , , , , , , , , , , , , , , , , , , , , , 闸 电 电 电 电 电 电(4) / No pole: = 妾 二源 / f峨 to the ground. When the VX terminal paste also keeps the vy terminal output signal, it is a low voltage level, otherwise, as shown in FIG. 5B, the drawing is in accordance with the present invention, another shift register unit (four) six-band 曰As shown by Lot, the inverter is also composed of two sets of transistors, a first dipole 505 and a seventh transistor 5〇7, and in the present embodiment, the % crystal is the same as the seventh transistor 5. 7 It is a P-type M〇s transistor. Wherein, the first source of the sixth transistor 5〇5 is not extremely secretive to the power supply Ichiro, and the gate is extremely lightly connected to the first and the first poles of the first transistor 401 described above, and the second source/none The extreme is lightly connected to the above-mentioned ==== and the seventh, ^ brother, the second day of the Japanese body 505 brothers two source / 汲 extreme, the gate is the coupling of the brother seven transistors 5 〇 7 The second source/汲 terminal is coupled to the second source/汲 terminal of the seventh transistor 5〇7 to ground. Similarly, when the signal at the VX terminal is at a high voltage level, νγ俨 is output. The fl is the low voltage level and vice versa. In this embodiment, the phase 407 is intended to provide an inverted signal, so that in addition to the circuit described above, any other type of inverter circuit 11 8 1259471 I63l〇twf can be used. Replace d〇c/g. second! In the embodiment, the above-mentioned first-electrode crystal, μ-electric coffee 4G3, and third crystal crystal are the second transistor of the p-type m 〇 ^ ^ 四 四 ^ ^ ^ ^ ^ ^ ^ 第二 第二 第二 第二The monthly step-down capacitor C' can be replaced by a second transistor 4〇/primary parasitic capacitance Cgd in addition to the externally applied, scoop-to-wood (Lump) electric valley. Code ~ Please refer to FIG. 6 , which shows an internal circuit diagram of the 4-stage shift register unit in the shift proposed by the ship. As shown in the second figure, the two sets of shift register and the united serial connection case are shown in the figure. Although only two pairs of: the serial connection mode are shown in the figure, the present invention proposes The shift register memory is the same as that of the circuit of the same type, and more stages of shift register units are connected in series according to the manner shown in FIG. = Fig. 7' shows the clock change diagram of the shift register unit in Fig. 6, which will be described below with reference to Fig. 6. As shown in FIG. 6, in the shift register circuit, each-stage shift register unit (4) is connected to the same clock signal ck and inverted XCK', wherein the clock signal CK and the inverted clock are Signal 2: The reverse clock signal 'The following is divided into three cycles to detail the change process of the signal. In cycle A, the inverted clock signal XCK is at a low voltage level (1^0, the clock signal CK is at a high voltage level (High), and the input signal is turned to a low voltage level (Low), due to A transistor 4〇la is conducting 1259471 1631 Otwf.doc/g sorrow, the low voltage level of the input signal INI is transmitted from the first =/汲 terminal of the first transistor to the second source/汲 terminal, thus the first The second extreme voltage VX1 will be pulled to a relatively low voltage level (L〇w+vth), causing the j crystal 403a to be in a conducting state. At this time, the high pen pressure level of the clock signal CK will be The first source/no terminal of the second transistor side a is transmitted to the first source and the terminal, and since the input voltage νχι of the inverter is a low voltage level, the output terminal _light νγι is converted to The high voltage level three makes the third transistor of the third transistor also have a high voltage level, so the third transistor 403a will be in a closed state, and finally the signal outputted by the temporary shifting terminal oim will be A high voltage level °. In the period B towel, the input signal IN1 returns to the normal high voltage xH - transistor 4G1 a gate extreme pure The inverting clock signal is simultaneously rotated, so the state of the first-transistor_ is turned off: = the younger -3⁄4 crystal 403a is additionally touched by a step-down electric valley C between the source and the interpole, in this period 3, the second The first clock signal CK of the transistor 4〇3a is at a low voltage level, causing the secret terminal to be pulled down to a lower low voltage level (L〇w+Vth-Av), which is _AV The value is the high and low voltage difference of the clock signal CK and multiplied by the falling 屙 + two; the ratio of the parasitic capacitance of the adjacent transistors, the calculation of the Λ ν
AV {High - Low)AV {High - Low)
上式中之C eq 等效電容（包括降壓電容c) 係指從端點電壓VX向右端所看出去之所有 ⑧ 13 1259471 163I0twf.d〇c/g 此日t的第二電晶體她之閘極端仍為低電鮮位，這 戶^^周期6中，第二電晶體她仍維持在導通狀態， 一才唬CK的低電壓準位會由第二電晶體40如的第 極〜傳送至第二源/汲極端，因此在此周期·B間， = 存态單兀4〇〇的輸出端係輸出低電壓準位至下一級 曰存器單元600中。 、 ΜηΛ前所述’由於在此實施例中，第二電晶體4〇3a係-电晶體’所以上述所提及的降壓電容c， 源極寄生電容Cgd。一般而言，電晶體在導 =關_狀態下’其_極寄生電容Cgd的電容值也會 『同’而在周期B中’由於第二電晶體恰為導 所以如的容值較大，可以將第二電晶體403a = Ϊϋ，νΧ1拉低至更低的電壓，以使第二電晶體可 在導通狀態。因此，當使用本發明所提出之移 曰子為電路時’若電路中的電晶體為MOS電晶體時， 電c晶體:二_寄生電容Cgd的特性 4A 免除而要再另行設計外加電容的困 摱。 ra么：3:期c中’時脈訊號CK與反相時脈訊號XCK 3為穴，的周期變化，所以在周期c的狀態與周期A相 輸入訊號1N1已經是高電壓準位，所以輸人 榀二二源/汲極端，也使得第二電晶體403a的閘 。而5讀態成高電壓準位，形成關閉的狀態。此外，此 1259471 1631〇twf.d〇c/g 時反相器、4 Ο 7的輸出端電壓v γ!為低電壓準位 電料通狀態，而移位暫存器單元的輸出端咖 則會輸出準位至下—級移位暫存器單元_中。 ^^的4明巾可以得知，輪人訊號ΙΝ1❺低電壓準 位會延遲-個職時間，才由移位暫存 ^outu專送至移位暫存器單元6〇〇之中，而移 早兀6⑻的内部電路結構與前述的移位 =第唯於第厂電晶體_係二 的訊號變化過程亦與移位暫存器_相同，在二 :述。而移位暫存器單元_ 】 與^的變化情形亦如同圖7中所示，而 :‘：會延遲—個周期時間，才輪出低電壓準位的訊號 二。以上的說明可知，此移位暫存器電路即是婉由内」: 母-級移位暫存器單元，來達 、、、工由内』 位暫存器電路亦可以的傳遞，而此移 位暫存哭單元了：依據不冋的需求，串接不同數目的移 =了早 以達到不同的效能。 移位ί存器、，電晶體所組成的 的每-級移者，移位暫存器電路中 設計。 9存$早凡亦可以由電晶體進行 界電Itl9，其繪示係利用本發明所提出之移位斬亡 ―’串接多級移位暫存器單元而成之訊號=The C eq equivalent capacitance (including the buck capacitor c) in the above equation refers to all the 8 13 1259471 163I0twf.d〇c/g seen from the end voltage VX to the right end. The gate terminal is still low-powered. In this case, the second transistor is still in the on state, and the low voltage level of the CK is transmitted from the second transistor of the second transistor 40. Up to the second source/汲 terminal, therefore, during this period·B, the output of the = state unit 4〇〇 outputs a low voltage level to the next stage buffer unit 600. ΜηΛ previously described 'because in this embodiment, the second transistor 4〇3a is a transistor', so the above-mentioned step-down capacitor c, the source parasitic capacitance Cgd. In general, the capacitance value of the _ pole parasitic capacitance Cgd of the transistor in the conduction state is "same" and in the period B, because the capacitance value of the second transistor is just as large, The second transistor 403a = Ϊϋ, ν Χ 1 can be pulled down to a lower voltage so that the second transistor can be in an on state. Therefore, when the mobile device proposed by the present invention is used as a circuit, if the transistor in the circuit is a MOS transistor, the characteristic 4A of the electric c crystal: the second parasitic capacitance Cgd is eliminated and the external capacitor is additionally designed. Hey. Ra?: 3: period c 'clock signal CK and inverted clock signal XCK 3 for the hole, the period changes, so the state of the period c and the period A phase input signal 1N1 is already a high voltage level, so lose The 榀22 source/汲 extreme also causes the gate of the second transistor 403a. The 5 read states are at a high voltage level, forming a closed state. In addition, when the 1259471 1631〇twf.d〇c/g inverter, the output voltage v γ! of the 4 Ο 7 is the low voltage level electric material pass state, and the output of the shift register unit is The output will be leveled to the lower-level shift register unit_. ^^ 4 towel can know that the wheel signal ΙΝ1❺ low voltage level will be delayed - the full time, only the shift temporary storage ^outu is sent to the shift register unit 6〇〇, and shift The internal circuit structure of the early 6 (8) and the above-mentioned shift = the signal change process of the first transistor _ system 2 is also the same as the shift register _, in the second:. The change of the shift register unit _ 】 and ^ is also as shown in Figure 7, and : ‘: will delay – cycle time, only the low voltage level signal is turned on. As can be seen from the above description, the shift register circuit is the internal: the mother-stage shift register unit, and the bit buffer circuit can also be transferred. Shifting the temporary crying unit: According to the unsatisfactory demand, serially connecting different numbers of shifts = early to achieve different performance. The shift register, the per-level shifter composed of the transistor, is designed in the shift register circuit. 9 deposits can also be carried out by the transistor. It is shown by the transistor.
15 1259471 I63l0twf.d〇c/〇 = ί所：’在此移位暫存器電路中，相鄰兩組 之用Γ任何型式之平面顯示器__別 於H掃描驅動器），藉以產生晝素電路寫入訊 ί取樣訊號於垂直驅動器（資_動器)藉以產生資 (反相器需 厅而的包日日肢數目，只需5個電晶體 當移位暫存哭電二 =比習知技術中的電路更少，因此 整體内部的電晶俨數2接多級的移位暫存器單元時，其 位暫存器可以大幅的縮減，再加上每-級移 號，因此整二二授下一級移位暫存器的輪出訊 雖然亦可以相對地縮小更多。 限定本發日^ 麵如上，财並非用以 和範圍内，當可作此者’在不脫離本發明之精神 【圖式簡ΐ二趣圍所界定者為準。 器的内圖：:習知技術中，-種 部電=纷示為習知技術中，另一種移位暫存器電路的内 圖增示為圖2中之移位暫存器電路内之訊號的工作 ⑧ 16 r f.doc/g r f.doc/g 時脈圖。 圖4繪示係依照本發明所提出之移位 + 其中一級移位〜暫存器單摘内部電路圖。日存以路中 圖5 A、％不係依昭太旅g 其卜級移位^存器單元的内部電路圖。Μ路中， 圖5A繪示係依照本發明所提出之 中，其中一級移位暫存器單元中之 夕暫存器電路 徑杪证皙存器單元中之反 ㈡丨丁益黾ί 圖6繪示係依照本發明所提出之;I:，： 串接兩級移位暫存器單元的内部電路圖。曰存态电路中， 圖7繪示係圖6中之移位暫存器^ mi。 甙琥的時脈變 圖5B繪所示係依照本發明所=内部電路圖。 中，另一種移位暫存器單元中之反相存器電路 繪示係依照本發明所提圖。 。 〜吋脈變 由N 圖0 18繪示係依照本發明所提出 型MOS電晶體所 ^位暫存器電路中， 成之私位暫存器單元的内部電辟 圖情示係利用本發明所提出之移 串接多級純暫存科元所組成之訊 中， 【主要兀件符號說明】 ）u生态的電路圖。 101 :栓鎖電路 103 :邏輯電路 201 、 407 : 400 、 600 : 401〜405 、 501 、 503 : 505 、 507 : 反相器 移位暫存器單元15 1259471 I63l0twf.d〇c/〇= 所: 'In this shift register circuit, two adjacent sets of flat-panel displays __ other than H-scan drivers), in order to generate a pixel circuit Write the signal, the sampling signal is generated by the vertical driver (the carrier), and the number of the day and the limbs of the inverter is required. Only 5 transistors are needed when the shift is temporarily stored. There are fewer circuits in the technology, so when the overall internal number of transistors is 2 to multi-stage shift register unit, the bit register can be greatly reduced, plus the shift per number, so the whole two The second round of the shift register can be relatively narrower. Although it is limited to the above date, the money is not used and scope, and can be used as it does not deviate from the present invention. The spirit of the figure is defined by the definition of the genre. The internal diagram of the device: in the conventional technology, the type of electricity = the traditional figure in the conventional technology, another internal map of the shift register circuit The operation is shown as the signal in the shift register circuit in Figure 2 8 16 r f.doc/gr f.doc/g clock map. Figure 4 shows the system According to the shifting proposed by the present invention, the internal circuit diagram of the first-order shifting-storage register is extracted. The daily memory is in the middle of the road. Figure 5 A, the % is not the same as the Zhao Zhaotai brigade In the circuit diagram, FIG. 5A is a diagram of the present invention, wherein the first stage shift register unit is in the temporary register circuit path and the counter is in the buffer unit (2) 丨丁益黾ί 6 is a schematic diagram of an internal circuit diagram of a series of two-stage shift register unit in accordance with the present invention. In the buffer state circuit, FIG. 7 illustrates the shift register in FIG. ^ mi. The clock change of Fig. 5B is shown in Fig. 5B. The internal circuit diagram according to the present invention. The reverse register circuit in another shift register unit is shown in accordance with the present invention.吋 变 由 由 N 图 图 图 图 图 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 MOS In the message composed of the series of multi-level pure temporary storage units, the [main element symbol description] u ecological circuit diagram. 101: latch circuit 103: logic circuit 201, 407: 400, 600: 401~405, 501, 503: 505, 507: inverter shift register unit
501、5〇3、Q1 〜Q4 : N型M0S電晶體 P型M0S電晶體 I259471_〇c/g A、VX、VY :端點電壓 C :電容 CK :時脈訊號 IN :輸入訊號501, 5〇3, Q1~Q4: N type M0S transistor P type M0S transistor I259471_〇c/g A, VX, VY: terminal voltage C: capacitance CK: clock signal IN: input signal
Vdd、Vcc ·電源端 0UT1〜0UT4 :輸出訊號 XCK :反相時脈訊號 OUT、 （N-l)OUT、（N)OUT、（N+1)〇UT :輸出端Vdd, Vcc · Power supply terminal 0UT1~0UT4 : Output signal XCK : Inverted clock signal OUT, (N-l)OUT, (N)OUT, (N+1)〇UT: Output
18 ⑧18 8