CN110689839B

CN110689839B - Shifting register unit, driving method, grid driving circuit and display device

Info

Publication number: CN110689839B
Application number: CN201911256425.8A
Authority: CN
Inventors: 李新国; 郝学光; 王漪
Original assignee: SCHOOL OF SOFTWARE AND MICROELECTRONICS PEKING UNIVERSITY; BOE Technology Group Co Ltd
Current assignee: SCHOOL OF SOFTWARE AND MICROELECTRONICS PEKING UNIVERSITY; BOE Technology Group Co Ltd
Priority date: 2019-12-10
Filing date: 2019-12-10
Publication date: 2020-04-17
Anticipated expiration: 2039-12-10
Also published as: CN110689839A

Abstract

The invention provides a shift register unit, a driving method, a grid driving circuit and a display device, and relates to the technical field of display. The shift register unit comprises a shift register module and an output module, wherein the shift register module is used for performing shift register on an input signal under the control of a reset signal and a first clock signal so as to generate a carry output signal; the voltage signal of the shift output node is opposite to the carry output signal; the output module is used for generating a grid driving signal according to the output control signal and the second clock signal; the output control signal is the carry output signal or the voltage signal of the shift output node. The shift register unit, the driving method, the grid driving circuit and the display device have stable characteristics. The display device may be an organic light emitting diode display device, a liquid crystal display device, or a polymer light emitting device display device.

Description

Shifting register unit, driving method, grid driving circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a shift register unit, a driving method, a grid driving circuit and a display device.

Background

At present, most of the middle and high-end mobile phones of many mobile phone manufacturers at home and abroad adopt LTPS (Low Temperature polysilicon) display screens, and in order to save the cost of the display screens, the adopted gate driving circuits are generally N-type gate driving circuits. The N-type gate driving circuit refers to a gate driving circuit which purely comprises N-type transistors.

However, in the OLED (organic Light-Emitting Diode) Display field, the LCD (Liquid Crystal Display) Display field, and the PLED (Polymer Light Emitting device) Display field, as the requirements of customers on Display quality and reliability are higher and higher, most mobile phone manufacturers gradually increase reliability test conditions (such as HTO (High Temperature Operation), LTO (Low Temperature Operation), thermal shock, etc.), and the simple N-type gate driving circuit is easy to generate the drift of the threshold voltage of the transistor under these harsh test conditions, which causes the output characteristic of the gate driving circuit to be unstable or invalid, and seriously affects the Display quality of the product and the user experience.

Disclosure of Invention

The invention mainly aims to provide a shift register unit, a driving method, a gate driving circuit and a display device, and solves the problem that the gate driving circuit in the conventional display device is easy to drift the threshold voltage of a transistor, so that the output characteristic of the gate driving circuit is unstable or invalid, and the display is influenced.

In order to achieve the above object, the present invention provides a shift register unit, comprising a shift register module and an output module, wherein,

the shift register module is respectively electrically connected with an input signal end, a shift output node, a carry output signal end, a reset end and a first clock signal end, and is used for performing shift register on an input signal provided by the input signal end under the control of a reset signal input by the reset end and a first clock signal input by the first clock signal end so as to generate a carry output signal; the voltage signal of the shift output node is opposite to the carry output signal;

the output module is used for generating a gate driving signal according to the output control signal and a second clock signal input by a second clock signal end;

the output control signal is the carry output signal or the voltage signal of the shift output node.

In implementation, the shift register module comprises a first node control circuit, a shift output node control circuit and a carry output circuit, wherein,

the first node control circuit is used for inverting the first clock signal and outputting the inverted first clock signal to a first node;

the shift output node control circuit is used for controlling the voltage signal of the shift output node under the control of the input signal, the voltage signal of the first node, the first clock signal, the reset signal and the carry output signal;

the carry output circuit is used for inverting the voltage signal of the shift output node to obtain the carry output signal.

In practice, the first node control circuit includes a first inverter;

the input end of the first phase inverter is electrically connected with the first clock signal end, and the output end of the first phase inverter is electrically connected with the first node.

In practice, the shift output node control circuit includes a first tri-state gate, a second tri-state gate, and a reset sub-circuit, wherein,

a first control end of the first tri-state gate is electrically connected with the first clock signal end, a second control end of the first tri-state gate is electrically connected with the input signal end, a third control end of the first tri-state gate is electrically connected with the first node, and an output end of the first tri-state gate is electrically connected with the shift output node;

a first control end of the second tri-state gate is electrically connected with the first node, a second control end of the second tri-state gate is electrically connected with the carry output signal end, a third control end of the second tri-state gate is electrically connected with the first clock signal end, and an output end of the second tri-state gate is electrically connected with the shift output node;

the control end of the reset sub-circuit is electrically connected with the reset end, the first end of the reset sub-circuit is electrically connected with the shift output node, the second end of the reset sub-circuit is electrically connected with the first voltage end, and the reset sub-circuit is used for controlling the shift output node to be communicated with the first voltage end under the control of the reset signal.

In practice, the first tri-state gate includes a first transistor, a second transistor, a third transistor, and a fourth transistor;

the control electrode of the first transistor is electrically connected with the first control end of the first tri-state gate, and the first electrode of the first transistor is electrically connected with the second voltage end;

the control electrode of the second transistor is electrically connected with the second control end of the first tri-state gate, the first electrode of the second transistor is electrically connected with the second electrode of the first transistor, and the second electrode of the second transistor is electrically connected with the output end of the first tri-state gate;

the control electrode of the third transistor is electrically connected with the second control end of the first tri-state gate, and the first electrode of the third transistor is electrically connected with the output end of the first tri-state gate;

a control electrode of the fourth transistor is electrically connected with a third control end of the first tri-state gate, a first electrode of the fourth transistor is electrically connected with a second electrode of the third transistor, and a second electrode of the fourth transistor is electrically connected with a first voltage end;

the first transistor and the second transistor are n-type transistors, and the third transistor and the fourth transistor are p-type transistors.

In practice, the second tri-state gate includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

a control electrode of the fifth transistor is electrically connected with a first control end of the second tri-state gate, and a first electrode of the fifth transistor is electrically connected with a second voltage end;

a control electrode of the sixth transistor is electrically connected with the second control end of the second tri-state gate, a first electrode of the sixth transistor is electrically connected with a second electrode of the fifth transistor, and the second electrode of the sixth transistor is electrically connected with the output end of the second tri-state gate;

a control electrode of the seventh transistor is electrically connected with a second control end of the second tri-state gate, and a first electrode of the seventh transistor is electrically connected with an output end of the second tri-state gate;

a control electrode of the eighth transistor is electrically connected to the third control terminal of the second tri-state gate, a first electrode of the eighth transistor is electrically connected to the second electrode of the seventh transistor, and a second electrode of the eighth transistor is electrically connected to the first voltage terminal;

the fifth transistor and the sixth transistor are n-type transistors, and the seventh transistor and the eighth transistor are p-type transistors.

In practice, the reset sub-circuit includes a reset transistor;

the control electrode of the reset transistor is electrically connected with the reset end, the first electrode of the reset transistor is electrically connected with the shift output node, and the second electrode of the reset transistor is electrically connected with the first voltage end.

In implementation, the carry output circuit includes a second inverter;

the input end of the second phase inverter is electrically connected with the shift output node, and the output end of the second phase inverter is electrically connected with the carry output signal end.

In implementation, the output control signal is the carry output signal; the output module comprises a NAND gate and a third inverter;

the first input end of the NAND gate is electrically connected with the carry output signal end, and the second input end of the NAND gate is electrically connected with the second clock signal end;

the input end of the third inverter is electrically connected with the output end of the NAND gate, and the output end of the third inverter is electrically connected with the gate drive signal output end.

In practice, the output control signal is a voltage signal of the shift output node; the output module comprises a NOR gate;

the first input end of the NOR gate is electrically connected with the shift output node, the second input end of the NOR gate is electrically connected with the second clock signal end, and the output end of the NOR gate is electrically connected with the gate drive signal output end.

In implementation, the shift register unit of the invention further comprises an input control module;

the input control module is respectively electrically connected with the forward scanning control end, the reverse scanning control end, the adjacent previous-stage carry output signal end, the adjacent next-stage carry output signal end and the input signal end and is used for controlling the input signal end to be communicated with the adjacent previous-stage carry output signal end or the adjacent next-stage carry output signal end under the control of the forward scanning control signal and the reverse scanning control signal;

the forward scanning control terminal is used for providing the forward scanning control signal, and the reverse scanning control terminal is used for providing the reverse scanning control signal.

In implementation, the input control module comprises a first transmission gate and a second transmission gate;

the forward phase control end of the first transmission gate is electrically connected with the forward scanning control end, the reverse phase control end of the first transmission gate is electrically connected with the reverse scanning control end, the input end of the first transmission gate is electrically connected with the adjacent upper-stage carry output signal end, and the output end of the first transmission gate is electrically connected with the input signal end;

the positive phase control end of the second transmission gate is electrically connected with the reverse scanning control end, the negative phase control end of the second transmission gate is electrically connected with the positive scanning control end, the input end of the second transmission gate is electrically connected with the adjacent next-stage carry output signal end, and the output end of the second transmission gate is electrically connected with the input signal end.

In implementation, the shift register unit of the invention further comprises an output control module;

the output control module is used for controlling the grid driving signal output end to output a first voltage under the control of an enable signal input by an enable end.

In implementation, when the output module comprises a nand gate and a third inverter, the output control module comprises a pull-down circuit and a control circuit;

the pull-down circuit is used for controlling the input end of the third inverter to be communicated with the second voltage end under the control of the enable signal;

the control circuit is used for controlling the NAND gate not to output a first voltage signal under the control of the enable signal.

In practice, the pull-down circuit includes a pull-down transistor;

the control electrode of the pull-down transistor is electrically connected with the enabling end, the first electrode of the pull-down transistor is electrically connected with the second voltage end, and the second electrode of the pull-down transistor is electrically connected with the input end of the third phase inverter.

In practice, the nand gate includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein,

a control electrode of the ninth transistor is electrically connected with a first input end of the NAND gate, and a first electrode of the ninth transistor is electrically connected with the second voltage end;

a control electrode of the tenth transistor is electrically connected to the second input terminal of the nand gate, a first electrode of the tenth transistor is electrically connected to the second electrode of the ninth transistor, and the second electrode of the tenth transistor is electrically connected to the output terminal of the nand gate;

a control electrode of the eleventh transistor is electrically connected with a first input end of the nand gate, a first electrode of the eleventh transistor is electrically connected with an output end of the nand gate, and a second electrode of the eleventh transistor is electrically connected with a first end of the control circuit;

a control electrode of the twelfth transistor is electrically connected with the second input end of the nand gate, a first electrode of the twelfth transistor is electrically connected with the output end of the nand gate, and a second electrode of the twelfth transistor is electrically connected with the first end of the control circuit;

the control end of the control circuit is electrically connected with the enable end, the second end of the control circuit is electrically connected with the first voltage end, and the control circuit is used for disconnecting the first end of the control circuit from the first voltage end under the control of the enable signal;

the ninth transistor and the tenth transistor are n-type transistors, and the eleventh transistor and the twelfth transistor are p-type transistors.

In practice, when the output module comprises a nor gate, the output control module comprises a pull-up circuit and a control circuit;

the pull-up circuit is used for controlling the connection between the grid driving signal output end and the first voltage end under the control of the enabling signal;

the control circuit is used for controlling the NOR gate not to output a second voltage signal under the control of the enable signal.

In practice, the pull-up circuit includes a pull-up transistor;

the control electrode of the pull-up transistor is electrically connected with the enabling end, the first electrode of the pull-up transistor is electrically connected with the first voltage end, and the second electrode of the pull-up transistor is electrically connected with the grid driving signal output end.

In practice, the nor gate includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

a control electrode of the thirteenth transistor is electrically connected with the second input end of the NOR gate, and a first electrode of the thirteenth transistor is electrically connected with the first voltage end;

a control electrode of the fourteenth transistor is electrically connected with the first input end of the nor gate, a first electrode of the fourteenth transistor is electrically connected with the second electrode of the thirteenth transistor, and a second electrode of the fourteenth transistor is electrically connected with the output end of the nor gate;

a control electrode of the fifteenth transistor is electrically connected with the second input end of the NOR gate, a first electrode of the fifteenth transistor is electrically connected with the output end of the NOR gate, and a second electrode of the fifteenth transistor is electrically connected with the first end of the control circuit;

a control electrode of the sixteenth transistor is electrically connected with a first input end of the nor gate, a first electrode of the sixteenth transistor is electrically connected with an output end of the nor gate, and a second electrode of the sixteenth transistor is electrically connected with a first end of the control circuit;

the control end of the control circuit is electrically connected with the enable end, the second end of the control circuit is electrically connected with the second voltage end, and the control circuit is used for disconnecting the first end of the control circuit from the second voltage end under the control of the enable signal;

the thirteenth transistor and the fourteenth transistor are p-type transistors, and the fifteenth transistor and the sixteenth transistor are n-type transistors.

The invention also provides a driving method, which is applied to the shift register unit and comprises the following steps:

the shift register module is used for performing shift register on an input signal under the control of a reset signal and a first clock signal so as to generate a carry output signal and controlling a voltage signal of a shift output node to be in reverse phase with the carry output signal;

the output module generates a gate driving signal according to the output control signal and the second clock signal;

In implementation, the shift register module comprises a first node control circuit, a shift output node control circuit and a carry output circuit, and the driving time comprises a reset stage and a display stage which are sequentially arranged;

the shift register module performs shift register on an input signal under the control of a reset signal and a first clock signal to generate a carry output signal, and controls the voltage signal of a shift output node to be in phase inversion with the carry output signal, wherein the shift register module comprises the following steps:

in a reset stage, the shift output node control circuit controls the shift output node to be communicated with a first voltage end under the control of the reset signal so as to reset the potential of the shift output node to a first voltage;

in a display stage, the first node control circuit inverts the first clock signal and outputs the inverted first clock signal to a first node; the shift output node control circuit controls the voltage signal of the shift output node under the control of the input signal, the voltage signal of the first node, the reset signal, the first clock signal and the carry output signal; and the carry output circuit inverts the voltage signal of the shift output node to obtain the carry output signal.

In implementation, the output control signal is a carry output signal; the output module comprises a NAND gate and a third inverter; the first input end of the NAND gate is electrically connected with the carry output signal end, and the second input end of the NAND gate is electrically connected with the second clock signal end; the input end of the third inverter is electrically connected with the output end of the NAND gate, and the output end of the third inverter is electrically connected with the gate drive signal output end;

the step of generating the gate driving signal by the output module according to the output control signal and the second clock signal comprises: in the display phase, the display device is,

the NAND gate controls a signal output to the input end of the third inverter according to the carry output signal and the second clock signal;

and the third inverter inverts the signal to obtain the gate drive signal.

In practice, the output control signal is a voltage signal of the shift output node; the output module comprises a NOR gate; a first input end of the NOR gate is electrically connected with the shift output node, a second input end of the NOR gate is electrically connected with a second clock signal end, and an output end of the NOR gate is electrically connected with the gate drive signal output end;

the step of generating the gate driving signal by the output module according to the output control signal and the second clock signal comprises: and in a display stage, the NOR gate generates a gate drive signal according to the voltage signal of the shift output node and a second clock signal.

In implementation, the shift register unit further comprises an output control module; the driving method further includes:

in the discharging stage, under the control of an enable signal input by an enable end, the output control module controls the gate driving signal output end to output a first voltage.

In implementation, the output module comprises a nand gate and a third inverter, and the output control module comprises a pull-down circuit and a control circuit;

in the discharging stage, the step of controlling the gate driving signal output end to output the first voltage by the output control module under the control of the enable signal input by the enable end comprises:

in the discharging stage, the control circuit controls the nand gate not to output the first voltage signal under the control of the enable signal, and the pull-down circuit is used for controlling the input end and the second voltage end of the third inverter to be communicated under the control of the enable signal, so that the gate driving signal output end outputs the first voltage.

In implementation, the output module comprises a nor gate, and the output control module comprises a pull-up circuit and a control circuit; in the discharging stage, the step of controlling the gate driving signal output end to output the first voltage by the output control module under the control of the enable signal input by the enable end comprises:

in the discharging stage, the control circuit controls the nor gate not to output a second voltage signal under the control of the enable signal, and the pull-up circuit controls the connection between the gate driving signal output end and a first voltage end under the control of the enable signal, so that the gate driving signal output end outputs a first voltage.

In implementation, the shift register unit further comprises an input control module; the driving method further includes:

the input control module controls the input signal end to be communicated with the adjacent previous stage carry output signal end or the adjacent next stage carry output signal end under the control of the forward scanning control signal and the reverse scanning control signal.

The invention also provides a grid driving circuit which comprises the multistage shift register unit.

The invention also provides a display device which comprises the grid drive circuit.

In implementation, the display device comprises two gate driving circuits; the display device further comprises N rows of pixel circuits; n is a positive integer;

the first grid driving circuit is used for providing corresponding grid driving signals for the pixel circuits in the odd rows of the pixel circuits in the N rows;

and the second gate drive circuit is used for providing corresponding gate drive signals for even-numbered pixel circuits in the N rows of pixel circuits.

In practice, the display device of the present invention further comprises a display substrate; the N rows of pixel circuits are arranged on the display substrate;

the first grid driving circuit is arranged on the left side of the display substrate, and the second grid driving circuit is arranged on the right side of the display substrate; or the first gate driving circuit is arranged on the right side of the display substrate, and the second gate driving circuit is arranged on the left side of the display substrate.

In implementation, the display device comprises two gate driving circuits; the display device further comprises a display substrate and N rows of pixel circuits arranged on the display substrate; n is a positive integer;

the first grid driving circuit is used for providing corresponding grid driving signals for the N rows of pixel circuits;

the second grid driving circuit is used for providing corresponding grid driving signals for the N rows of pixel circuits;

the first gate driving circuit is arranged on the left side of the display substrate, and the second gate driving circuit is arranged on the right side of the display substrate.

Compared with the prior art, the shift register unit, the driving method, the grid driving circuit and the display device shift and register the input signal under the control of the reset signal and the first clock signal to generate a carry output signal, and control the voltage signal of the shift output node to be in reverse phase with the carry output signal; the output module generates a gate driving signal according to the output control signal and the second clock signal. The shift register unit in the embodiment of the present invention can conveniently and rapidly generate a gate driving signal, and the shift register unit in the embodiment of the present invention employs a CMOS (Complementary Metal Oxide Semiconductor) gate circuit, so that the characteristics are stable, and under a severe reliability test condition such as high temperature and high humidity, due to the complementarity of the characteristics of the N-type transistor and the P-type transistor, the shift register unit can effectively prevent the threshold voltages of the N-type transistor and the P-type transistor from drifting, and cannot cause false on or false off of the transistors, and failure of the shift register unit, so that a gate line in a display device can be correctly opened, a display effect is not affected, and display abnormality is not caused.

Drawings

FIG. 1 is a block diagram of a shift register unit according to an embodiment of the present invention;

FIG. 2 is a block diagram of a shift register unit according to another embodiment of the present invention;

FIG. 3 is a block diagram of a shift register unit according to yet another embodiment of the present invention;

FIG. 4 is a block diagram of a shift register unit according to another embodiment of the present invention;

fig. 5 is a circuit configuration diagram of the first TRI-state gate TRI1 in fig. 4;

FIG. 6 is a circuit configuration diagram of the second TRI-state gate TRI2 of FIG. 4;

FIG. 7 is a block diagram of a shift register unit according to another embodiment of the present invention;

FIG. 8 is a block diagram of a shift register unit according to yet another embodiment of the present invention;

FIG. 9 is a block diagram of a shift register unit according to yet another embodiment of the present invention;

FIG. 10 is a block diagram of a shift register unit according to yet another embodiment of the present invention;

FIG. 11 is a block diagram of a shift register unit according to yet another embodiment of the present invention;

FIG. 12 is a diagram illustrating the connection between an embodiment of the NAND gate of the shift register unit shown in FIG. 11 and the control circuit according to the present invention;

FIG. 13 is a block diagram of a shift register unit according to yet another embodiment of the present invention;

FIG. 14 is a diagram illustrating the connection between an embodiment of a NOR gate in the shift register unit shown in FIG. 13 and a control circuit according to the present invention;

FIG. 15 is a circuit diagram of a first embodiment of a shift register cell according to the present invention;

FIG. 16 is a timing diagram illustrating the operation of the shift register unit according to the first embodiment of the present invention;

FIG. 17 is a circuit diagram of a second embodiment of a shift register cell according to the present invention;

FIG. 18 is a timing diagram illustrating the operation of a second embodiment of the shift register unit according to the present invention;

fig. 19 is a structural diagram of a gate driving circuit according to an embodiment of the present invention;

FIG. 20 is a circuit diagram of a first embodiment of a display device according to the present invention;

fig. 21 is a circuit diagram of a second embodiment of the display device according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.

In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

The shift register unit according to the embodiment of the present invention includes a shift register module and an output module, wherein,

The shift register unit according to the embodiment of the present invention shifts and registers an input signal to generate a carry output signal and controls a voltage signal of a shift output node to be in phase opposition to the carry output signal through the shift register module under the control of a reset signal and a first clock signal; the output module generates a gate driving signal according to the output control signal and the second clock signal. The shift register unit according to the embodiment of the present invention can conveniently and rapidly generate a gate driving signal, and the shift register unit according to the embodiment of the present invention employs a CMOS (Complementary Metal oxide semiconductor) gate circuit, so that the characteristics are stable.

In the embodiment of the present invention, the shift register unit does not include only an N-type transistor or only a P-type transistor, and the shift register unit in the embodiment of the present invention is a CMOS circuit, and may include a gate circuit composed of an N-type transistor and a P-type transistor, for example, at least one of a tri-state gate, an inverter, a nor gate, a nand gate, and a transmission gate, and the shift register unit in the embodiment of the present invention has stable characteristics, and under the severe reliability test conditions of high temperature, high humidity, and the like, due to the complementarity of the characteristics of the N-type transistor and the P-type transistor, the shift register unit can effectively avoid the drift of the threshold voltages of the N-type transistor and the P-type transistor, and can not cause the false turn-on or false turn-off of the transistors, and can not cause the failure of the shift register unit, so that the gate line in the, display abnormality is not caused.

The shift register unit provided by the embodiment of the invention has the advantages of simple circuit structure, small number of adopted transistors and stable output of grid driving signals. When the shift register unit is applied to a display screen of a mobile terminal (the mobile terminal can be a mobile phone or a tablet personal computer, for example), the shift register unit is beneficial to realizing a narrow frame.

In the related art, a display device may include a display substrate, and a plurality of rows of gate lines, a plurality of columns of data lines, and a plurality of rows and a plurality of columns of pixel units disposed on the display substrate. The shift register unit according to the embodiment of the present invention is configured to provide a gate driving signal to a gate line included in a display device, and in a corresponding driving time period of a display stage, the gate driving signal can control the corresponding gate line to be opened so as to write a corresponding data signal into a corresponding pixel unit, so that the pixel unit can display at a corresponding brightness according to the data signal. The shift register unit provided by the embodiment of the invention has stable output characteristics, and the display quality and the user experience of the display device cannot be influenced.

The shift register unit according to the embodiment of the present invention is applied to a display device, and the display device may be an OLED (organic Light-Emitting Diode) display device, an LCD (Liquid crystal display) device, or a PLED (Polymer Light Emitting device) display device.

Liquid crystal display devices have been used in various display fields such as mobile phones, flat panel displays, vehicles, televisions, and public displays, because of their advantages such as low power consumption, miniaturization, and light weight.

An OLED (organic light emitting diode) is increasingly used in the field of high performance display due to its characteristics of self-luminescence, fast response, wide viewing angle, and being capable of being fabricated on a flexible substrate, etc., as a current type light emitting device.

Polymer Light Emitting Device (PLED) display devices are easy to produce and cost effective. The application of ink jet printing techniques to the manufacture of PLED display products is easy to implement and can be used to manufacture large size display products. With the progress of high-performance polymers and thin film production methods, PLED display devices are widely used.

As shown in fig. 1, the shift register unit according to the embodiment of the present invention includes a shift register module 11 and an output module 12, wherein,

the shift register module 11 is electrically connected to an Input signal end Input, a shift output node N2, a carry output signal end STV _ N, a Reset end Reset, and a first clock signal end, and configured to shift register an Input signal provided by the Input signal end Input under the control of a Reset signal Input by the Reset end Reset and a first clock signal CLK Input by the first clock signal end to generate a carry output signal, output the carry output signal through the carry output signal end STV _ N, and control a voltage signal of the shift output node N2 to be in phase opposition to the carry output signal;

the output module 12 is electrically connected to the gate driving signal output terminal OUT _ N, the carry output signal terminal STV _ N, and the second clock signal terminal, respectively, and is configured to generate a gate driving signal according to the carry output signal and the second clock signal CLKB input by the second clock signal terminal, and output the gate driving signal through the gate driving signal output terminal OUT _ N.

In the embodiment shown in fig. 1, the output control signal is the carry output signal.

When the embodiment of the shift register unit shown in fig. 1 of the present invention is in operation, the shift register module 11 controls the carry output signal output terminal STV _ N to output the carry output signal, and controls the voltage signal of the shift output node N2 to be in phase opposition to the carry output signal, and the output module 12 generates the gate driving signal according to the carry output signal and the second clock signal CLKB.

As shown in fig. 2, the shift register unit according to the embodiment of the present invention includes a shift register module 11 and an output module 12, wherein,

the output module 12 is electrically connected to the gate driving signal output terminal OUT _ N, the shift output node N2, and the second clock signal terminal, and configured to generate a gate driving signal according to the voltage signal of the shift output node N2 and the second clock signal CLKB input by the second clock signal terminal, and output the gate driving signal through the gate driving signal output terminal OUT _ N.

In the embodiment shown in fig. 2, the output control signal is a voltage signal of the shift output node.

When the embodiment of the shift register unit shown in fig. 2 of the present invention is in operation, the shift register module 11 controls the carry output signal output terminal STV _ N to output the carry output signal, and controls the voltage signal of the shift output node N2 to be in phase opposition to the carry output signal, and the output module 12 generates the gate driving signal according to the voltage signal of the shift output node N2 and the second clock signal CLKB.

Specifically, the shift register module may include a first node control circuit, a shift output node control circuit, and a carry output circuit, wherein,

In a specific implementation, the shift register module may include a first node control circuit, a shift output node control circuit, and a carry output circuit, where the first node control circuit controls a voltage signal of a first node, the shift output node control circuit is configured to control the voltage signal of the shift output node, and the carry output circuit is configured to obtain the carry output signal according to the voltage signal of the shift output node.

As shown in fig. 3, the shift register module may include a first node control circuit 111, a shift output node control circuit 112, and a carry output circuit 113, wherein,

the first node control circuit 111 is electrically connected to the first clock signal terminal and the first node N1, and configured to invert the first clock signal CLK and output the inverted first clock signal to a first node N1;

the shift output node control circuit 112 is electrically connected to an Input signal terminal Input, the first node N1, the first clock signal terminal, the Reset terminal Reset, a carry output signal terminal STV _ N, and the shift output node N2, respectively, and is configured to control a voltage signal of the shift output node N2 under the control of the Input signal, the voltage signal of the first node N1, the first clock signal CLK, the Reset signal, and the carry output signal;

the carry output circuit 113 is electrically connected to the shift output node N2 and the carry output signal terminal STV _ N, respectively, and is configured to invert the voltage signal of the shift output node N2 to obtain the carry output signal, and output the carry output signal through the carry output signal terminal STV _ N.

In specific implementation, the first node control circuit 111 controls the voltage signal of the first node N1, the shift output node control circuit 112 controls the voltage signal of the shift output node N2, and the carry output circuit 113 controls the carry output signal to be output through the carry output signal terminal STV _ N.

Specifically, the first node control circuit may include a first inverter;

In particular, the shift output node control circuit may include a first tri-state gate, a second tri-state gate, and a reset sub-circuit, wherein,

In specific implementation, the first tri-state gate, the second tri-state gate and the reset sub-circuit control a voltage signal of a shift output node; in a reset stage before the display stage, under the control of a reset signal, the reset sub-circuit controls the shift output node to be communicated with the first voltage end, so that a voltage signal of the shift output node is a first voltage signal; in the display stage, the first tri-state gate controls the voltage signal of the shift output node under the control of the first clock signal, the input signal and the voltage signal of the first node, and the second tri-state gate controls the voltage signal of the shift output node under the control of the voltage signal of the first node, the carry output signal and the first clock signal.

In a specific implementation, the first voltage terminal may be a high voltage terminal, but is not limited thereto.

As shown in fig. 4, on the basis of the embodiment of the shift register module shown in fig. 3, the first node control circuit 111 may include a first inverter NOT 1;

the input end of the first inverter NOT1 is connected with a first clock signal CLK, and the output end of the first inverter NOT1 is electrically connected with the first node N1;

the shift output node control circuit 112 may include a first TRI-state gate TRI1, a second TRI-state gate TRI2, and a reset sub-circuit 40, wherein,

a first control terminal of the first TRI-state gate TRI1 is connected to the first clock signal CLK, a second control terminal of the first TRI-state gate TRI1 is electrically connected to the Input signal terminal Input, a third control terminal of the first TRI-state gate TRI1 is electrically connected to the first node N1, and an output terminal of the first TRI-state gate TRI1 is electrically connected to the shift output node N2;

a first control terminal of the second TRI-state gate TRI2 is electrically connected to the first node N1, a second control terminal of the second TRI-state gate TRI2 is electrically connected to the carry output signal terminal STV _ N, a third control terminal of the second TRI-state gate TRI2 is connected to the first clock signal CLK, and an output terminal of the second TRI-state gate TRI2 is electrically connected to the shift output node N2;

the control terminal of the Reset sub-circuit 40 is electrically connected to the Reset terminal Reset, the first terminal of the Reset sub-circuit 40 is electrically connected to the shift output node N2, the second terminal of the Reset sub-circuit 40 is electrically connected to a high voltage terminal, and the Reset sub-circuit 40 is configured to control the shift output node N2 to communicate with the high voltage terminal under the control of the Reset signal;

the high voltage end is used for inputting a high voltage VDD.

In particular implementations, the first tri-state gate may include a first transistor, a second transistor, a third transistor, and a fourth transistor;

In a specific implementation, the second tri-state gate may include a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

In an embodiment of the invention, the second voltage terminal may be a low voltage terminal, and the first voltage terminal may be a high voltage terminal, but not limited thereto.

In particular implementations, the reset sub-circuit may include a reset transistor;

In the reset phase, under the control of a reset signal, the reset transistor is conducted so that the shift output node is communicated with the first voltage end to reset the potential of the shift output node to the first voltage.

As shown in fig. 5, the first TRI-state gate TRI1 in fig. 4 may include a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4;

the gate of the first transistor M1 is electrically connected to the first control terminal a1 of the first TRI-state gate TRI1, and the source of the first transistor M1 is electrically connected to the low voltage terminal for inputting the low voltage VSS;

the gate of the second transistor M2 is electrically connected to the second control terminal B1 of the first TRI-state gate TRI1, the source of the second transistor M2 is electrically connected to the drain of the first transistor M1, and the drain of the second transistor M2 is electrically connected to the output terminal D1 of the first TRI-state gate TRI 1;

the gate of the third transistor M3 is electrically connected to the second control terminal B1 of the first TRI-state gate TRI1, and the drain of the third transistor M3 is electrically connected to the output terminal D1 of the first TRI-state gate TRI 1;

a gate of the fourth transistor M4 is electrically connected to the third control terminal C1 of the first TRI-state gate TRI1, a drain of the fourth transistor M4 is electrically connected to a source of the third transistor M3, and a source of the fourth transistor M4 is electrically connected to a high voltage terminal for inputting a high voltage VDD.

In the embodiment of the first TRI-state gate TRI1 shown in fig. 5, M1 and M2 may be NTFT (N-type thin film transistor), and M3 and M4 may be PTFT (P-type thin film transistor), but not limited thereto. When the first TRI-state gate TRI1 shown in fig. 5 is in operation, when B1 is turned on low level and C1 is turned on low level, a high voltage is output through D1;

when A1 and B1 are switched into high level, a low voltage is output through D1;

when the A1 and the B1 are switched to a low level and the C1 is switched to a high level, the D1 is in a high impedance state;

when A1, B1 and C1 are all switched in high level, a low voltage is output through D1;

when both A1 and C1 are switched to low level and B1 is switched to high level, D1 is in high impedance state;

when both A1 and C1 are switched on high level and B1 is switched on low level, D1 is in high impedance state;

when a1 goes low and both B1 and C1 go high, D1 is in a high impedance state.

As shown in fig. 6, the second TRI-state gate TRI2 in fig. 4 may include a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8; the gate of the fifth transistor M5 is electrically connected to the first control terminal a2 of the second TRI-state gate TRI2, and the drain of the fifth transistor M5 is electrically connected to the low voltage terminal for inputting the low voltage VSS;

the gate of the sixth transistor M6 is electrically connected to the second control terminal B2 of the second TRI-state gate TRI2, the drain of the sixth transistor M6 is electrically connected to the source of the fifth transistor M5, and the source of the sixth transistor M6 is electrically connected to the output terminal D2 of the second TRI-state gate TRI 2;

the gate of the seventh transistor M7 is electrically connected to the second control terminal B2 of the second TRI-state gate TRI2, and the drain of the seventh transistor M7 is electrically connected to the output terminal D2 of the second TRI-state gate TRI 2;

a gate of the eighth transistor M8 is electrically connected to the third control terminal C2 of the second TRI-state gate TRI2, a drain of the eighth transistor M8 is electrically connected to a source of the seventh transistor M7, and a source of the eighth transistor M8 is electrically connected to a high voltage terminal for inputting a high voltage VDD.

In the embodiment of the second TRI-state gate TRI2 shown in fig. 6, M5 and M6 may be NTFT (N-type thin film transistor), and M7 and M8 may be PTFT (P-type thin film transistor), but not limited thereto.

When the second TRI-state gate TRI2 shown in fig. 6 is in operation, when B2 is turned on low level and C2 is turned on low level, a high voltage is output through D2;

when A2 and B2 are switched into high level, a low voltage is output through D2;

when the A2 and the B2 are switched to a low level and the C2 is switched to a high level, the D2 is in a high impedance state;

when A2, B2 and C2 are all switched in high level, a low voltage is output through D2;

when both A2 and C2 are switched to low level and B2 is switched to high level, D2 is in high impedance state;

when both A2 and C2 are switched on high level and B2 is switched on low level, D2 is in high impedance state;

when a2 goes low and both B2 and C2 go high, D2 is in a high impedance state.

Specifically, the carry output circuit may include a second inverter;

In a specific implementation, the carry output circuit may include a second inverter, where the second inverter is configured to invert the voltage signal of the shift output node to obtain a carry output signal, and output the carry output signal through the carry output signal terminal.

According to a specific embodiment, the output control signal may be the carry output signal; the output module may include a nand gate and a third inverter;

As shown in fig. 7, on the basis of the embodiment of the shift register cell shown in fig. 1, the output module 12 may include a NAND gate NAND and a third inverter NOT 3;

a first input end of the NAND gate is electrically connected with the carry output signal end STV _ N, and a second input end of the NAND gate is connected with a second clock signal CLKB;

an input end of the third inverter NOT3 is electrically connected to an output end of the NAND gate NAND, and an output end of the third inverter NOT3 is electrically connected to the gate driving signal output end OUT _ N.

When the embodiment of the shift register unit shown in fig. 7 of the present invention is in operation, NAND outputs a low voltage signal when both the carry output signal and CLKB are high voltage signals;

when the carry output signal is a high voltage signal and CLKB is a low voltage signal, NAND outputs the high voltage signal;

when the carry output signal is a low voltage signal and CLKB is a high voltage signal, NAND outputs a high voltage signal;

when the carry output signal and the CLKB are both low-voltage signals, the NAND outputs a high-voltage signal;

when the NAND outputs a low voltage signal, the OUT _ N outputs a high voltage signal;

when the NAND outputs a high voltage signal, OUT _ N outputs a low voltage signal.

According to another specific embodiment, the output control signal may be a voltage signal of the shift output node; the output module may include a nor gate;

As shown in fig. 8, on the basis of the embodiment of the shift register cell shown in fig. 2, the output block 12 may comprise a NOR gate NOR;

a first input terminal of the NOR gate NOR is electrically connected to the shift output node N2, a second input terminal of the NOR gate NOR is connected to the second clock signal CLKB, and an output terminal of the NOR gate NOR is electrically connected to the gate driving signal output terminal OUT _ N.

When the embodiment of the shift register cell of the present invention shown in fig. 8 is in operation, NOR outputs a high voltage signal when both the voltage signal of N2 and CLKB are low voltage signals;

when both the voltage signal of N2 and CLKB are high, NOR outputs a low voltage signal and OUT _ N outputs a low voltage signal;

when the voltage signal of N2 is a low voltage signal and the CLKB is a high voltage signal, the NOR outputs a low voltage signal;

when the voltage signal of N2 is a high voltage signal and the CLKB is a low voltage signal, the NOR outputs a low voltage signal.

In a preferred case, the shift register unit according to the embodiment of the present invention may further include an input control module;

The shift register unit of the embodiment of the invention can adopt the input control module to control the scanning direction, and when the forward scanning is needed, the input control module controls the communication between the input signal end and the adjacent previous-stage carry output signal end under the control of the forward scanning control signal and the reverse scanning control signal; when reverse scanning is needed, the input control module controls the input signal end to be communicated with the adjacent next-stage carry output signal end under the control of the forward scanning control signal and the reverse scanning control signal.

As shown in fig. 9, on the basis of the embodiment of the shift register unit shown in fig. 1, the shift register unit according to the embodiment of the present invention may further include an input control module 90;

the Input control module 90 is respectively electrically connected to the forward scanning control terminal CN, the reverse scanning control terminal CNB, the adjacent previous-stage carry output signal terminal STV _ N-1, the adjacent next-stage carry output signal terminal STV _ N +1, and the Input signal terminal Input, and is configured to control the Input signal terminal Input to be communicated with the adjacent previous-stage carry output signal terminal STV _ N-1 or the adjacent next-stage carry output signal terminal STV _ N +1 under the control of the forward scanning control signal and the reverse scanning control signal;

the forward scan control terminal CN is configured to provide the forward scan control signal, and the reverse scan control terminal CNB is configured to provide the reverse scan control signal.

When the embodiment of the shift register unit shown in fig. 9 of the present invention is in operation, the Input control module 90 controls the Input to be electrically connected to STV _ N-1 or STV _ N +1 under the control of the forward scan control signal provided by CN and the reverse scan control signal provided by CNB, so as to control the forward scan or the reverse scan.

As shown in fig. 10, on the basis of the embodiment of the shift register unit shown in fig. 2, the shift register unit according to the embodiment of the present invention may further include an input control module 90;

When the embodiment of the shift register unit shown in fig. 10 of the present invention is in operation, the Input control module 90 controls the Input to be electrically connected to STV _ N-1 or STV _ N +1 under the control of the forward scan control signal provided by CN and the reverse scan control signal provided by CNB, so as to control the forward scan or the reverse scan.

Specifically, the input control module may include a first transmission gate and a second transmission gate;

When the forward scanning control signal is a high-voltage signal and the reverse scanning control signal is a low-voltage signal, the input signal end is communicated with the adjacent upper-stage carry output signal end; when the forward scanning control signal is a low voltage signal and the reverse scanning control signal is a high voltage signal, the input signal end is communicated with the adjacent next stage carry output signal end.

In a specific implementation, the input control module may include a first transmission gate and a second transmission gate, where when the non-inverting control terminal of the first transmission gate is connected to a high voltage signal and the inverting control terminal of the first transmission gate is connected to a low voltage signal, the input terminal of the first transmission gate and the output terminal of the first transmission gate are connected, and when the non-inverting control terminal of the first transmission gate is connected to a low voltage signal and the inverting control terminal of the first transmission gate is connected to a high voltage signal, the input terminal of the first transmission gate and the output terminal of the first transmission gate are not connected; when the positive phase control end of the second transmission gate is connected with the low voltage signal and the negative phase control end of the second transmission gate is connected with the high voltage signal, the input end of the second transmission gate is connected with the output end of the second transmission gate, and when the positive phase control end of the second transmission gate is connected with the low voltage signal and the negative phase control end of the second transmission gate is connected with the high voltage signal, the input end of the second transmission gate is not connected with the output end of the second transmission gate.

Preferably, the shift register unit according to the embodiment of the present invention further includes an output control module;

In a preferred case, the shift register unit according to the embodiment of the present invention may further include an output control module, and in a fast discharging stage, under the control of the enable signal, the output terminal of the gate driving signal is controlled to output the first voltage, so that the corresponding row gate line is opened, and the charges remaining in the pixel circuit are released.

Specifically, when the output module includes a nand gate and a third inverter, the output control module may include a pull-down circuit and a control circuit;

In a specific implementation, the output control module may include a pull-down circuit and a control circuit, where the pull-down circuit controls an input terminal of a third inverter to access a second voltage signal under the control of an enable signal, so that the third inverter outputs a first voltage signal; and the control circuit controls the NAND gate not to output the first voltage signal under the control of the enable signal, so that the third inverter cannot output the second voltage signal, and error output is avoided.

As shown in fig. 11, on the basis of the embodiment of the shift register unit shown in fig. 7, the shift register unit according to the embodiment of the present invention further includes an output control module; the output control module may include a pull-down circuit 71 and a control circuit 72;

the pull-down circuit 71 is respectively electrically connected with an enable terminal EN, the input terminal of the third inverter NOT3 and a low-voltage terminal for inputting a low voltage VSS, and is used for controlling the input terminal of the third inverter NOT3 to be communicated with the low-voltage terminal under the control of an enable signal input by EN;

the control circuit 72 is electrically connected to the enable terminal EN and the NAND gate NAND, respectively, and is configured to control the NAND gate NAND to be unable to output a high-voltage signal under the control of the enable signal, so as to control the third inverter NOT3 to be unable to output a low-voltage signal.

In the embodiment of the invention, the second voltage signal may be a low voltage signal, and the first voltage signal may be a high voltage signal, but not limited thereto.

Specifically, the pull-down circuit comprises a pull-down transistor;

In a specific implementation, the nand gate may include a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein,

As shown in fig. 12, in the embodiment of the shift register cell of the present invention as shown in fig. 11, the NAND gate NAND may include a ninth transistor MA1, a tenth transistor MA2, an eleventh transistor MA3, and a twelfth transistor MA4, wherein,

the gate of the ninth transistor MA1 is electrically connected to the first input terminal I1 of the NAND gate, and the drain of the ninth transistor MA1 is electrically connected to the low voltage terminal; the low voltage end is used for inputting low voltage VSS;

the gate of the tenth transistor MA2 is electrically connected to the second input terminal I2 of the NAND gate, the drain of the tenth transistor MA2 is electrically connected to the source of the ninth transistor MA1, and the source of the tenth transistor MA2 is electrically connected to the output terminal Out of the NAND gate;

a gate of the eleventh transistor MA3 is electrically connected to the first input terminal I1 of the NAND gate, a drain of the eleventh transistor MA3 is electrically connected to the output terminal Out of the NAND gate, and a source of the eleventh transistor MA3 is electrically connected to the first terminal of the control circuit 72;

a gate of the twelfth transistor MA4 is electrically connected to the second input terminal I2 of the NAND gate, a drain of the twelfth transistor MA4 is electrically connected to the output terminal Out of the NAND gate, and a source of the twelfth transistor MA4 is electrically connected to the first terminal of the control circuit 72;

the control end of the control circuit 72 is electrically connected to the enable end EN, the second end of the control circuit 72 is electrically connected to the high-voltage end, and the control circuit 72 is configured to disconnect the first end of the control circuit 72 from the high-voltage end under the control of the enable signal; the high voltage end is used for inputting a high voltage VDD;

the ninth transistor and the tenth transistor may be NTFT (N-type thin film transistor), and the eleventh transistor and the twelfth transistor may be PTFT (P-type thin film transistor), but not limited thereto.

In operation of the shift register unit shown in fig. 12 of the present invention, during the fast discharging phase, under the control of the enable signal input by EN, the control circuit 72 controls the first terminal of the shift register unit not to be connected to the high voltage terminal, that is, the source of MA3 is not connected to the high voltage terminal, and the source of MA4 is not connected to the high voltage terminal, so that the NAND gate NAND cannot output the high voltage VDD.

When the embodiment of the shift register unit shown in fig. 12 of the present invention is in operation, in the display phase, under the control of the enable signal, the pull-down circuit 71 controls to disconnect the input terminal of the third inverter NOT3 from the low-voltage terminal, and the control circuit 72 controls to connect the first terminal of the pull-down circuit to the high-voltage terminal, so that the NAND gate NAND can output the high-voltage VDD.

In particular implementations, the control circuit 72 may include a control transistor;

the control electrode of the control transistor is a control terminal of the control circuit 72, the first electrode of the control transistor is a first terminal of the control circuit 72, and the second electrode of the control transistor is a second terminal of the control circuit 72.

Specifically, when the output module includes a nor gate, the output control module may include a pull-up circuit and a control circuit;

In a specific implementation, when the output module includes a nor gate, the output control module may include a pull-up circuit and a control circuit, and in a fast discharge phase, under the control of an enable signal, the pull-up circuit controls the gate drive signal output terminal to output a first voltage signal, and the control circuit controls the nor gate not to output a second voltage signal, so as to ensure that no erroneous output occurs.

As shown in fig. 13, on the basis of the embodiment of the shift register unit shown in fig. 8, the shift register unit according to the embodiment of the present invention further includes an output control module; the output control module includes a pull-up circuit 70 and a control circuit 72;

the pull-up circuit 70 is respectively electrically connected to the enable terminal EN, the gate driving signal output terminal OUT _ N, and the high voltage terminal, and is configured to control the connection between the gate driving signal output terminal OUT _ N and the high voltage terminal under the control of the enable signal, so as to control OUT _ N to output a high voltage signal; the high voltage end is used for inputting a high voltage VDD;

the control circuit 72 is electrically connected to the enable terminal EN and the NOR gate NOR, respectively, and is configured to control the NOR gate NOR to be incapable of outputting a low voltage signal under the control of the enable signal.

Specifically, the pull-up circuit may include a pull-up transistor;

In a specific implementation, the nor gate may include a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

As shown in fig. 14, in the embodiment of the shift register unit shown in fig. 13, the NOR gate NOR may include a thirteenth transistor MR1, a fourteenth transistor MR2, a fifteenth transistor MR3, and a sixteenth transistor MR 4;

the gate of the thirteenth transistor MR1 is electrically connected to the second input terminal F2 of the NOR gate NOR, and the source of the thirteenth transistor MR1 is electrically connected to the high voltage terminal; the high voltage end is used for inputting a high voltage VDD;

a gate of the fourteenth transistor MR2 is electrically connected to the first input terminal F1 of the NOR gate NOR, a source of the fourteenth transistor MR2 is electrically connected to a drain of the thirteenth transistor MR1, and a drain of the fourteenth transistor MR2 is electrically connected to the output terminal M of the NOR gate NOR;

a gate of the fifteenth transistor MR3 is electrically connected to the second input terminal F2 of the NOR gate NOR, a drain of the fifteenth transistor MR3 is electrically connected to the output terminal M of the NOR gate NOR, and a source of the fifteenth transistor MR3 is electrically connected to the first terminal of the control circuit 72;

a gate of the sixteenth transistor MR4 is electrically connected to the first input terminal F1 of the NOR gate NOR, a drain of the sixteenth transistor MR4 is electrically connected to the output terminal of the NOR gate NOR, and a source of the sixteenth transistor MR4 is electrically connected to the first terminal of the control circuit 72;

the control end of the control circuit 72 is electrically connected to the enable end EN, the second end of the control circuit 72 is electrically connected to the low-voltage end, and the control circuit 72 is configured to disconnect the first end of the control circuit 72 from the low-voltage end under the control of the enable signal; the low voltage end is used for inputting low voltage VSS;

the thirteenth transistor MR1 and the fourteenth transistor MR2 may be PTFT (P-type thin film transistor), and the fifteenth transistor MR3 and the sixteenth transistor MR4 may be NTFT (N-type thin film transistor), but not limited thereto.

In operation of the shift register unit shown in fig. 14 of the present invention, during the fast discharging phase, under the control of the enable signal inputted by EN, the control circuit 72 controls the first terminal of the shift register unit not to be connected to the low voltage terminal, that is, the source of MR3 is not connected to the low voltage terminal, and the source of MR4 is not connected to the low voltage terminal, so that the NOR gate NOR cannot output the low voltage VSS.

In operation of the shift register cell of the embodiment of the present invention as shown in fig. 14, in the display phase, under the control of the enable signal, the pull-up circuit 70 controls to disconnect the output terminal of the NOR gate NOR from the high voltage terminal, and the control circuit 72 controls to connect the first terminal of the NOR gate NOR to the low voltage terminal, so that the NOR gate NOR can output the low voltage VSS.

The shift register unit according to the invention is described below in two specific embodiments.

As shown in fig. 15, the first embodiment of the shift register unit of the present invention includes a shift register module, an output module 12, an input control module 90, and an output control module;

the shift register module includes a first node control circuit 111, a shift output node control circuit 112, and a carry output circuit 113, wherein,

the first node control circuit 111 includes a first inverter NOT 1;

the input end of the first inverter NOT1 is connected to a first clock signal CLK, and the output end of the first inverter NOT1 is electrically connected to the first node N1.

The shift output node control circuit 112 comprises a first TRI-state gate TRI1, a second TRI-state gate TRI2, and a reset sub-circuit, wherein,

the reset subcircuit includes a reset transistor NTFT 9;

a gate of the Reset transistor NTFT9 is electrically connected to the Reset terminal Reset, a drain of the Reset transistor NTFT9 is electrically connected to the shift output node N2, and a source of the Reset transistor NTFT9 is electrically connected to a high voltage terminal; the high voltage end is used for inputting a high voltage VDD;

the carry output circuit 113 includes a second inverter NOT 2;

an input end of the second inverter NOT2 is electrically connected to the shift output node N2, and an output end NOT2 of the second inverter is electrically connected to the carry output signal end STV _ N;

the output module 12 includes a NAND gate NAND and a third inverter NOT 3;

the input end of the third inverter NOT3 is electrically connected with the output end of the NAND gate NAND, and the output end of the third inverter NOT3 is electrically connected with the gate drive signal output end OUT _ N;

the input control module 90 includes a first transmission gate TG1 and a second transmission gate TG 2;

a positive phase control end of the first transmission gate TG1 is electrically connected with the positive direction scanning control end CN, an inverted phase control end of the first transmission gate TG1 is electrically connected with the inverted direction scanning control end CNB, an Input end of the first transmission gate TG1 is electrically connected with the adjacent previous stage carry output signal end STV _ N-1, and an output end of the first transmission gate TG1 is electrically connected with the Input signal end Input;

a positive phase control end of the second transmission gate TG2 is electrically connected with the reverse scan control end CNB, a negative phase control end of the second transmission gate TG2 is electrically connected with the positive scan control end CN, an Input end of the second transmission gate TG2 is electrically connected with the adjacent next-stage carry output signal end STV _ N +1, and an output end of the second transmission gate TG2 is electrically connected with the Input signal end Input;

the output control module comprises a pull-down circuit 71 and a control circuit 72;

the pull-down circuit 71 includes a pull-down transistor NTFT 4; the control circuit 72 includes a control transistor PTFT 0;

the gate of the pull-down transistor NTFT4 is electrically connected to the enable terminal EN, the drain of the pull-down transistor NTFT4 is electrically connected to the low voltage terminal, and the source of the pull-down transistor NTFT4 is electrically connected to the input terminal of the third inverter NOT 3; the low voltage end is used for inputting low voltage VSS;

the gate of the control transistor PTFT0 is electrically connected with the enable terminal EN, the source of the control transistor PTFT0 is electrically connected with the high voltage input terminal of the NAND gate NAND, and the drain of the control transistor PTFT0 is electrically connected with the high voltage terminal; the high voltage end is used for inputting a high voltage VDD.

In fig. 15, the third node N3 is a node electrically connected to STV _ N, and the fourth node N4 is a node electrically connected to an input terminal of NOT 3.

In a first specific embodiment of the shift register unit according to the present invention, the output control signal is the carry output signal.

In the first embodiment of the shift register unit according to the present invention, the NTFT9 and NTFT4 are n-type thin film transistors, and the PTFT0 is a p-type thin film transistor, but not limited thereto.

In the first embodiment of the shift register unit according to the present invention, during the Reset phase before the display phase, the Reset signal inputted by Reset is a high voltage signal to control the NTFT9 to be turned on, so as to Reset the voltage signal of the shift output node N2 to be a high voltage signal; in the display stage, the Reset signal input by Reset is a low voltage signal to control NTFT9 to be switched off;

when the first specific embodiment of the shift register unit works, in a fast discharging stage, an enable signal input by EN is a high-voltage signal, NTFT4 is turned on, and PTFT0 is turned off, so that the input end of NOT3 is connected to VSS, and the high-voltage input end of NAND cannot be connected to high-voltage VDD, so that NAND cannot output a high level, so that NOT3 outputs a high level, that is, OUT _ N outputs a high level, to control a corresponding row gate line to be opened, thereby releasing charges remaining in a corresponding pixel circuit; in the display phase, the enable signal input by EN is a low voltage signal, NTFT4 is turned off, and PTFT0 is turned on, so that the NAND can output a high level.

As shown in fig. 16, when the first embodiment of the shift register unit according to the present invention operates, taking forward scan as an example, at this time, CN inputs high level, CNB inputs low level, and TG1 controls communication between Input and STV _ N-1;

in the display phase, the display device is,

in the first input period ti1, STV _ N-1 inputs a high level, CLK is a low level, CLKB is a high level, the potential of N1 is a high level, N2 registers a high level of the reset stage, STV _ N outputs a low level, TRI2 outputs a high level, NAND outputs a high level, and OUT _ N outputs a low level;

in a second input period ti2, a high level is input to STV _ N-1, CLK is a high level, CLKB is a low level, a potential of N1 is a low level, TRI1 outputs a low level, a potential of N2 is a low level, STV _ N outputs a high level, TRI2 does not output (that is, an output terminal of TRI2 is in a high impedance state), NAND outputs a high level, and OUT _ N outputs a low level;

in the output time period to, a low level is input into STV _ N-1, CLK is a low level, CLKB is a high level, the potential of N1 is a high level, the TRI1 does not output (that is, the output end of the TRI1 is in a high impedance state), the N2 registers the low level of the previous time period, STV _ N outputs a high level, the TRI2 outputs a low level, NAND outputs a low level, and OUT _ N outputs a high level;

in a first output off period tc1, STV _ N-1 inputs a high level, CLK is a high level, CLKB is a low level, TRI1 outputs a high level, the potential of N2 is a high level, STV _ N outputs a low level, TRI2 does not output, NAND outputs a high level, OUT _ N outputs a low level;

in the second output off period tc2, STV _ N-1 inputs a high level, CLK is a low level, CLKB is a high level, TRI1 does not output, N2 registers a high level of the previous period, STV _ N outputs a low level, TRI2 outputs a high level, NAND outputs a high level, and OUT _ N outputs a low level.

In the first embodiment of the shift register unit according to the present invention, NTFT9 may be replaced by a p-type thin film transistor, NTFT4 may be replaced by a p-type thin film transistor, and PTFT0 may be replaced by an n-type thin film transistor, and the transistors may be turned on or off only by changing the potentials of the gates of the transistors.

As shown in fig. 17, the second embodiment of the shift register unit of the present invention includes a shift register module, an output module 12, an input control module 90, and an output control module;

the first node control circuit 111 includes a first inverter NOT 1;

the reset subcircuit includes a reset transistor NTFT 9;

the carry output circuit 113 includes a second inverter NOT 2;

the output module 12 comprises a NOR gate NOR;

a first input terminal of the NOR gate NOR is electrically connected to the shift output node N2, a second input terminal of the NOR gate NOR is connected to a second clock signal CLKB, and an output terminal of the NOR gate NOR is electrically connected to the gate driving signal output terminal OUT _ N;

the output control module includes a pull-up circuit 70 and a control circuit 72;

the pull-up circuit 70 includes a pull-up transistor NTFT 0; the control circuit 72 includes a control transistor PTFT 0;

the gate of the pull-up transistor NTFT0 is electrically connected to an enable terminal EN, the drain of the pull-up transistor NTFT0 is electrically connected to a high voltage terminal, and the source of the pull-up transistor NTFT0 is electrically connected to the output terminal of the NOR gate NOR; the high voltage end is used for inputting a high voltage VDD;

the gate of the control transistor PTFT0 is electrically connected to the enable terminal EN, the source of the control transistor PTFT0 is electrically connected to the low voltage input terminal of the NOR gate NOR, and the drain of the control transistor PTFT0 is electrically connected to the low voltage terminal; the low voltage end is used for inputting a low voltage VSS.

In a second embodiment of the shift register unit according to the present invention, the output control signal is a voltage signal of the shift output node N2.

In the second embodiment of the shift register unit according to the present invention, the NTFT9 and NTFT0 are n-type thin film transistors, and the PTFT0 is a p-type thin film transistor, but not limited thereto.

In the second embodiment of the shift register unit according to the present invention, during the Reset phase before the display phase, the Reset signal inputted by Reset is a high voltage signal to control the NTFT9 to be turned on, so as to Reset the voltage signal of the shift output node N2 to be a high voltage signal; in the display stage, the Reset signal input by Reset is a low voltage signal to control NTFT9 to be switched off;

when the second specific embodiment of the shift register unit works, in a fast discharging stage, an enable signal input by EN is a high-voltage signal, NTFT0 is turned on, and PTFT0 is turned off, so that OUT _ N is connected to VDD, and a low-voltage input end of NOR is not connected to low-voltage VSS, so that NOR cannot output a low level, so that OUT _ N outputs a high level to control a corresponding row gate line to be opened, thereby releasing charges remaining in a corresponding pixel circuit; in the display phase, the enable signal input by EN is a low voltage signal, NTFT0 is turned off, and PTFT0 is turned on, so that the NAND can output a high level.

As shown in fig. 18, when the second embodiment of the shift register unit according to the present invention operates, taking forward scan as an example, at this time, CN inputs high level, CNB inputs low level, and TG1 controls communication between Input and STV _ N-1;

in the display phase, the display device is,

in an input time period ti, a high level is input into STV _ N-1, CLK is a low level, CLKB is a high level, TRI1 does not output, N2 registers a high level in a reset stage, TIR2 outputs a high level, STV _ N outputs a low level, NOR outputs a low level, that is, OUT _ N outputs a low level;

in the output period to, the STV _ N-1 inputs a high level, CLK is a high level, CLKB is a low level, the TRI1 outputs a low level, that is, the potential of N2 is a low level, the STV _ N outputs a high level, the TRI2 does not output, and the NOR outputs a high level, that is, the OUT _ N outputs a high level;

in a first output off period tc1, STV _ N-1 outputs a low level, CLK is a low level, CLKB is a high level, TIR1 does not output, N2 registers a low level of a previous period, STV _ N outputs a high level, TRI2 outputs a low level, NOR outputs a low level, OUT _ N outputs a low level;

in a second output off period tc2, STV _ N-1 outputs a low level, CLK is a high level, CLKB is a low level, TRI1 outputs a high level, the potential of N2 is a high level, STV _ N outputs a low level, TRI2 does not output, NOR outputs a low level, OUT _ N outputs a low level;

in the third output off period tc3, STV _ N-1 outputs a low level, CLK is a low level, CLKB is a high level, N2 registers a high level of the previous period, STV _ N outputs a low level, TRI2 outputs a high level, NOR outputs a low level, and OUT _ N outputs a low level.

In the second embodiment of the shift register unit according to the present invention, NTFT9 may be replaced by a p-type thin film transistor, NTFT0 may be replaced by a p-type thin film transistor, and PTFT0 may be replaced by an n-type thin film transistor, and the transistors may be turned on or off only by changing the potentials of the gates of the transistors.

Compared with the first embodiment of the shift register unit, the second embodiment of the shift register unit provided by the invention adopts one less inverter, so that the number of adopted transistors is reduced, the size of a frame of a display panel is further reduced, and the realization of a narrow frame is facilitated.

The driving method according to the embodiment of the present invention is applied to the shift register unit, and includes:

In the driving method according to the embodiment of the present invention, the shift register module performs shift register on an input signal under the control of a reset signal and a first clock signal to generate a carry output signal, and controls a voltage signal of the shift output node to be in phase opposition to the carry output signal; the output module generates a gate driving signal according to the output control signal and the second clock signal, so that the shift register unit can conveniently and quickly generate the gate driving signal.

According to a specific embodiment, the shift register module may include a first node control circuit, a shift output node control circuit, and a carry output circuit, and the driving time includes a reset phase and a display phase that are sequentially set;

the step of the shift register module shifting and registering the input signal under the control of the reset signal and the first clock signal to generate a carry output signal, and controlling the voltage signal of the shift output node to be inverted with respect to the carry output signal may include:

In a specific implementation, in a reset stage before the display stage, the shift output node control circuit controls to reset the potential of the shift output node to a first voltage under the control of a reset signal input by the reset terminal, so as to avoid that the shift output node is in a floating state and no carry output signal is output when the display stage starts.

In a preferred case, the shift register unit according to the embodiment of the present invention may further include an output control module; the driving method according to the embodiment of the present invention may further include:

in the discharging stage, under the control of an enable signal input by an enable end, the output control module controls the gate driving signal output end to output a first voltage so as to control the corresponding row of gate lines to be opened and release charges remained in the corresponding row of pixel circuits.

According to a specific embodiment, the output control signal may be a carry output signal; the output module may include a nand gate and a third inverter; the first input end of the NAND gate is electrically connected with the carry output signal end, and the second input end of the NAND gate is electrically connected with the second clock signal end; the input end of the third inverter is electrically connected with the output end of the NAND gate, and the output end of the third inverter is electrically connected with the gate drive signal output end;

the step of generating the gate driving signal by the output module according to the output control signal and the second clock signal may include: in the display phase, the display device is,

and the third inverter inverts the signal to obtain the gate driving signal, and outputs the gate driving signal through the gate driving signal output end.

In this embodiment of the present invention, the output control signal may be a carry output signal, the output module may include a nand gate and a third inverter, and when both the carry output signal and the second clock signal are at a high level, the nand gate outputs a low level; when the carry output signal and/or the second clock signal are/is at a low level, the NAND gate outputs a high level; and the signal output by the NAND gate is inverted by the third inverter to obtain a gate drive signal.

in the discharging stage, the step of controlling the gate driving signal output terminal to output the first voltage by the output control module under the control of the enable signal input by the enable terminal may include:

In a specific implementation, the second voltage terminal may be a low voltage terminal, and the first voltage terminal may be a high voltage terminal, but not limited thereto.

In a specific implementation, when the output module includes the nand gate and the third inverter, the output control module may include a pull-down circuit and a control circuit, and in a discharging stage, the control circuit controls the nand gate not to output the first voltage signal but only to output the second voltage signal, and controls the input terminal of the third inverter to be connected to the second voltage terminal, so as to ensure that the gate driving signal output terminal outputs the first voltage, thereby controlling the corresponding gate line to be opened.

According to another specific embodiment, the output control signal may be a voltage signal of the shift output node; the output module comprises a NOR gate; a first input end of the NOR gate is electrically connected with the shift output node, a second input end of the NOR gate is electrically connected with a second clock signal end, and an output end of the NOR gate is electrically connected with the gate drive signal output end;

the step of generating the gate driving signal by the output module according to the output control signal and the second clock signal may include: and in a display stage, the NOR gate generates a gate driving signal according to the voltage signal of the shift output node and a second clock signal, and outputs the gate driving signal through the gate driving signal output end.

In an embodiment of the present invention, the output control signal may be a voltage signal of the shift output node, the output module may include a nor gate, and when the voltage signal of the shift output node and/or the second clock signal is at a high level, the nor gate outputs a low level, that is, the gate driving signal output end outputs a low level; when the voltage signal of the shift output node and the second clock signal are both at a low level, the nor gate outputs a high level, that is, the gate driving signal output terminal outputs a high level.

Specifically, when the output module includes a nor gate, the output control module may include a pull-up circuit and a control circuit; in the discharging stage, the step of controlling the gate driving signal output terminal to output the first voltage by the output control module under the control of the enable signal input by the enable terminal may include:

Preferably, the shift register unit according to the embodiment of the present invention may further include an input control module; the driving method may further include: and the input control module controls the input signal end to be communicated with the adjacent upper-stage carry output signal end or the adjacent lower-stage carry output signal end under the control of a forward scanning control signal and a reverse scanning control signal.

Preferably, the shift register unit according to the embodiment of the present invention may further include an input control module to control the forward scanning or the reverse scanning.

In specific implementation, when the input control module controls the input signal end to be communicated with the adjacent previous-stage carry output signal end under the control of a forward scanning control signal and a reverse scanning control signal, the shift register unit in the embodiment of the invention is in a forward scanning state; when the input control module controls the input signal end to be communicated with the adjacent next-stage carry output signal end under the control of a forward scanning control signal and a reverse scanning control signal, the shift register unit in the embodiment of the invention is in a reverse scanning state.

The gate driving circuit according to the embodiment of the present invention may include a plurality of stages of the shift register units.

In a specific implementation, when the shift register unit includes the input control module, in the gate driving circuit according to the embodiment of the present invention, except for the first stage shift register unit and the last stage shift register unit, each stage of shift register unit is electrically connected to a carry output signal terminal of an adjacent previous stage shift register unit and a carry output signal terminal of an adjacent next stage shift register unit.

As shown in fig. 19, the gate driving circuit according to the embodiment of the present invention may include W stages of the shift register unit; w is a positive integer;

in fig. 19, a first stage shift register unit S1 included in the gate driver circuit, a second stage shift register unit S2 included in the gate driver circuit, a third stage shift register unit S3 included in the gate driver circuit, a W-1 stage shift register unit SW-1 included in the gate driver circuit, and a W stage shift register unit SW included in the gate driver circuit are shown;

the S1 is accessed to the start signal STV, and the carry output signal end of the S1 and the S2 are electrically connected;

s2 is respectively connected with the carry output signal terminal of S1 and the carry output signal terminal of S3;

s3 are electrically connected to the carry output signal terminal of S2 and the carry output signal terminal of the fourth stage shift register unit (not shown in fig. 19) included in the gate drive signal circuit, respectively;

the SW is electrically connected with the carry output signal end of the SW-1;

in FIG. 19, the gate-driving signal output terminal denoted by S1 denoted by OUT _1, the gate-driving signal output terminal denoted by S2 denoted by OUT _2, the gate-driving signal output terminal denoted by S3 denoted by OUT _3, the gate-driving signal output terminal denoted by SW-1 denoted by OUT _ W-1, and the gate-driving signal output terminal denoted by SW denoted by OUT _ W; reference numeral CLK is a first clock signal and reference numeral CLKB is a second clock signal.

When the embodiment of the gate driving circuit shown in fig. 19 of the present invention is in operation, during forward scanning, S1 turns on the start signal STV; and in the reverse scan, SW is turned on to start signal STV.

The display device provided by the embodiment of the invention comprises the gate drive circuit.

In the embodiment of the present invention, the Display device may be an OLED (organic Light-Emitting Diode) Display device, an LCD (Liquid Crystal Display) device, or a PLED (Polymer Light Emitting device) Display device, but not limited thereto.

According to a specific implementation manner, the display device according to the embodiment of the invention may include two gate driving circuits; the display device may further include N rows of pixel circuits; n is a positive integer;

In a specific implementation, the first gate driving circuit may provide corresponding gate driving signals for the odd-numbered pixel circuits, and the second gate driving circuit may provide corresponding gate driving signals for the even-numbered pixel circuits.

The display device provided by the embodiment of the invention can accelerate the grid scanning speed by providing corresponding grid driving signals for the odd-numbered row pixel circuit and the even-numbered row pixel circuit through the two grid driving circuits respectively.

In a specific implementation, the display device according to the embodiment of the invention may further include a display substrate; the N rows of pixel circuits are arranged on the display substrate;

the first gate driving circuit may be disposed at a left side of the display substrate, and the second gate driving circuit may be disposed at a right side of the display substrate; alternatively, the first gate driving circuit may be disposed at a right side of the display substrate, and the second gate driving circuit may be disposed at a left side of the display substrate, but not limited thereto.

According to another specific implementation manner, the display device according to the embodiment of the invention may include two gate driving circuits; the display device can further comprise a display substrate and N rows of pixel circuits arranged on the display substrate; n is a positive integer;

The display device provided by the embodiment of the invention can provide corresponding gate drive signals for the pixel circuits through the two gate drive circuits respectively, and can avoid the situation that partial pixel circuits are insufficiently charged due to unidirectional provision of the gate drive signals.

As shown in fig. 20, the first embodiment of the display device according to the present invention includes a control signal providing circuit 201, N rows of pixel circuits, a first gate driving circuit G1, and a second gate driving circuit G2; n is a positive integer;

the first gate driving circuit G1 is used for providing corresponding gate driving signals for the pixel circuits in odd rows;

the second gate driving circuit G2 is used for providing corresponding gate driving signals for the pixel circuits in the even rows;

the first gate driving circuit G1 is located at the left side of the display substrate (not shown in fig. 20), and the second gate driving circuit G2 is located at the right side of the display substrate;

the first stage shift register unit S11 included in the first gate driving circuit G1 is electrically connected to the first row Pixel circuits Pixel1, and is used for providing corresponding gate driving signals for the first row Pixel circuits Pixel 1;

the second stage shift register unit S13 included in the first gate driving circuit G1 is electrically connected to the third row Pixel circuits Pixel3, and is used for providing corresponding gate driving signals for the third row Pixel circuits Pixel 3;

the first gate driving circuit G1 comprises a shift register unit S1N-3 of the second last stage electrically connected with the pixel circuit PixelN-3 of the N-3 th row for providing a corresponding gate driving signal for the pixel circuit PixelN-3 of the N-3 th row;

the last stage shift register unit S1N-1 included in the first gate driving circuit G1 is electrically connected to the pixel circuit PixelN-1 of the (N-1) th row, and is used for providing a corresponding gate driving signal for the pixel circuit PixelN-1 of the (N-1) th row;

the second gate driving circuit G2 includes a first stage shift register unit S12 electrically connected to the second row Pixel circuit Pixel2 for providing corresponding gate driving signals to the second row Pixel circuit Pixel 2;

the second stage shift register unit S14 included in the second gate driving circuit G2 is electrically connected to the fourth row Pixel circuit Pixel4, and is used for providing corresponding gate driving signals for the fourth row Pixel circuit Pixel 4;

the second gate driving circuit G2 includes a shift register unit S1N-2 in the second to last stage electrically connected to the pixel circuits PixelN-2 in the N-2 th row for providing corresponding gate driving signals to the pixel circuits PixelN-2 in the N-2 th row;

the shift register unit S1N of the last stage included in the second gate driving circuit G2 is electrically connected to the pixel circuits PixelN of the nth row, and is configured to provide corresponding gate driving signals to the pixel circuits PixelN of the nth row;

the control signal providing circuit 201 is configured to provide a left start signal STVL for S1N-1, and provide a first left clock signal CLKL and a second left clock signal CLKBL for the first gate driving circuit G1;

the control signal providing circuit 201 is used to provide a right start signal STVR for S1N and provide a first right clock signal CLKR and a second right clock signal CLKBR for the second gate driving circuit G2.

In the first embodiment of the display device shown in fig. 20, S11 is electrically connected to the carry output signal terminal of S13; s13 are electrically connected to the carry output signal terminal of S11 and the carry output signal terminal of the third stage shift register unit (not shown in fig. 20) included in the first gate driving circuit G1, respectively;

the S1N-1 is also electrically connected with the carry output signal end of the S1N-3; the carry output signal end of S1N-3 and S1N-1 is electrically connected;

s14 are electrically connected to the carry output signal terminal of S12 and the carry output signal terminal of the third stage shift register unit (not shown in fig. 20) included in the second gate driving circuit G2, respectively;

S1N is also electrically connected to the carry out signal terminal of S1N-2, and S1N-2 is electrically connected to the carry out signal terminal of S1N.

In the first embodiment of the display device shown in fig. 20, a bilateral unidirectional gate driving scanning manner is adopted, and the first gate driving circuit G1 located at the left side of the display substrate provides corresponding gate driving signals for the odd-numbered rows of pixel circuits, and the second gate driving circuit G2 located at the right side of the display substrate provides corresponding gate driving signals for the even-numbered rows of pixel circuits.

As shown in fig. 21, the second embodiment of the display device according to the present invention includes a control signal providing circuit 201, N rows of pixel circuits, a first gate driving circuit G1, and a second gate driving circuit G2; n is a positive integer;

the first gate driving circuit G1 is used for providing corresponding gate driving signals for the N rows of pixel circuits;

the second gate driving circuit G2 is used for providing corresponding gate driving signals for the N rows of pixel circuits;

the first gate driving circuit G1 is disposed at the left side of the display substrate (not shown in fig. 21), and the second gate driving circuit G2 is disposed at the right side of the display substrate;

the first stage shift register unit S11 included in the first gate driving circuit G1 is electrically connected to the first row Pixel circuits Pixel 1;

the second stage shift register unit S12 included in the first gate driving circuit G1 is electrically connected to the second row Pixel circuit Pixel 2;

the first gate driving circuit G1 comprises an N-1 stage shift register unit S1N-1 electrically connected with the N-1 row pixel circuit PixelN-1;

the first gate driving circuit G1 includes an nth stage shift register unit S1N electrically connected to the nth row pixel circuit PixelN;

the second gate driving circuit G2 includes a first stage shift register unit S21 electrically connected to the first row Pixel circuits Pixel 1;

the second stage shift register unit S22 included in the second gate driving circuit G2 is electrically connected to the second row Pixel circuit Pixel 2;

the second gate driving circuit G2 comprises an N-1 stage shift register unit S2N-1 electrically connected with the N-1 row pixel circuit PixelN-1;

the second gate driving circuit G2 includes an nth stage shift register unit S2N electrically connected to the nth row pixel circuit PixelN;

the control signal providing circuit 201 is configured to provide a left start signal STVL for S1N, and provide a first left clock signal CLKL and a second left clock signal CLKBL for the first gate driving circuit G1;

the control signal providing circuit 201 is used to provide a right start signal STVR for S2N and provide a first right clock signal CLKR and a second right clock signal CLKBR for the second gate driving circuit G2.

In the second embodiment of the display device shown in fig. 21, S11 is electrically connected to the carry output signal terminal of S12; s12 are electrically connected to the carry output signal terminal of S11 and the carry output signal terminal of the third stage shift register unit (not shown in fig. 21) included in the first gate driving circuit G1, respectively;

the S1N is also electrically connected with the carry output signal end of the S1N-1;

the carry output signal end of S21 and S22 is electrically connected; s22 are electrically connected to the carry output signal terminal of S21 and the carry output signal terminal of the third stage shift register unit (not shown in fig. 21) included in the second gate driving circuit G2, respectively;

the S2N is also electrically connected with the carry output signal end of the S2N-1.

In the second embodiment of the display device shown in fig. 21, a bilateral bidirectional gate driving scanning manner is adopted, and the first gate driving circuit G1 located on the left side of the display substrate and the second gate driving circuit G2 located on the right side of the display substrate simultaneously provide corresponding gate driving signals for the N rows of pixel circuits.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A shift register unit is characterized by comprising a shift register module and an output module, wherein,

the shift register module is respectively electrically connected with an input signal end, a shift output node, a carry output signal end, a reset end and a first clock signal end, and is used for performing shift register on an input signal provided by the input signal end under the control of a reset signal input by the reset end and a first clock signal input by the first clock signal end so as to generate a carry output signal;

the voltage signal of the shift output node is opposite to the carry output signal;

the output control signal is a voltage signal of the shift output node;

the shift register unit also comprises an output control module;

the output control module is used for controlling the gate drive signal output end to output a first voltage under the control of an enable signal input by an enable end so as to open a corresponding row of grid lines and release residual charges in the pixel circuit;

the output module comprises a NOR gate; a first input end of the NOR gate is electrically connected with the shift output node, a second input end of the NOR gate is electrically connected with a second clock signal end, and an output end of the NOR gate is electrically connected with the gate drive signal output end;

the output control module comprises a pull-up circuit and a control circuit;

the control circuit is used for controlling the NOR gate not to output a second voltage signal under the control of the enable signal;

the NOR gate comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor;

2. The shift register cell of claim 1, wherein the shift register module comprises a first node control circuit, a shift output node control circuit, and a carry output circuit, wherein,

3. The shift register cell of claim 2, wherein the first node control circuit comprises a first inverter;

4. The shift register cell of claim 2, wherein the shift output node control circuit comprises a first tri-state gate, a second tri-state gate, and a reset sub-circuit, wherein,

5. The shift register cell of claim 4, wherein the first tri-state gate comprises a first transistor, a second transistor, a third transistor, and a fourth transistor;

6. The shift register cell of claim 4, wherein the second tri-state gate comprises a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

7. The shift register cell of claim 4, wherein the reset subcircuit includes a reset transistor;

8. The shift register cell of claim 2, wherein the carry output circuit comprises a second inverter;

9. The shift register cell of any one of claims 1-8, further comprising an input control module;

10. The shift register cell of claim 9, wherein the input control module comprises a first transmission gate and a second transmission gate;

11. The shift register cell of claim 1, wherein the pull-up circuit comprises a pull-up transistor;

12. A driving method applied to the shift register unit according to any one of claims 1 to 11, the driving method comprising:

the output control signal is a voltage signal of the shift output node;

the shift register unit also comprises an output control module; the driving method further includes:

in the discharging stage, under the control of an enable signal input by an enable end, the output control module controls the gate driving signal output end to output a first voltage so as to open the corresponding row grid line and release charges remained in the pixel circuit;

the step of generating the gate driving signal by the output module according to the output control signal and the second clock signal comprises: in a display stage, the NOR gate generates a gate drive signal according to the voltage signal of the shift output node and a second clock signal;

the output control module comprises a pull-up circuit and a control circuit; in the discharging stage, the step of controlling the gate driving signal output end to output the first voltage by the output control module under the control of the enable signal input by the enable end comprises:

13. The driving method of claim 12, wherein the shift register module includes a first node control circuit, a shift output node control circuit, and a carry output circuit, and the driving time includes a reset phase and a display phase that are sequentially set;

14. The driving method according to claim 12 or 13, wherein the shift register unit further includes an input control module; the driving method further includes:

15. A gate drive circuit comprising a plurality of stages of the shift register cell of any one of claims 1 to 11.

16. A display device comprising the gate driver circuit according to claim 15.

17. The display device according to claim 16, wherein the display device includes two of the gate driver circuits; the display device further comprises N rows of pixel circuits; n is a positive integer;

18. The display device of claim 17, further comprising a display substrate; the N rows of pixel circuits are arranged on the display substrate;

19. The display device according to claim 16, wherein the display device includes two of the gate driver circuits; the display device further comprises a display substrate and N rows of pixel circuits arranged on the display substrate; n is a positive integer;