TWI245394B - Device including an opto-electronic chip with inner lead bonding and method for manufacturing the same - Google Patents
Device including an opto-electronic chip with inner lead bonding and method for manufacturing the same Download PDFInfo
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- TWI245394B TWI245394B TW093118577A TW93118577A TWI245394B TW I245394 B TWI245394 B TW I245394B TW 093118577 A TW093118577 A TW 093118577A TW 93118577 A TW93118577 A TW 93118577A TW I245394 B TWI245394 B TW I245394B
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- 230000005693 optoelectronics Effects 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title description 5
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 230000005496 eutectics Effects 0.000 claims abstract description 13
- 229910000679 solder Inorganic materials 0.000 claims description 24
- 239000003292 glue Substances 0.000 claims description 18
- 239000004973 liquid crystal related substance Substances 0.000 claims description 11
- 239000011521 glass Substances 0.000 claims description 8
- 230000003287 optical effect Effects 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 230000000295 complement effect Effects 0.000 claims 2
- TVEXGJYMHHTVKP-UHFFFAOYSA-N 6-oxabicyclo[3.2.1]oct-3-en-7-one Chemical compound C1C2C(=O)OC1C=CC2 TVEXGJYMHHTVKP-UHFFFAOYSA-N 0.000 claims 1
- 229930091051 Arenine Natural products 0.000 claims 1
- 235000010627 Phaseolus vulgaris Nutrition 0.000 claims 1
- 244000046052 Phaseolus vulgaris Species 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 210000003108 foot joint Anatomy 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000003466 welding Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004021 metal welding Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Wire Bonding (AREA)
Abstract
Description
1245394 五、發明説明α) 【發明所屬之技術領域】 一插有關於—種晶片之接合構造’特別係有關於 種光電日日片之内弓丨腳接合構造。 【先前技術】 m·習=光電,晶片與基板之電性連接方法，例如覆晶接合 (’lip Chip Bondmg)、打線接合（Wire b〇nding)或利用 ACF(、AnisotropiC Conductive Film，異方性導電膠）等接 合方式，以電性連接該光電晶片之複數個銲墊與該基板之 對，連接墊，其中，覆晶接合為高溫之製程，該光電晶片 於咼溫之接合過程中，較易受到損壞，因此，為考量該光 電晶片之敏感性，一般以低溫製程之電性連接方法較佳，· 例如利用打線接合方式形成之銲線（b〇nding wi re)或利用 ACF方式，電性連接該光電晶片與該基板。 習知其中一種光電晶片係為用以影像投影2LC〇s (Liquid Crystal On Si 1 icon，液晶矽基板）晶片，通常 該LC0S晶片係以打線方式形成之銲線連接至一基板，以達 到低溫接合’防止損傷該LC0S晶片内之光電元件，例如中 華民國專利公告第551 50 9號「減少應力集中之LCOS(液晶 石夕基板）微型顯示器模組」，其係揭示有一種習知Lc〇s晶 片之打線接合構造，請參閱第1圖，該LC0S晶片之打線接讀 合構造1 0 0係包含有'LC0S晶片11〇(梦基板）、一軟性電路 板130及複數個金屬銲線150，該LC0S晶片110係具有一主 動面111及一背面112，該主動面111係包含有一光作動區 113及複數個銲墊1 14，該LC0S晶片1 10係與一具有透明電1245394 V. Description of the invention α) [Technical field to which the invention belongs] A plug-in structure related to a kind of wafer 'is particularly related to an inner bow-to-foot joint structure of a variety of photovoltaic sun-chips. [Prior art] m · Xi = Optoelectronics, a method of electrically connecting a wafer to a substrate, such as flip chip bonding (Wire Chip Bonding), wire bonding (Wire Bonding), or the use of ACF (AnisotropiC Conductive Film, anisotropic Conductive glue) and other bonding methods to electrically connect the plurality of solder pads of the optoelectronic chip with the substrate, the connection pads, where the flip-chip bonding is a high-temperature process, and the optoelectronic chip is relatively cold during the high temperature bonding process. It is easy to be damaged. Therefore, in order to consider the sensitivity of the optoelectronic chip, it is generally better to use an electrical connection method at a low temperature process. For example, using a bonding wire formed by wire bonding or an ACF method, The optoelectronic chip and the substrate are connected in a sexual manner. One of the known photoelectric chips is a 2LC0s (Liquid Crystal On Si 1 icon) wafer for image projection. Usually, the LCOS chip is a bonding wire formed by wire bonding to a substrate to achieve low temperature bonding. 'Prevent damage to the optoelectronic components in the LCOS chip, such as the Republic of China Patent Bulletin No. 551 50 9 "LCOS (Liquid Crystal Stone Substrate) Miniature Display Module Reducing Stress Concentration", which discloses a conventional Lcos chip For the wire bonding structure, please refer to FIG. 1. The wire bonding structure 100 of the LC0S chip includes the 'LC0S chip 110 (Dream substrate), a flexible circuit board 130, and a plurality of metal bonding wires 150. The LC0S chip 110 has an active surface 111 and a back surface 112. The active surface 111 includes a light active region 113 and a plurality of bonding pads 1 14. The LC0S chip 1 10 and a transparent circuit
1245394 五、發明說明（2) —' - 極層121之玻璃基板120結合，一液晶122係形成於該LC〇s 晶片110及該玻璃基板120之間，以密封該光作動區113， 以構成一 LCOS 胞室（Liquid Crystal On Silic〇n ceii)， 该軟性電路板1 3 〇係貼附於一散熱板1 4 〇，該軟性電路板 130係包含有複數個線路13ι及一介電層132，每一線路131 係形成有一連接墊133，該LC0S晶片110之該背面112係以 一黏晶膠1 6 1黏結於該散熱板1 4 0，並且，一導電膠丨6 2連 接至少一銲塊163與該玻璃基板1 20不與該LC0S晶片11〇重 豐之部分透明電極層1 21，該些金屬銲線1 5 0係電性連接該 LC0S晶片11 〇之該些銲墊11 4與該軟性電路板丨3〇之對應連 接塾133，並以一固化膠170密封該些銲墊114、該些連接麵丨 墊1 3 3及該些金屬銲線1 5 〇，以保護該些金屬銲線1 $ 〇，然 而，該固化膠1 7 0固化後，其收縮性會影響該些金屬銲線 150，嚴重則扯裂該些金屬銲線丨50而影響電性連接效果， 或者’該固化膠170之固化硬度不足以提供該些金屬銲線 150適當的保護，而增加該LC0S微型顯示器模組於使用時 損壞之可能性。 【發明内容】 本發明之主要目的係在於提供一種光電晶片之内引腳 接5構造，其係包含有一光電晶片、一可撓性基板及複數丨 個凸塊，該光電晶片係具有複數個形成於一主動面之銲 墊亥可挽性基板係具有複數個内終端，每一内終端係形 成有一結合孔，該些結合孔係對準於該些銲墊，以該些凸 塊透過對應之結合孔而共晶鍵合該些銲塾與對應之内終1245394 V. Description of the invention (2) — '-The glass substrate 120 of the electrode layer 121 is combined, and a liquid crystal 122 is formed between the LC0s wafer 110 and the glass substrate 120 to seal the light actuating region 113 to constitute An LCOS cell (Liquid Crystal On Silicone). The flexible circuit board 130 is attached to a heat sink 1440. The flexible circuit board 130 includes a plurality of lines 13m and a dielectric layer 132. Each circuit 131 is formed with a connection pad 133. The back surface 112 of the LCOS chip 110 is bonded to the heat sink 1 4 0 with a crystal adhesive 1 6 1, and a conductive adhesive 6 2 is connected to at least one solder. The block 163 and the glass substrate 120 are not part of the transparent electrode layer 121 of the LCOS chip 110. The metal bonding wires 150 are electrically connected to the bonding pads 11 of the LCOS chip 11 and Corresponding connection 133 of the flexible circuit board 315, and the bonding pads 114, the connection surfaces 315, and the metal bonding wires 150 are sealed with a curing glue 170 to protect the metals. Welding wire 1 $ 〇 However, after the curing adhesive 170 is cured, its shrinkage will affect these metal welding wires 150. On the other hand, the metal bonding wires are torn 50 and the electrical connection effect is affected, or 'the curing hardness of the curing glue 170 is not enough to provide proper protection of the metal bonding wires 150, and the LC0S micro display module is increased in use. The possibility of damage. [Summary of the Invention] The main purpose of the present invention is to provide an internal pin 5 structure of a photovoltaic chip, which includes a photovoltaic chip, a flexible substrate, and a plurality of bumps. The photovoltaic chip has a plurality of formations. The reversible substrate of the solder pad on an active surface has a plurality of inner terminals, and each inner terminal is formed with a combination hole. The combination holes are aligned with the pads, and the bumps pass through the corresponding ones. Eutectic bonding of these solder joints with corresponding holes
第8頁 1245394 五、發明說明（3) "~ " --------- 端，該可撓性基板係可於不支撐該光電晶片之情況下，而 電性連接该光電晶片，取代習知必須以一散熱板或硬質基、 板支撐該光電晶片之打線製程，另外，以一固化膠密封該 些凸塊及部分之該些内終端，當該固化膠固化收縮後，其 係對該些用以共晶鍵合之凸塊影響較小，因此該光電晶片、 之内引腳接合構造係具有較佳之電性連接可靠度。 . 一本發明之次一目的係在於提供一種光電晶片之内引腳 接合1造，其中複數個凸塊係以低溫超音波植球技術或單 點回銲技術形成，其係透過一可撓性基板之複數個内終蠕 之對應，合孔而共晶鍵合一光電晶片與一可撓性基板，取 ，習知南溫之覆晶製程，該些低溫形成之凸塊係較不會對 4光電晶片造成損壞，因此，該内引腳接合構造係適用於 該光電5片之電性連接，並且，形成該些凸塊於該可撓性 基板之母一内終端之結合孔即可達到電性連接，其電性連 接路徑係較習知打線接合之路徑短。 依據本發明，一種光電晶片之内引腳接合構造係包含 有一光電晶片、一可撓性基板及複數個凸塊，該光電晶片 係具有一主動面，複數個銲墊係形成於該主動面上，該可 挽性基板係具有複數個内終端，每一内終端係形成有一結 合孔’該些結合孔係對準於對應之銲墊，複數個凸塊係透|| 過e亥些結合孔而共晶鍵合該光電晶片之該些銲墊與該可撓 性基板之對應内終端，較佳地，該些凸塊係為打線方式形 成之結線凸塊（stud bump)，並以一固化膠密封該些凸塊 及部分之該些内終端。Page 8 1245394 V. Description of the invention (3) " ~ " At the end, the flexible substrate can be electrically connected to the optoelectronic chip without supporting the optoelectronic chip. The chip replaces the conventional wire bonding process in which the photovoltaic chip must be supported by a heat sink or a hard substrate. In addition, a curing glue is used to seal the bumps and some of the internal terminals. When the curing glue cures and shrinks, It has a small influence on the bumps used for eutectic bonding, so the optoelectronic chip and the inner pin bonding structure have better reliability of electrical connection. A second object of the present invention is to provide a pin bonding process in an optoelectronic chip, in which a plurality of bumps are formed by a low-temperature ultrasonic ball-planting technique or a single-point reflow technique, which is achieved through a flexibility Corresponding to multiple internal final creeps of the substrate, the holes are combined and the eutectic bonds a photovoltaic chip and a flexible substrate. Taken from the South-Chip flip-chip process, these low-temperature bumps are less resistant to 4 optoelectronics. The chip causes damage. Therefore, the internal pin bonding structure is suitable for the electrical connection of the five optoelectronics, and electrical properties can be achieved by forming the bonding holes of the bumps in the female-inner terminal of the flexible substrate. The electrical connection path is shorter than the conventional wire bonding path. According to the present invention, an internal pin bonding structure of a photovoltaic chip includes a photovoltaic chip, a flexible substrate, and a plurality of bumps. The photovoltaic chip has an active surface, and a plurality of solder pads are formed on the active surface. The releasable substrate has a plurality of inner terminals, and each inner terminal is formed with a combination hole. The combination holes are aligned with corresponding solder pads, and a plurality of bumps are penetrated through || The eutectic bonds the solder pads of the optoelectronic chip and the corresponding internal terminals of the flexible substrate. Preferably, the bumps are stud bumps formed by wire bonding, and are cured by a Glue seals the bumps and portions of the inner terminals.
第9頁 1245394 五、發明說明（4) 【實施方式】 參閱所附圖式，本發明將列舉以下之實施例說明。 依本發明之第一具體實施例，請參閱第2及3圖，一種 光電晶片之内引腳接合構造2 〇 〇係主要包含一光電晶片 210、一可撓性基板230及複數個凸塊240，該光電晶片210 係可選自於一影像投影晶片，例如一 L C 0 S ( L i q u i d Crystal On Si 1 icon，液晶矽基板）晶片或一j)LP(Digi tal Light Process i ng數位光學處理）晶片，在本實施例中， 該光電晶片210係為一LC0S晶片，該光電晶片21 0係具有一 主動面211，其係包含有一光作動區212及複數個銲墊 · 213 ’ 一具有透明電極層221之透光片220係結合於該光電 晶片21 0之該主動面2 11，較佳地，該透光片2 2 0係為一玻 璃基板，一液晶222係形成於該光電晶片210與該透光片 220之間，以密封該光作動區212，而構成一LC0S胞室。 請再參閱第2及3圖，該可撓性基板230係可選自於一 軟性電路板（Flexible Printed Circuit，FPC)、一捲帶 承載封裝基板（Tape Carrier Package，TCP)、一薄膜覆 晶封裝基板（Chip-On-Film Package，C0F)與一導線架之 其中之一，在本實施例中，該可撓性基板230係為一軟性 電路板，該可撓性基板2 3 0係包含有複數個線路2 3 1及一介· 電層232，該些線路231係形成於該介電層232之間，每一 線路231係突出於該介電層232而形成有一内終端233，每 一内終端233係形成有一結合孔234，在本實施例中，該些 内終端233係為TCP捲帶之懸空接腳（flying lead)，該些Page 9 1245394 V. Description of the invention (4) [Embodiment] Referring to the attached drawings, the present invention will enumerate the following embodiments. According to a first specific embodiment of the present invention, please refer to FIGS. 2 and 3, a pin bonding structure of an optoelectronic chip 200 series mainly includes an optoelectronic chip 210, a flexible substrate 230, and a plurality of bumps 240. The photoelectric chip 210 may be selected from an image projection chip, such as an LC 0 S (Liquid Crystal On Si 1 icon) or a j) LP (Digital Light Process i ng digital optical processing). In this embodiment, the optoelectronic chip 210 is an LCOS chip, and the optoelectronic chip 210 has an active surface 211, which includes a light actuation region 212 and a plurality of solder pads 213 '-with a transparent electrode The light-transmitting sheet 220 of the layer 221 is coupled to the active surface 2 11 of the photovoltaic chip 21 0. Preferably, the light-transmitting sheet 220 is a glass substrate, and a liquid crystal 222 is formed on the photovoltaic chip 210 and The light-transmitting sheet 220 seals the light-acting area 212 to form an LCOS cell. Please refer to FIGS. 2 and 3 again. The flexible substrate 230 may be selected from a flexible printed circuit (FPC), a tape carrier package (TCP), and a thin-film chip. One of a Chip-On-Film Package (C0F) and a lead frame. In this embodiment, the flexible substrate 230 is a flexible circuit board, and the flexible substrate 230 includes There are a plurality of lines 2 3 1 and a dielectric and electrical layer 232. The lines 231 are formed between the dielectric layers 232. Each line 231 protrudes from the dielectric layer 232 to form an internal terminal 233. The inner terminal 233 is formed with a coupling hole 234. In this embodiment, the inner terminals 233 are flying leads of a TCP tape.
第10頁 1245394 五、發明說明（5) 結合孔234係小於對應之銲墊2 1 3，較佳地，該些結合孔 2 3 4係對準於該光電晶片2 1 〇之對應鲜塾21 3，並且，該些 内終端233之下表面係接觸對應之銲墊213。 請再參閱第2及3圖，該些凸塊240係形成於對應之結 合孔234而共晶鍵合（eutectic bonding)該光電晶片210之 該些銲墊2 1 3與對應之内終端2 3 3，較佳地，該些凸塊2 4 0 係為利用打線方式形成之結線凸塊（s t u d b u m p )，該些凸 塊240係可為金凸塊（g〇i d bump)、鋁凸塊或錫鉛凸塊，透 過該些結合孔2 3 4同時共晶鍵合該光電晶片2 1 〇之該些銲墊 213與對應之内終端233。之後，以一固化膠250密封該些 凸塊240與該可撓性基板230之部份之該些内終端233，以< 構成該光電晶片之内引腳接合構造2〇〇。 依本發明之光電晶片之内引腳接合構造2〇〇之製造方 法係詳細說明於後，請參閱第4A圖，首先係提供有該光電 晶片2 1 0，該光電晶片2 1 〇之該主動面211係結合有該透光 片220 ’該液晶222係形成於該光電晶片21〇與該透光片220 之間，以密封該光作動區212，以構成一LC0S胞室；請再 參閱第4B圖，提供該可撓性基板23〇，較佳地，另執行一 定位該可撓性基板2 3 0之步驟，以使該些内終端2 3 3之該些 結合孔2 3 4對準於該光電晶片2 1 〇之對應銲墊2 1 3，並使該丨 些内終端233之下表面接觸對應之銲墊213 ;請再參閱第4C 圖，以打線方式形成該些凸塊240於對應之結合孔2 34，較 佳地’遠些凸塊2 4 0係利用低溫超音波植球技術形成，其 係將一毛細管狀之銲針1 〇(Capi丨lary)輔以超音波震盪，Page 10 1245394 V. Description of the invention (5) The bonding holes 234 are smaller than the corresponding pads 2 1 3, preferably, the bonding holes 2 3 4 are aligned with the corresponding fresh fins 21 of the photovoltaic chip 2 1 0 3, and the lower surfaces of the inner terminals 233 are in contact with corresponding pads 213. Please refer to FIGS. 2 and 3 again, the bumps 240 are formed in the corresponding bonding holes 234 and eutectic bonding the bonding pads 2 1 3 of the photovoltaic chip 210 and the corresponding inner terminals 2 3 3. Preferably, the bumps 2 40 are studbumps formed by a wire bonding method, and the bumps 240 may be gold bumps, aluminum bumps, or tin. The lead bumps simultaneously eutecticly bond the pads 213 of the photovoltaic chip 21 and the corresponding inner terminals 233 through the bonding holes 2 3 4. Afterwards, the bumps 240 and the inner terminals 233 of the flexible substrate 230 are sealed with a curing glue 250, and the inner pin bonding structure of the photovoltaic chip is formed as 200. The manufacturing method of the pin bonding structure 200 of the photovoltaic chip according to the present invention is described in detail hereinafter. Please refer to FIG. 4A. First, the photovoltaic chip 2 10 is provided. The surface 211 is combined with the light-transmitting sheet 220. The liquid crystal 222 is formed between the photovoltaic chip 21 and the light-transmitting sheet 220 to seal the light-acting region 212 to form an LCOS cell; 4B, the flexible substrate 23 is provided. Preferably, another step of positioning the flexible substrate 2 30 is performed so that the bonding holes 2 3 4 of the inner terminals 2 3 3 are aligned. Corresponding solder pads 2 1 3 on the optoelectronic chip 2 1 0, and the lower surfaces of the inner terminals 233 contact the corresponding solder pads 213; please refer to FIG. 4C again, and form the bumps 240 by wire bonding. Corresponding to the bonding hole 2 34, it is preferable that the 'distant bumps 2 40' are formed by using a low-temperature ultrasonic ball-planting technique, which is supplemented by a capillary-shaped solder pin 10 (Capi 丨 lary) with ultrasonic vibration,
第11頁 1245394 五、發明説明（6) 將該鲜針1 0内銲線之一尖端熔結成塊狀，該低溫超音波植 球技術之溫度係低於2〇〇 °c，該些凸塊240係透過對應之結 合孔234而共晶鍵合該光電晶片21〇之該些銲墊213與對應 之内終端2 3 3 ;請再參閱第2圖，以塗佈方式形成該固化膠 250，以密封該些凸塊240及該可撓性基板230之部份之該 些内終端233，以構成該光電晶片之内引腳接合構造2〇〇。 在上述之光電晶片之内引腳接合構造2〇〇中，該些凸 塊240係以低溫之超音波植球技術形成，因此，該些凸塊 240係較不會對該光電晶片2 1 〇造成損壞，並且，每一凸塊 240係透過該些内終端233之對應結合孔234而共晶接合該儀 光電晶片2 1 0之該些銲墊21 3與該可撓性基板2 3 0之對應内 終端233，即可達到該光電晶片210與該可撓性基板23〇之 電性連接，其電性連接路徑係較習知打線接合之路徑短， 並且’該光電晶片2 1 0之内引腳接合係不需如習知先將該 光電晶片2 1 0黏結於一散熱板或一硬質基板後，才可進行 電性連接之步驟，另外，當該固化膠250固化收縮後，該 固化膠250係對該些用以共晶鍵合之凸塊24〇影響較小，因 此該光電晶片之内引腳接合構造2 〇 〇係具有較佳之電性連 接可靠度。 依本發明之第二具體貫施例，請參閱第5圖，一種光馨 電晶片之内引腳接合構造300係主要包含有一光電晶片 3 1 0、一可撓性基板330及複數個凸塊340，該光電晶片31 0 係可選自於一影像感測晶片與一光發射晶片（如Led (Li‘ght Emitting Diode)，發光二極體晶片）之其中之一，其中該Page 11 1245394 V. Description of the invention (6) The tip of one of the welding wires in the fresh needle 10 is fused into a block. The temperature of the low-temperature ultrasonic ball-planting technology is lower than 200 ° c. The bumps 240 is the eutectic bonding of the bonding pads 213 of the photovoltaic chip 21 and the corresponding inner terminals 2 3 3 through the corresponding bonding holes 234; please refer to FIG. 2 again to form the curing glue 250 by coating, The inner terminals 233 of the bumps 240 and a portion of the flexible substrate 230 are sealed to form an inner pin bonding structure of the photovoltaic chip. In the above-mentioned pin bonding structure 200 of the optoelectronic chip, the bumps 240 are formed by a low-temperature ultrasonic ball implantation technique. Therefore, the bumps 240 are less likely to the optoelectronic chip 2 1 〇 It causes damage, and each of the bumps 240 eutectically bonds the pads 21 3 of the instrument photovoltaic chip 2 10 and the flexible substrate 2 3 0 through the corresponding coupling holes 234 of the inner terminals 233. Corresponding to the internal terminal 233, the electrical connection between the optoelectronic chip 210 and the flexible substrate 23 can be achieved. The electrical connection path is shorter than the conventional wire bonding path, and 'the optoelectronic chip is within 2 10 The pin bonding system does not need to adhere the photovoltaic chip 210 to a heat sink or a hard substrate as before, and then the electrical connection step can be performed. In addition, when the curing adhesive 250 cures and shrinks, the curing adhesive 250 The effect on the bumps 240 for eutectic bonding is small, so the pin bonding structure 200 of the optoelectronic chip has a better reliability of electrical connection. According to a second specific embodiment of the present invention, please refer to FIG. 5. A pin bonding structure 300 of an optical chip mainly includes a photovoltaic chip 3 1 0, a flexible substrate 330, and a plurality of bumps. 340, the photoelectric chip 31 0 may be selected from one of an image sensing chip and a light emitting chip (such as a Led (Li'ght Emitting Diode), a light emitting diode chip), wherein the
第12頁 1245394 ___— 五、發明說明（7) 影像感測晶片係選自於一CM0S(Complenien1:ary Metal Oxide Semiconductor ，互彳甭式金屬氧4匕半導體）晶片與一 CCD(Charge Coupled Device，電荷|馬合裝置）晶片之其中 之一，在本實施例中，該光艰晶片3 1 0係為一CMOS晶片， 該光電晶片310係具有一主動面311，其係包含有一光作動 區3 1 2，複數個銲墊3 1 3係排列於該光作動區3 1 2之外周 邊，一透光片3 2 0係以一黏膠3 2 1結合於該光電晶片31 〇之 該主動面311，形成一氣密空間於該透光片32〇與該光電晶 片310之ό亥主動面311之間’以氣密該光作動區312，並 且，該透光片32 0係不覆蓋該些銲墊313，在本實施例中， 該透光片320係為一玻璃基板。 < 請再參閱第5圖，該可撓性基板3 3 0係包含有複數個線 路331及一介電層332，該些線路331係形成於該介電層332 之間’每一線路331係突出於該介電層332而形成有一内終 端333，每一内終端333係形成有一結合孔334，該些結合 孔334係小於對應之銲墊31 3，較佳地，該些結合孔334係 對準於該光電晶片310之對應銲墊313，且該些内終端333 之下表面係接觸對應之銲墊3丨3，在本實施例中，該可撓 性基板330係為一捲帶承載封裝基板（Tape Carrier Package，TCP) 〇 < 請再參閱第5圖，該些凸塊3 4〇係形成於對應之結合孔 334 ’以共晶鍵合該光電晶片31〇之該些銲墊313與對應之 内終端333，並且，以一固化膠3 5〇密封該些凸塊34〇及該 可挽性基板3 30之部份之該些内終端333，以構成該光電晶1245394 on page 12 ___— 5. Description of the invention (7) The image sensing chip is selected from a CM0S (Complenien1: ary Metal Oxide Semiconductor) chip and a CCD (Charge Coupled Device, Charge | horizontal device) One of the wafers. In this embodiment, the light wafer 3 1 0 is a CMOS wafer, and the photoelectric wafer 310 has an active surface 311, which includes a light active region 3 1 2. A plurality of solder pads 3 1 3 are arranged outside the light active area 3 1 2. A light transmitting sheet 3 2 0 is bonded to the active surface of the photoelectric chip 31 2 with an adhesive 3 2 1. 311, forming an air-tight space between the light-transmitting sheet 32 and the active surface 311 of the photovoltaic chip 310 to air-tighten the light actuating area 312, and the light-transmitting sheet 32 0 does not cover the welding The pad 313, in this embodiment, the transparent sheet 320 is a glass substrate. < Please refer to FIG. 5 again. The flexible substrate 3 3 0 includes a plurality of lines 331 and a dielectric layer 332. The lines 331 are formed between the dielectric layers 332. 'Each line 331 An inner terminal 333 is formed protruding from the dielectric layer 332, and each inner terminal 333 is formed with a combination hole 334. The combination holes 334 are smaller than the corresponding pads 31. Preferably, the combination holes 334 The corresponding solder pads 313 are aligned with the optoelectronic chip 310, and the lower surfaces of the inner terminals 333 are in contact with the corresponding solder pads 3, 3. In this embodiment, the flexible substrate 330 is a tape. Tape Carrier Package (TCP) 〇 < Please refer to FIG. 5 again, the bumps 3 40 are formed in the corresponding bonding holes 334 ′, and the solders of the photovoltaic chip 31 0 are bonded by eutectic bonding. The pad 313 and the corresponding inner terminal 333 are sealed with a curing glue 3 50 and the inner terminals 333 of a part of the susceptible substrate 3 30 to form the photovoltaic crystal.
第13頁 1245394 五、發明說明（8) 片之内引腳接合構造3 〇〇。 該光電晶片之内引腳接合構造3 00之製造方法係說明 於後’凊參閱第6 A圖，首先係提供有該光電晶片3 1 0，該 光電晶片310之該主動面31ι係結合有該透光片32〇 ;請再 參閱第6B圖，提供該可撓性基板33〇，較佳地，另執行一 定位該可撓性基板330之步驟，以使該些内終端333之該些 結合孔334對準於該光電晶片31〇之對應銲墊313，並使該 些内終端333之下表面接觸對應之銲墊313 ;請再參閱第6C 圖’利用打線方式以該銲針1 〇壓銲一鮮線，輔以超音波震 盪將一銲線之一端熔結成塊狀，而形成該些凸塊34 〇，該 些凸塊340係透過對應之結合孔334而共晶鍵合該光電晶片攀 310之該些銲墊3 13與對應之内終端333 ;請再參閱第5圖， 以塗佈方式形成該固化膠350以密封該些凸塊34〇及該可撓 性基板330之部份之該些内終端333，以構成該光電晶片之 内引腳接合構造30 0。 在上述之光電晶片之内引腳接合構造3〇 〇中，該些凸 塊340係低溫形成，因此，該些凸塊34〇係較不會對該光電 晶片310造成損壞，並且，每一凸塊34〇係透過該些内終端 3 3 3之對應結合孔3 3 4而共晶鍵合該光電晶片3 1 〇之該歧鲜 墊313與該可撓性基板33 0之對應内終端333，即可達到今籲 光電晶片310與該可撓性基板330之電性連接，其電性連接 路徑係較習知打線接合之路徑短，並且該光電^片31〇之 内引腳接合係可不需要基板之支撐即可谁# : μ i > I J進仃，另外，當該 固化膠350固化收縮後，該固化膠35 0传斜兮+ m υ 對该些用以共晶接Page 13 1245394 V. Description of the invention (8) In-chip pin bonding structure 3 00. The manufacturing method of the pin bonding structure 3 00 in the optoelectronic chip is described later. Refer to FIG. 6A. First, the optoelectronic chip 3 1 0 is provided, and the active surface 31 i of the optoelectronic chip 310 is combined with the Transparent sheet 32〇; Please refer to FIG. 6B again to provide the flexible substrate 33〇, preferably, perform another step of positioning the flexible substrate 330 so that the inner terminals 333 are combined with each other. The holes 334 are aligned with the corresponding solder pads 313 of the photovoltaic chip 31, and the lower surfaces of the inner terminals 333 contact the corresponding solder pads 313; please refer to FIG. 6C again, using the wire bonding method to press the solder pins 10 A fresh wire is welded, and one end of a welding wire is fused into a block with the aid of ultrasonic vibration to form the bumps 34. The bumps 340 are eutectically bonded to the photovoltaic chip through corresponding bonding holes 334. The pads 3 13 and the corresponding inner terminals 333 of the 310; please refer to FIG. 5 again, and the curing glue 350 is formed by coating to seal the bumps 34 and the flexible substrate 330. The inner terminals 333 constitute the inner pin bonding structure 300 of the photovoltaic chip. In the above-mentioned pin bonding structure 300 of the photovoltaic chip, the bumps 340 are formed at a low temperature. Therefore, the bumps 34 are less likely to cause damage to the photovoltaic chip 310, and each bump The block 34o is the corresponding inner terminal 333 of the flexible substrate 330 and the flexible pad 313 of the optoelectronic wafer 3 1o through eutectic bonding through the corresponding coupling holes 3 3 4 of the inner terminals 3 3 3. That is to say, the electrical connection between the photovoltaic chip 310 and the flexible substrate 330 can be achieved. The electrical connection path is shorter than the conventional wire bonding path, and the pin bonding system within the photovoltaic chip 31 may not be required. The substrate can be supported by anyone #: μ i > IJ enters, in addition, when the curing glue 350 cures and shrinks, the curing glue 35 0 is transmitted obliquely + m υ These are used for eutectic connection
1245394__ 五、發明說明（9) 合之凸塊340影響較小，因此該光電晶片之内引腳接合構 造300係具有較佳之電性連接可靠度。 本發明之保護範圍當視後附之申請專利範圍所界定者 為準，任何熟知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保護範圍。1245394__ V. Description of the invention (9) The influence of the combined bump 340 is small, so the pin bonding structure 300 of the optoelectronic chip has better reliability of electrical connection. The protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .
第15頁 1245394 圖式簡單說明 【圖式簡單說明】 第1 圖·習知LCOS晶片之打線接合構造之截面示意 圖， 第 2 圖：依本發明之第一具體實施例，一種光電晶片 之内引腳接合構造之截面示意圖； 第 3 圖：依本發明之第一具體實施例，該光電晶片之 内引腳接合構造之立體示意圖； 第4 A至4 C圖：依本發明之第一具體實施例，該光電晶片之 内引腳接合構造在製造過程中之截面示意圖； 第 5 圖：依本發明之第二具體實施例，一種光電晶片鲁 之内引腳接合構造之截面示意圖；及 第6A至6C圖：依本發明之第二具體實施例，該光電晶片之 内引腳接合構造在製造過程中之截面示意圖。 元件符號簡單說明： 10 鲜針 1 0 0 L· C 0 S晶片之打線接合構造 110 LCOS 晶片 11 3光作動區 1 2 0玻璃基板 1 3 0軟性電路板 1 3 3連接墊 111主動面 114 銲墊 1 21透明電極層 1 31線路 11 2背面Page 15 1245394 Brief description of the drawings [Simplified description of the drawings] Fig. 1 · A cross-sectional view of a conventional LCOS chip wire bonding structure, Fig. 2: According to a first embodiment of the present invention, an internal lead of a photoelectric chip Sectional schematic diagram of the foot bonding structure; Figure 3: A three-dimensional schematic diagram of the pin bonding structure in the photovoltaic chip according to the first specific embodiment of the present invention; Figures 4 A to 4 C: the first specific implementation of the present invention For example, a schematic cross-sectional view of the inner pin bonding structure of the photovoltaic chip during the manufacturing process; FIG. 5: A cross-sectional schematic view of the inner pin bonding structure of the photovoltaic chip according to the second specific embodiment of the present invention; and FIG. 6A FIG. 6C is a schematic cross-sectional view of the pin bonding structure of the photovoltaic chip during the manufacturing process according to the second embodiment of the present invention. Simple description of the component symbols: 10 fresh pins 1 0 0 L · C 0 S chip wire bonding structure 110 LCOS chip 11 3 light operating area 1 2 0 glass substrate 1 3 0 flexible circuit board 1 3 3 connection pad 111 active surface 114 soldering Pad 1 21 Transparent electrode layer 1 31 Circuit 11 2 Back
122液晶 132介電層 14 0散熱板 150金屬銲線 國 第16頁 1245394 光電晶片之内引腳接合構造 光電晶片 311主動面 鋒墊 圖式簡單說明 1 6 1黏晶膠 170 固化膠 200 光電晶片之内 2 1 0 光電晶片 213 銲墊 220 透光片 230 可撓性基板 2 3 3 内終端 240 凸塊 250 固化膠 300 310 313 320透光片 330 可撓性基板 3 3 3 内終端 340 凸塊 350 固化膠 162導電膠 引腳接合構造 211主動面 221透明電極層 2 3 1線路 2 3 4結合孔 3 21點膠 3 31線路 334結合孔 1 6 3銲塊 2 1 2 光作動區 2 2! 2 液晶 232介電層 3 1 2 光作動區 332介電層122 Liquid crystal 132 Dielectric layer 14 0 Heat sink 150 Metal bonding wire Page 16 1245394 Photonic chip internal pin bonding structure Photoelectric chip 311 Active surface front pad Schematic description 1 6 1 Adhesive film 170 Curing adhesive 200 Photoelectric chip Within 2 1 0 Photoelectric chip 213 Welding pad 220 Transparent sheet 230 Flexible substrate 2 3 3 Inner terminal 240 Bump 250 Curing glue 300 310 313 320 Transparent sheet 330 Flexible substrate 3 3 3 Inner terminal 340 Bump 350 Curing glue 162 Conductive glue pin bonding structure 211 Active surface 221 Transparent electrode layer 2 3 1 Circuit 2 3 4 Bonding hole 3 21 Dispensing 3 31 Circuit 334 bonding hole 1 6 3 Solder block 2 1 2 Light active area 2 2! 2 Liquid crystal 232 dielectric layer 3 1 2 Photoactive region 332 dielectric layer
II
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