TW589744B - Thin film transistor device with body contact - Google Patents

Abstract

A kind of thin film transistor device with body contact is applicable on polysilicon thin film transistor liquid crystal display. The thin film transistor is used to manufacture the body contact region for separating the gate electrode, the source region and the drain region. The threshold voltage of the thin film transistor driving circuit is reduced, so as to thus increase its driving current by exerting body-trigger bias on the body of the thin film transistor through doping the body contact region with the dopant type different from what is used for the source region and the drain region.

Description

589744 V. Description of the invention (1) — "Technical field to which the invention belongs" The present invention relates to a thin film transistor element, and more particularly to a thin film with substrate contact applied to a low temperature polycrystalline silicon thin film transistor liquid crystal display. Transistor element. [Previous technology] Thin film transistor (TFT) is an important element of thin film transistor liquid crystal display (TFT LCD). The technology of thin film transistor is mainly divided into Amorph〇us Si 1 icon and many There are two types of polysilicon (Polysi 1 icon). Amorphous silicon thin film transistors are currently mature and are the mainstream products of liquid crystal displays. Polycrystalline silicon technology requires amorphous silicon to be recrystallized into a polycrystalline silicon structure. Due to process cost and display quality considerations, low-temperature polycrystalline silicon technology is currently the focus of development. Polycrystalline silicon transistors have a hundred times faster electron movement speed than amorphous silicon, and have the advantages of fast daylight display speed, high brightness, and high resolution. In addition, because polycrystalline silicon has a fast electron moving speed, peripheral driving circuits can be integrated on the polycrystalline silicon glass substrate to reduce its weight and achieve lightness and thinness. However, the current process of integrating thin-film transistors and their driving circuits on a glass substrate called Shi Xi's is compared with the use of a complementary metal oxide semiconductor (Complementary Meta and Oxide Semiconductor). It has the disadvantages of higher threshold voltage and lower electron mobility. It can be seen that under the same size, the driving current generated by the thin film transistor is still smaller than that of the complementary metal-oxide semiconductor hybrid device. The transistor liquid crystal display is oriented towards large size and = 744, the description of the invention (2) In the case of the development of resolution, it is necessary to cooperate with it. At the same time, the production of high-efficiency thin-film transistor elements whose road area is limited by the pixel pitch is [Summary of the Invention] How to make a higher-efficiency thin-film transistor to drive a polycrystalline silicon glass substrate 'how to make it within a limited area has become the focus of current research. Increasing the thin-film bias to increase the thickness of the thin-film The insulation system forms a mixed source channel electrode that is in contact with the channel body and is not in contact with the gate region. Different from the insulation, in order to solve the problems of the conventional technology, the driving current of the film transistor. The film transistor uses the substrate of the thin film transistor to drive the current. To achieve the above purpose, the present crystal device includes: The layer (its material can be oxidized stone) is composed of the surface, region and a drain region of the insulating substrate, and is connected to the channel region, part of the source region and the channel formed in the polycrystalline layer respectively. The region has a connecting insulating substrate and the surface of the region has a through-electrode contact. This substrate is connected to impurities of the type to provide a base substrate. For the purpose and structure of the present invention, the present invention provides a substrate with a substrate. Add a body-trigger to reduce the threshold voltage of the thin-film transistor _ polycrystalline silicon layer with substrate contact, polycrystalline chip layer, an insulating substrate, and a gate electrode, the polycrystalline silicon layer system The source region and the drain region; the insulating layer covers the surface of the electrode region; the contact layer of the base layer of the insulating layer on the oxide layer of the region, The contact area needs to be doped and source-source triggered (body-tr, a channel area, doped with a polysilicon layer, and a gate side. Among them, the contact area, its base, and contact layer polar area and non-polar igger) Bias fabrication features and their functions have further

589744 V. Description of the invention (3) I understand that the detailed description with the illustration is as follows: [Embodiment]

First, an actual circuit is used to explain the operation of the present invention. Please refer to FIG. L, which is a schematic diagram of a thin film transistor driving circuit of the present invention. It connects the P-type and N-type thin film transistor elements (Mp and Mη) with substrate contact with the load valley (CL), power supply (vcc), input terminal (In) and output terminal (Out). When the input terminal (I n) receives a low-to-high signal, the bias voltage generated by the substrate trigger circuit is applied to the P-type and N-type thin-film transistor components; meanwhile, the critical voltage of the N-type thin-film transistor is also applied. The threshold voltage of the p-type thin film transistor decreases. Therefore, the driving current of the N-type thin film transistor is increased and the driving current of the p-type thin film transistor is decreased, thereby reducing the output falling time. On the contrary, when the input terminal (I η) receives a high-to-low signal, the bias voltage generated by the substrate trigger circuit is applied to the p-type and N-type thin-film transistor elements; at the same time, the P-type thin film is electrically charged. The threshold voltage of the crystal decreases, and the threshold voltage of the N-type thin film transistor increases. Therefore, the driving current of the p-type thin film transistor is increased and the driving current of the N-type thin film transistor is decreased, thereby reducing the rising time at the output terminal.

As mentioned above, due to the influence of the body-trigger bias, the driving current of the P-type and N-type thin-film transistor elements during the reaction can be increased to reduce the rise and fall times. It is shown that the present invention can reduce the size of the thin film transistor without affecting the reaction speed; thereby, more driving circuits and components can be manufactured in a limited area to reduce costs and have good reliability.

Page 5. Description of the invention (4) Please refer to Fig. 2 and Fig. 3, 俯视 2FI inflammation I a top view of the structure; Fig. 3 is two copies; the schematic diagram of the first embodiment, the section line is the 12th The structure of the embodiment is a n-type thin film electric line segment. The first-substrate 20, polycrystalline silicon layer, and oxygen of the present invention: It is composed of an insulation established on the-substrate 10 in the order of nI% R n and 0, and a gate electrode 50; a team electrode 50 and a silicon oxide layer 4 () Stacked from top to bottom. T, two: Guanghe insulating substrate 20 source region 21 and a drain region 2: said: the layer system is composed of-channel region 23,-mixed with suitable H,, source region 21 and drain region 22 The system is doped with £ 2 = connected to the channel region 23 respectively; and the other ends of the channel region 23 are respectively provided with a substrate contact region 3 of Chinese and rhenium. Its substrate: contact layer 31, contact layer 31 of substrate 20 and silicon oxide layer 40, and two === broken contact through the oxide. This substrate contact area 3. System replacement; not connected to f electrode 50 Connect rh〇H_,.,, And heterodimorphic to provide the matrix to trigger the yr lgger) bias to the insulating matrix 20. The interlayer stacking situation is shown in Figure 3 = = 2. The surface is covered by the oxide system Oxidation in the V-pass channel region 23: of .: formed on the insulating substrate 2 of the layer 2. and oxidation; layer two; two = the channel has a contact region Q Π ^ ^ ^ a ^ ^ W, The substrate contact area has a contact layer 31 through the silicon oxide layer 40, and the contact layer is in contact with the gate electrode 50. This substrate contact area 30a 21 and the drain region 22 are trivalent in different types. The acceptor to provide substrate contact: (body-trigger) biased to the insulating substrate 20. The source region also has a contact layer 31 penetrating the silicon oxide layer 40. & 22 589744 V. Description of the invention (5) Among them, the contact region of the substrate can be established at various positions in the channel region under the premise that the contact layer is not in contact with the blood gate electrode. Even within the electrode The exit-perforation is used to establish the substrate contact area and its connection in the perforation. As shown in FIG. 4, it is the structure of the second embodiment of the present invention. Top view = thinking. This thin film transistor element with substrate contact is An octagonal perforation 5 which exposes the silicon oxide layer 40 is excavated within 50 volts of the gate electrode, and a base contact area 30 and its contact layer 3 are formed in the octagonal perforation 51, namely the gate electrode. = The area surrounds the substrate contact area 30 and its contact layer 31. Further advance: Step by step to clarify its configuration, 'refer to item 5, which is a schematic cross-sectional view of the structure of the second embodiment of the present invention', and its section line is As shown in FIG. 4, the eight-line material Γ can be seen from the arrangement of the gate electrode 50, the substrate contact area 30, and the contact layer 31. In addition, please refer to FIG. 6, which is a second embodiment of the present invention. ::: A schematic cross-sectional view, whose cross-section is the line B, -B in Figure 4. 2: No: The gate electrode 50, the substrate contact area 30, and the phase M of the contact 31 are also channels of the polycrystalline silicon layer. Region 23, source region 21, and drain region 22. The quotient can also be placed on the edge of the gate electrode. Extending above the channel area =: Establishing a substrate contact area and its stem I Η in the area hollowed out by the groove, which is the structure of the third embodiment of the present invention; iT50 forms a Η-shaped area, The source region 21 and the channel region 23 below the pole electrode of the eight-piece Jieshe Valley hybrid five-shell yoke are generated by it. Then, by the section " Ben Mingdi For stacking and configuration of the embodiment, please refer to

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V. Description of the invention (6) Figure 8 is a schematic cross-sectional view of the structure of the third embodiment of the present invention. The top line is the A, -A line segment in Figure 7. It shows the relative positions and configurations of the second per-pole 50, the base contact region 30, the contact layer 31, and the gate electrode source region 21 and the drain region 22, respectively. That is, the channel region 23, wherein the source contact region is known from the above embodiment, and the doped region through the base contact region and the electrode region are adjacent to the body-trigger bias. Moreover, different impurities are used to provide one of the substrate contact with aluminum. The electrode gate of the above two embodiments of the present invention can be made of chromium, and the ground method can also be implemented on a P-type TFT solar panel to increase Its driving current. The i 1M power is based on the limitation of the Tailu n0 # 1 target example as described above, but it is not intended to be used by anyone who is familiar with related technologies, and can make some changes without departing from the present invention. ^ 4 The fence must be defined by the scope of the patent application attached to this specification

589744 Brief description of the drawings. Fig. 1 is a schematic layout of a thin film transistor driving circuit according to the present invention. Fig. 2 is a schematic top view of the structure of the first embodiment of the present invention. Fig. 3 is a schematic cross-sectional view of the structure of the first embodiment of the present invention. Figure 4 is a schematic plan view of the structure of the second embodiment of the present invention; Figure 5 is a schematic cross-sectional view of the structure of the second embodiment of the present invention; Figure 6 is a schematic cross-sectional view of the structure of the second embodiment of the present invention; FIG. 8 is a schematic plan view of the structure of the third embodiment of the present invention; and FIG. 8 is a schematic cross-sectional view of the structure of the third embodiment of the present invention. [Illustration of Symbols] 10 substrate 20 insulating substrate 21 source region 22 drain region 23 channel region 30 substrate contact region 31 contact layer 40 silicon oxide layer 5 0 gate electrode 51 octagonal perforation 52 groove

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Claims (1)

589744 Application Patent Scope 1 · A thin film electro-crystalline hetero element with substrate contact, which is composed of an insulating substrate, a polycrystalline silicon layer, an insulating layer and a gate electrode. The polycrystalline silicon layer system includes a channel region, A source region and a drain region. The second aspect is that the source region and the drain region are doped with an appropriate first impurity and connected to the channel region, respectively. The channel region has a connection between the insulating substrate and A substrate contact region of the insulating layer, the surface of the substrate contact region has a contact layer penetrating the insulating layer, and it is seen that the contact layer is not in contact with the gate electrode, the substrate contact region needs to be doped and the source electrode A second impurity having a different valence from the drain region and the drain region is provided to provide a substrate trigger (body—rigger) bias to the insulating substrate. 2. The thin film electro-crystalline TL device with substrate contact as described in item 丨 of the patent application, wherein when the first impurity is a pentavalent donor, the second impurity is a trivalent acceptor. 3. The thin film electro-crystalline element with substrate contact as described in item 1 of the patent claim, wherein when the first impurity is a trivalent acceptor, the second impurity is a pentavalent donor. # 4. The thin film transistor element with substrate contact as described in item 丨 of the scope of the patent application, wherein the edge of the inter electrode is formed into a groove extending to the channel area 2 and hollowed out by the groove The area establishes the base contact area and the contact layer. 5 · As described in item 1 of the scope of the patent application, ^ ^ Φ, one of the groups of thin film electric crystal parts with a substrate contact on the side, the electrode material of the electrode, and the search of a μ #. τ 卄 is selected from the group consisting of chromium and aluminum 6 · —a thin-film electrical component with a substrate contact $ 11 pages 589744 VI. Patent application scope layer, an insulating layer and a 卩 卩 4 right one, If 1¾, one, and E gate electrode, the multiple L k ° ° / original electrode region and one drain electrode region The first and second polar regions are mixed with the first impurity of the drain region. The channel region has a contact region connecting the insulating substrate to the substrate. The surface of the substrate contact region has a contact layer. The substrate contact area and an internal area surrounded by the gate electrode above the gate electrode, and the gate electrode contacts' the substrate contact area needs to be doped and different in valence of the electrode area. An impurity is provided to provide a substrate (igger) biased to the insulating substrate. The thin film transistor having a substrate contact as described in item 6 and a polycrystalline spar spar slab layer includes the following features: the source is connected to the insulation layer through the insulation layer contact layer to form a contact layer; Not related to the source region and the non-triggering (body-tr 7 · If the patent application 3 element 'where the-impurity is-donor time':-a mass system is a trivalent acceptor. Edition and Diyiza 8. The body element as described in item 6 of the scope of patent application, wherein the Λ Λ chaotic thin film transistor with substrate contact m is a divalent acceptor, and the second miscellaneous It is a pentavalent donor. "The edge of the electrode with a base electrode as described in the sixth item of the range is formed to extend to the contact area of the channel area; and 2 layers are established in the area hollowed by the groove to establish the One of the matrix groups: the electrode gate material is selected from the group consisting of chromium and aluminum Page 12