200418187 五、發明說明（1) 【發明所屬之技術領域】 本發明是關於一種薄膜電晶體元件，特別是關於一種 應用於低溫多晶石夕薄膜電晶體液晶顯示器的具有基體接觸 之薄膜電晶體元件。 【先前技術】 薄膜電晶體（Thin Film Transistor，TFT)為薄膜電 晶體液晶顯示器（TFT LCD)的重要元件，薄膜電晶體的技 術主要分為非晶石夕（Amorphous S i 1 i con )與多晶石夕 (Polys i 1 icon)二種，非晶矽薄膜電晶體目前技術成熟， 為液晶顯示器的主流產品。而多晶矽技術則需使非晶矽經 再結晶轉化成多晶矽結構，由於製程成本及顯示品質上的 考量，其中又以低溫多晶矽技術為目前的發展重點。多晶 石夕電晶體的電子移動速度較非晶矽提高百倍，具有顯示晝 面反映速度快、高亮度、及高解析度等優點。此外，由於 多晶矽的電子移動速度快，因此可將週邊驅動電路整合於 多晶石夕之玻璃基板上，以減輕其重量，達到輕薄化的要 求。 然而，目前將薄膜電晶體及其驅動電路整合製作於多 晶石夕之玻璃基板的製程，相較於利用互補金氧半導體 (C 〇 m p 1 e m e n t a r y M e t a 1 - 0 X i d e S e m i c 〇 n d u c t 〇 r，c Μ 0 S )技 術製作之驅動電路，其具有臨界電壓較高以及電子遷移率 ^低的缺點。由此可知，在相同尺寸大小的情況下，薄膜 電晶體元件所產生的驅動電流仍小於互補式金氧半導體整 合元件。而且，在薄膜電晶體液晶顯示器朝向大尺寸與高 200418187 五、發明說明（2) 解析度發展的情況下，需要更高效能的薄膜電晶體驅動電 路來加以配合。同時，製作於多晶石夕之玻璃基板的驅動電 路面積需受限於像素的間距，要如何在有限的面積内製作 向效能的薄膜電晶體元件即成為目前的研究重點。 【發明内容】 為解決習知技術的問題’即在有限的驅動電路面積内 增加薄膜電晶體之驅動電流。本發明提供一種具有基體接 觸之薄膜電晶體元件，利用施加基體觸發（body-trigger) 偏壓於薄膜電晶體的基體，來降低薄膜電晶體的臨界電壓 以增加其驅動電流。 為了達到上述目的，本發明所揭露之具有基體接觸之 薄膜電晶體元件，其包含有：一絕緣基體、一多晶矽層、 〜絕緣層（其材質可為氧化矽）以及一閘極電極；多晶矽層 係形成於此絕緣基體的表面，此多晶矽層係由一通道區、 〜源極區及一没極區所組成，源極區與沒極區係摻雜有適 田之雜質且分別連接於通道區；絕緣層係覆蓋於多晶石夕層 史通道區、部分之源極區和；:及極區之表面；以及，一閘極 重極係形成於多晶矽層之通道區的氧化矽層上方。其中， 2通道區具有連接絕緣基體與絕緣層之基體接觸區，其基 •接觸區表面係具有貫穿絕緣層之接觸層，並且，接觸層 ^與閘極電極接觸。此基體接觸區需摻雜和源極區與汲極 區不同型態之雜質，以提供基體觸發（body-trigger)偏壓 於絕緣基體。 為使對本發明的目的、構造特徵及其功能有進一步的200418187 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a thin film transistor element, and more particularly, to a thin film transistor element with substrate contact applied to a low temperature polycrystalline silicon thin film transistor liquid crystal display. . [Previous technology] Thin film transistor (TFT) is an important element of thin film transistor liquid crystal display (TFT LCD). The technology of thin film transistor is mainly divided into Amorphous S i 1 i con and many There are two types of polycrystalline silicon (Polys i 1 icon). Amorphous silicon thin film transistors are currently mature and are the mainstream products of liquid crystal displays. Polycrystalline silicon technology requires amorphous silicon to be recrystallized into a polycrystalline silicon structure. Due to process cost and display quality considerations, low-temperature polycrystalline silicon technology is currently the focus of development. The polycrystalline stone evening electron has a hundred times faster electron moving speed than the amorphous silicon, and has the advantages of fast display, high brightness, and high resolution. In addition, since polycrystalline silicon has a fast electron moving speed, peripheral driving circuits can be integrated on the polycrystalline glass substrate to reduce its weight and achieve thinner and lighter requirements. However, the current process of integrating thin-film transistors and their driving circuits on polycrystalline glass substrates is currently compared to the use of complementary metal-oxide semiconductors (C 〇mp 1 ementary M eta 1-0 X ide Semi 〇nduct 〇). r, c M 0 S) technology has the disadvantages of higher threshold voltage and lower electron mobility. It can be seen that the driving current generated by the thin film transistor is still smaller than that of the complementary metal-oxide semiconductor integrated device under the same size. In addition, as thin film transistor liquid crystal displays are oriented toward large size and high 200418187 V. Invention Description (2) With the development of resolution, higher efficiency thin film transistor driving circuits are needed to cooperate. At the same time, the driving circuit area of the glass substrate made of polycrystalline stone needs to be limited by the pixel pitch. How to make a thin film transistor with high efficiency in a limited area has become the current research focus. [Summary of the Invention] To solve the problem of the conventional technology, that is, to increase the driving current of the thin film transistor in a limited driving circuit area. The present invention provides a thin film transistor element having a substrate contact, and a body-trigger bias is applied to the substrate of the thin film transistor to reduce the threshold voltage of the thin film transistor to increase its driving current. In order to achieve the above object, the thin film transistor device with substrate contact disclosed in the present invention includes: an insulating substrate, a polycrystalline silicon layer, an insulating layer (which may be made of silicon oxide), and a gate electrode; the polycrystalline silicon layer The polycrystalline silicon layer is formed on the surface of the insulating substrate. The polycrystalline silicon layer is composed of a channel region, a source region, and an electrodeless region. The source and electrodeless regions are doped with suitable impurities and connected to the channel. The insulating layer covers the channel area of the polycrystalline silicon layer, part of the source region, and the surface of the polar region; and a gate heavy electrode system is formed over the silicon oxide layer in the channel region of the polycrystalline silicon layer. . Among them, the 2-channel region has a substrate contact region connecting the insulating substrate and the insulating layer. The surface of the base contact region has a contact layer penetrating the insulating layer, and the contact layer ^ is in contact with the gate electrode. This substrate contact region needs to be doped and different types of impurities in the source and drain regions to provide a body-trigger bias to the insulating substrate. In order to further the purpose, structural features and functions of the present invention
200418187 五、發明說明（3) 了解，茲配合圖示詳細說明如下： 【實施方式】 首先以貫際電路來說明本發明之作用情形，請表 — 1圖，其為本發明之薄膜電晶體驅動電路示意圖。%^ 弟 有基體接觸之P型與N型薄膜電晶體元件（Mp和如）盥：恭、 f⑴:電源供應⑽）、輸入端（ln)和輸出端（0^) = 艏ί雷當其輸入端（ln)係接收一由低至高的訊號時，基體 元；:：1產生之偏壓係分別施加於p型與N型薄膜電曰:曰體 ;;晶電晶體的臨界電壓下降心 ”型薄膜電晶體的驅動電流下降，而減,ί 出&的下降時間（falUng七置）。 而减）輪 體觸發電路^輪入^ ( 1 11 )係接收一由高至低的訊號時，基 體元件；同=產生之偏壓係分別施加於P型與N型薄膜電晶 薄膜電晶體:則使P型薄膜電晶體的臨界電壓下降，N型 驅動電流上升臨界電+壓上升。因此，使P型薄膜電晶體的 輪出端的上和N型薄膜電晶體的驅動電流下降，而減少 綜化升時間（r isin§ time)。 所 響，可以增知，由於基體觸發（body-trigger)偏壓的影 流進而減少P型與N型薄膜電晶體元件於反應時的驅動電 速度的前提卞升與下降時間。顯示本發明可在不影響反應 的面積内製，減少薄膜電晶體的尺寸大小；藉此在有限 良好之可靠度更多的驅動電路與元件，以降低成本且具有 五、發明說明（4) 请參考第2圖與第，锋 結構俯視示意圖；第3圖圖為本發明第一實施例的 面示意®，其剖面線為第2 $日月第一實施例的結構之剖 實施例係為一N型薄膜為電弟曰^中=-A線段。本發明第-基體20、多晶石夕層、氧曰由建立於一基板10之絕緣 依次為閑極電極5。、； ：：以娜^極50所組成； 由上而下堆疊而成。：中Γ曰〇、多晶嫩絕緣基體2〇 源極區21及一汲極區22:』曰曰“夕層係由-通道區23、-^ ^ ^ ^ ^ 陆 Ζ所、、且成，源極區2 1與汲極區2 2係摻 施體且分別連接於通道區23;以及，通道 之芙體接觸5 糸分別具有連接絕緣基體20與氧化石夕層40 其基體接觸區3。表面係具有貫穿氧化石夕 曰 觸層31 ’並且，此接觸層31未與閘極電極50接 觸。此基體接觸區30係摻雜三價受體，以提供基體觸發 (body trigger)偏壓於絕緣基體2〇。 其貝際層豎情形係於第3圖中所示，多晶矽層係形成 於，絕緣基體2〇的表面，氧化矽層4〇係覆蓋於多晶矽層通 逗區23的表面；以及，一閘極電極50係形成於多晶矽層之 通逗區23的氧化矽層4〇上方。其中，於通道區23具有連接 絕緣基體20與氧化矽層4〇之基體接觸區3〇，其基體接觸區 30表面係具有貫穿氧化矽層4〇之接觸層31，並且，接觸層 31未與閘極電極50接觸。此基體接觸區3〇需摻雜和源極區 2 1與没極區2 2不同型態之三價受體，以提供基體觸發 (body-trigger)偏壓於絕緣基體2〇。源極區21與汲極區u 亦具有貝牙氧化石夕層4〇之接觸層31。200418187 V. Description of the invention (3) It is understood that the detailed description with the illustrations is as follows: [Embodiment] First, the function of the present invention will be described with an intermediary circuit. Please refer to Table -1, which is the thin film transistor driver of the present invention. Circuit diagram. % ^ P-type and N-type thin film transistor elements (Mp and R) with substrate contact: Christine, f⑴: power supply⑽), input terminal (ln) and output terminal (0 ^) = 艏 ί 雷 当 其When the input terminal (ln) receives a low-to-high signal, the elementary element: :: 1 is applied to the bias voltages applied to the p-type and N-type thin films. The driving current of the thin film transistor decreases, and the falling time (falUng is set) is reduced. The wheel trigger circuit ^ wheel-in ^ (1 11) receives a signal from high to low At the same time, the base element; the same bias voltage is applied to the P-type and N-type thin-film transistor thin-film transistor: the threshold voltage of the P-type thin-film transistor will be reduced, and the N-type driving current will increase and the critical voltage + voltage will increase. Therefore, the driving current of the upper end of the P-type thin-film transistor and the driving current of the N-type thin-film transistor are reduced, and the integrated rise time (r isin§ time) is reduced. Therefore, it can be known that the body- trigger) Biased video flow to reduce the driving electric speed of P-type and N-type thin film transistor elements during reaction Premise rise and fall time. It shows that the present invention can be manufactured in an area that does not affect the reaction, reducing the size of the thin film transistor; thereby, there are more drive circuits and components with limited good reliability to reduce costs and have five Explanation of the invention (4) Please refer to Figure 2 and Figure 2. Top schematic diagram of the front structure; Figure 3 is a schematic diagram of the first embodiment of the present invention, and its section line is the structure of the second embodiment The sectional example is an N-type thin film that is an electric wire, and the medium is equal to the -A line segment. The -substrate 20, the polycrystalline layer, and the oxygen layer of the present invention are sequentially formed as insulation electrodes 5 on the substrate 10 . ::: It is composed of Na 50 poles; It is stacked from top to bottom .: Middle Γ is 0, polycrystalline insulation substrate 20 source region 21 and a drain region 22: "said" eve The layer system is composed of -channel region 23,-^ ^ ^ ^ ^ LuZ, and the source region 21 and the drain region 2 2 are doped donors and are connected to the channel region 23 respectively; The body contact 5 具有 has a substrate contact region 3 connecting the insulating substrate 20 and the oxidized oxide layer 40, respectively. The surface is provided with a contact layer 31 'through the oxidized stone, and this contact layer 31 is not in contact with the gate electrode 50. The substrate contact region 30 is doped with a trivalent acceptor to provide a body trigger bias to the insulating substrate 20. The vertical state of the interfacial layer is shown in FIG. 3, a polycrystalline silicon layer is formed on the surface of the insulating substrate 20, and a silicon oxide layer 40 covers the surface of the polycrystalline silicon layer pass-through region 23; and a gate The electrode 50 is formed on the silicon oxide layer 40 of the comma region 23 of the polycrystalline silicon layer. Among them, the channel region 23 has a substrate contact region 30 connecting the insulating substrate 20 and the silicon oxide layer 40, and the surface of the substrate contact region 30 has a contact layer 31 penetrating the silicon oxide layer 40, and the contact layer 31 is not in contact with the silicon oxide layer 40. The gate electrode 50 is in contact. The substrate contact region 30 needs to be doped and a trivalent acceptor of a different type from the source region 21 and the non-electrode region 22 to provide a body-trigger bias to the insulating substrate 20. The source region 21 and the drain region u also have a contact layer 31 of a bayonet oxide layer 40.
第7頁 200418187 五、發明說明（5) % 其中’此基體接觸區可在其上方的接觸層在不與閘極 電極接觸的W提之下，建立於通道區的各個位置。甚或於 閘極電極内挖出一穿孔以於穿孔内建立基體接觸區及其接 觸層’如第4圖所示，其為本發明第二實施例之結構俯視 不意圖。此具有基體接觸之薄膜電晶體元件係於其閘極電 極50之内挖出露出氧化矽層4〇的八邊型穿孔51，並且，於 此八邊型穿孔51内建立基體接觸區3〇及其接觸層31，即閘 極，極50區域係環繞於此基體接觸區30及其接觸層31。再 例置i請參考第5圖’其為本發明第二實施 段。由此可知不思、圖，其剖面線為第4圖中之A，-A線 相對位置。另=極電極50、基體接觸區30及其接觸層31的 的結構之剖面一、立明苓考第6圖，其為本發明第二實施例 除了表示出Η 圖，其剖面線為第4圖中之Β，—Β線段。 對位置，亦顯:=極50、基體接觸區30及其接觸層31的相 22的配置關係^夕晶矽層之通道區23、源極區21及汲極區 此外，亦 之適當凹槽7 :於間極電極的邊緣形成延伸至通道區上方 接觸層，如第=槽所掏工之區域建立基體接觸區及其 視示意圖；^間極發明第三實施例之結構俯 延伸至通道區2;::極5〇L成Η形區域，並於其所產生的 體接觸區及龙接 之凹s 2建立數個摻雜三價受體之基 22則分別連接於此；極；施體的源極區2!與… 圖來說明本發明第；;IS的下再藉由剖面 且汉配置情形，請參考第 200418187Page 7 200418187 V. Description of the invention (5)% ’The contact area of this substrate can be established at various locations in the channel area under the contact layer that does not contact the gate electrode. Even a hole is dug out in the gate electrode to establish a substrate contact area and its contact layer 'in the hole as shown in Fig. 4, which is a plan view of the structure of the second embodiment of the present invention. The thin film transistor element with substrate contact is excavated within its gate electrode 50 to expose an octagonal perforation 51 exposing a silicon oxide layer 40, and a substrate contact area 30 is established in the octagonal perforation 51 and The contact layer 31, that is, the gate electrode, and the electrode 50 region surround the substrate contact region 30 and the contact layer 31 thereof. For another example, please refer to FIG. 5 ', which is the second embodiment of the present invention. It can be seen from this figure that the section line is the relative position of line A, -A in Figure 4. Another = cross section of the structure of the electrode 50, the base contact region 30, and the contact layer 31. FIG. 6 is a diagram of the second embodiment of the present invention. In addition to the diagram shown in FIG. B, -B line segment in the figure. For the position, it is also shown: = the arrangement relationship of the pole 50, the base contact region 30 and the phase 22 of the contact layer 31 ^ the channel region 23, the source region 21, and the drain region of the silicon layer. In addition, it is also an appropriate groove 7: A contact layer is formed on the edge of the interelectrode to extend above the channel area, such as the area where the groove is cut to establish a base contact area and a schematic view thereof; the structure of the third embodiment of the interelectrode extends downward to the channel area 2; :: pole 50L into a Η-shaped region, and several body-doped trivalent acceptor bases 22 are established on the body contact area and the dragon's concavity s 2 generated therefrom, respectively; poles; The source region 2 of the body and the diagrams to illustrate the invention; the lower part of the IS is further configured by a cross section and a Han, please refer to the 200418187
五、發明說明（6) 8圖，其為本發明第三實施例的結構 — 面線為第7圖中之A，-A線段。其顯示第示意圖，其剖 極50、基體接觸區30、接觸層31、夕日—M施例之閘極電 源極區2 1及汲極區2 2的相對位置及配置$之通道區2 3、 其中，由上述實施例得知湄 觸區，且藉^基體接觸區所摻=區與波極區係鄰接於接 發（body-trigger)偏壓。而且^ +不同雜質來提供基體觸 與鋁其中之一製成，以上所、，f，本發明之電極閘極可由鉻 晶體上，以增加其驅動電流=之方法亦可實施在P型TFT電 雖然本發明之較佳實施泰 以限定本發明，任何熟習相如上所述 '然其並非用 精神和範圍内，當可作些許P支蟄者，在不脫離本發明之 專利保護範圍須視本說明蚩^更動與潤飾，因此本發明之 為準。 曰所附之申請專利範圍所界定者 200418187 圖式簡單說明 第1圖為本發明之薄膜電晶體驅動電路佈局示意圖； 第2圖為本發明第一實施例的結構俯視示意圖； 第3圖為本發明第一實施例的結構之剖面示意圖； 第4圖為本發明第二實施例之結構俯視示意圖； 第5圖為本發明第二實施例的結構之剖面示意圖； 第6圖為本發明第二實施例的結構之剖面示意圖； 第7圖為本發明第三實施例之結構俯視示意圖；及 第8圖為本發明第三實施例的結構之剖面示意圖。 【圖 式符號 說 明 ] 10 基 板 20 絕 緣 基 體 21 源 極 區 22 汲 極 區 23 通 道 區 30 基 體 接 觸區 31 接 觸 層 40 氧 化 矽 層 50 閘 極 電 極 51 八 邊 型 穿孔 52 凹 槽V. Description of the invention (6) Figure 8 shows the structure of the third embodiment of the present invention-the face line is the A, -A line segment in Figure 7. It shows the first schematic diagram, the relative positions of the cross section 50, the substrate contact area 30, the contact layer 31, and the evening-M embodiment of the gate power source electrode area 21 and the drain electrode area 2 2 and the channel area 23 configured with $ 3. Among them, according to the above embodiments, the Mae contact region is known, and the region doped with the base contact region and the polar region are adjacent to the body-trigger bias. And ^ + different impurities to provide one of the substrate contact with aluminum, the above, f, the electrode gate of the present invention can be made of chromium crystal to increase its driving current = method can also be implemented in P-type TFT Although the best practice of the present invention is to limit the present invention, any familiarity is as described above, but it is not within the spirit and scope. When it can be used as a supporter, it is necessary to consider this without departing from the scope of patent protection of the present invention. It is explained that the modification and retouching are based on the present invention. The attached patent application is defined by the scope of the patent application. 200418187 Brief description of the diagram. Figure 1 is a schematic layout of the thin film transistor driving circuit of the present invention; Figure 2 is a schematic top view of the structure of the first embodiment of the present invention; A schematic sectional view of the structure of the first embodiment of the invention; FIG. 4 is a schematic plan view of the structure of the second embodiment of the invention; FIG. 5 is a schematic sectional view of the structure of the second embodiment of the invention; A schematic sectional view of the structure of the embodiment; FIG. 7 is a schematic plan view of the structure of the third embodiment of the present invention; and FIG. 8 is a schematic sectional view of the structure of the third embodiment of the present invention. [Illustration of Symbols] 10 base plate 20 insulated base body 21 source area 22 drain area 23 channel area 30 base contact area 31 contact layer 40 silicon oxide layer 50 gate electrode 51 octagonal perforation 52 recessed groove
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