564543 五、發明說明564543 V. Description of the invention
【發明領域】 本發明係有關一種半導體 關於一種利用銅的材質，在元 【發明背景】 在半導體製程中，需靠金 )各個電晶體，以發揮半導體 元件以來，晶片製造商就將艇 電阻值很小、電路圖案的沈積 導體的製程進行深次微米後， 也相對的變得很細，另一方面 求之下，鋁材質的導線便無法 如何減少連線的電阻是非 ，消耗的電力會較小、RC延遲 也會較快，因此有銅導線的出 :雖然銅比鋁的電阻值低，但 造成元件因為石夕基底的銅污染 線無法用蝕刻方來形成導線的 次微米領域後，有人發展出利 copper interconnection)的 材料做為介電層，再利用化學 mechanical polishing, CMP 金屬層。 元件的製造方法，特別是有 件間形成連接導線的方法。 屬線連接（interconnection 裝置的功能·，而自有半導體 當成主要的導線材料，因其 和钱刻均十分容易，但當半 元件積集度愈來愈高，導線 低電力消耗與高速度I C的要 提供可靠的電流承載功能。 常重要的，因電阻小的元件 時間也較短，I C元件的速度 現’因鋼的電阻值比鋁還小 銅在石夕中的擴散速率很高， 物而降低可靠度，而且銅導 圖案’因此在半導體進入深 用銅導線鑲嵌（damascene 方式’配合使用低介電質的 機械研磨（chemical )磨除介電層表面上多餘的銅 件之高頻I C晶片結 3 2時，於進行銅的化 但在形成如第1圖具有内建電感元 構時，形成銅金屬導線3 0與電感元件[Field of the Invention] The present invention relates to a semiconductor material that uses copper. [Background of the Invention] In the semiconductor manufacturing process, various transistors are required to make use of semiconductor components. The process of depositing conductors that are very small and have a circuit pattern is relatively fine after deep sub-micron processes. On the other hand, the aluminum wire cannot reduce the resistance of the connection. Small, RC delay will also be faster, so there are copper wires: Although copper has a lower resistance than aluminum, but because the copper contaminated wires on the Shixi substrate cannot be etched to form the sub-micron area of the wires, some people Developed a material for copper interconnection) as the dielectric layer, and then used chemical mechanical polishing, CMP metal layer. A method for manufacturing a component, particularly a method for forming a connecting wire between components. Line connection (interconnection device function, and own semiconductor as the main wire material, because it is very easy to cut money, but when the half-element accumulation is getting higher and higher, the wire has low power consumption and high-speed IC To provide a reliable current-carrying function. Often it is important that the time of IC components is short because of the low resistance components. Because the resistance value of steel is smaller than aluminum, the diffusion rate of copper in stone is very high. Reduced reliability, and the copper conductive pattern 'damascene method' (damascene method) is used to deepen the semiconductor into the high-frequency IC chip with the use of low-dielectric mechanical polishing to remove excess copper on the surface of the dielectric layer At the time of junction 32, when copper is converted, but when a built-in inductor structure is formed as shown in FIG. 1, a copper metal wire 30 and an inductor are formed.
第4頁 564543 i 五、發明說明（2) -- 學機械研磨過程，或疑磨墊中研磨顆 污染物附著在晶圓表面的現象’極易在銅金屬表面產生製 程缺陷’這進一步限制了銅金屬在半導體製程上的應用。 因此習知半導體製造方法中’在面臨元件積集度越來 越高’製程的線寬愈來愈小的情況下，應用銅材質的導線 結構是未來的趨勢’但銅在矽基底形成的污染物不僅影^ 元件的穩定性’難以製作較小的半導體元件，更降低^ 之良率及電性品質。因此’本發明即在針對上述之缺失， 提出一種形成高頻I C導線與電感線圈元件的方法，以有效 克服傳統方式之缺失。 【發明目的與概述】 本發明之主要目的係在提供一種形成高頻丨(^導線與電 感線圈元件的方法，其係利用光阻浮離（photoresist lift-off)的方式’形成銅金屬導線及電感的線圈結構， 以減少電力的消耗，發揮銅導線的特性。 本發明之次要目的係在提供一種形成高頻丨(；導線與電 感線圈元件的方法，可降低RC延遲時間，並提升抗電子遷 移的特性，藉此增進元件之特性及電性品質。 為達到上述之目的，本發明係在^一基底表面完成元件 層後，塗佈一光阻，利用對準、曝光及顯影等製程形成一 圖案化光阻，接著在光阻與未被光阻覆蓋的基底中鑛上一 層金屬銅，經光阻浮離的步驟，形成銅導線或電感線圈結 構。 以下藉由具體實施例配合所附的圖式詳加說明，當更Page 4 564543 i V. Description of the invention (2)-learn the mechanical polishing process, or the phenomenon of abrasive particles contaminating the wafer surface in the polishing pad 'prone to produce process defects on the surface of copper metal', which further limits Application of copper metal in semiconductor process. Therefore, it is known in the semiconductor manufacturing method that "in the face of increasingly higher component accumulation" in the process of the line width is getting smaller and smaller, the use of copper wire structure is the future trend ", but the formation of copper on the silicon substrate pollution Objects not only affect the stability of the device, it is difficult to make smaller semiconductor devices, but also reduce the yield and electrical quality of the device. Therefore, the present invention proposes a method for forming a high-frequency IC wire and an inductor coil component in order to effectively overcome the deficiency of the traditional method in view of the above-mentioned defects. [Objective and Summary of the Invention] The main purpose of the present invention is to provide a method for forming high-frequency wires and inductor coil components, which uses a photoresist lift-off method to form copper metal wires and The coil structure of the inductor reduces the power consumption and makes use of the characteristics of the copper wire. The secondary object of the present invention is to provide a method for forming high-frequency wires and wires and inductor coil components, which can reduce the RC delay time and improve the resistance. The characteristics of electron migration, thereby improving the characteristics and electrical quality of the device. In order to achieve the above-mentioned purpose, the present invention is to apply a photoresist after completing the device layer on the surface of a substrate, and use processes such as alignment, exposure and development. A patterned photoresist is formed, and then a layer of metal copper is deposited on the photoresist and the substrate not covered by the photoresist, and the photoresist is floated away to form a copper wire or an inductor coil structure. The following uses specific examples to cooperate with the The attached drawings are explained in detail.
第5頁 564543Page 5 564543
技術内容、特點及其所達成之功 爷易瞭解本發明之目的 效0 【圖號簡單說明】 10 基底 12 元件層 14 光阻 16 罩幕層 18 圖案化光阻 20 金屬層 3 0 銅金屬導線 32 電感元件 【詳細說明】 、請參閱第2A圖:首先提供一基底1〇，在該基底1〇上形 成一 7L件層1 2，該元件層丨2視不同的半導體結構而有所不 同，該7C件層1 2包括主動區、隔離結構與被動元件等，如 在金氧半％效電晶體（MOSFET)中，元件層12則可為一閘 氧化層、多晶矽層之閘極堆疊結構與源極/汲極等結構設 ’接著在該元件層1 2上塗佈一層光阻1 4，此處所形成的 ^阻1 4係為負光阻，即經過曝光的部份會因為光化學反應 變成交連狀（cross-linked)及高分子化（polymerized) ’在顯影之後變硬而保留在基底表面，未曝光的部份被顯 影劑所溶解。 接著請參閱第2B圖，在該光阻1 4上覆蓋一罩幕層1 6， 經對準與曝光步驟後，進行.一氨氣體的曝光後烘烤The technical content, characteristics and achievements achieved are easy to understand the purpose and effect of the present invention. [Simplified description of the drawing number] 10 substrate 12 element layer 14 photoresist 16 mask layer 18 patterned photoresist 20 metal layer 3 0 copper metal wire 32 Inductive element [Detailed description] Please refer to FIG. 2A: First, a substrate 10 is provided, and a 7L component layer 12 is formed on the substrate 10. The element layer 2 differs according to different semiconductor structures. The 7C component layer 12 includes an active region, an isolation structure, and a passive component. For example, in a metal-oxide-semiconductor half-effect transistor (MOSFET), the component layer 12 may be a gate oxide layer and a gate stack structure of a polycrystalline silicon layer. The source / drain structure and other structures are then coated with a layer of photoresist 14 on the element layer 12. The ^ resistance 14 formed here is a negative photoresist, that is, the exposed portion will be reacted by photochemical reactions. Cross-linked and polymerized 'After development, it hardens and remains on the substrate surface, and the unexposed part is dissolved by the developer. Next, please refer to FIG. 2B. A photomask 16 is covered on the photoresist 14 and after the alignment and exposure steps, an ammonia gas is baked after the exposure.
第6頁 564543 五、發明說明（4) (postexposure bake)，以減少光阻層14的曝光過度及 曝光不足區域之條紋狀結構產生的駐波效應（standing wave effect)，其中該氨氣體在反應爐中的濃度接近飽 和’而爐中的溫度則控制在5 0°C至2 5 0°C之間；然後再經 紫外線的照射以強化光阻結構，避免後續形成銅薄膜時， 發生光阻軟化的現象。 經顯影步驟，將罩幕層1 6的圖案轉移至光阻1 4上，蝕 刻光阻1 4形成如第2 B圖所示之反梯形態樣的圖案化光阻1 8 ’即底邊窄頂邊寬的光阻形狀，蝕刻的方式可利用非等向 性的乾蝕刻。 然 除去圖 和可能 應；接 阻18覆 2 0係以 層2 0最 確保圖 層2 0完 浮離步 形 製程。 4匕光阻 未連接 傻進行金 案化光阻 的聚合物 著請參閱 蓋的元件 濺鍍或蒸 好不能出 案化光阻 全隔離， 驟時，形 成鋼金屬 如第2D圖 1 8上的鋼 ’因此將 屬前的 18與基 ，以減 第2C圖 層12表 链方式 現在該 18上的 即沒有 成所需 層2 0後 所示， 金屬層 半導體 清洗步 底10上 少這些 ，在圖 面形成 沈積的 反梯形 銅金屬 連接的 的銅金 ，接著 由於前 2 0與元 材料放 驟（metal pre-clean)，以 元件層1 2表面的自然 殘餘物可能引起的高 案化光阻1 8與未被圖 一銅金屬 一層銅薄 圖案化光 層2 0與元 情形發生 屬導線。 進行去除 述形成銅 件層1 2表 入含丙_ 層20，該銅 膜。形成的 阻1 8的兩壁 件層1 2上的 ，以在後續 該圖案化光 金屬層2 0時 面的銅金屬 之類的溶劑 氧化層 電阻效 案化光 金屬層 銅金屬 邊，以 銅金屬 的光阻 阻18的 ，圖案 層2 0並 中，即Page 6 564543 V. Description of the invention (4) (postexposure bake) to reduce the standing wave effect caused by the stripe structure of the overexposed and underexposed areas of the photoresist layer 14, wherein the ammonia gas is reacting The concentration in the furnace is close to saturation, and the temperature in the furnace is controlled between 50 ° C and 250 ° C; then, the photoresist structure is strengthened by ultraviolet irradiation to avoid photoresist when the copper film is subsequently formed. Softening phenomenon. After the developing step, the pattern of the cover layer 16 is transferred to the photoresist 14 and the photoresist 14 is etched to form a patterned photoresist 1 8 ′ as shown in FIG. 2B, that is, the bottom edge is narrow. The top edge has a wide photoresist shape, and the etching method can use anisotropic dry etching. Of course, remove the map and possible applications; the resistance of 18 over 20 is to ensure that the layer 20 finishes the floating step process. 4 The photoresist is not connected. The polymer of gold photoresist is not connected. Please refer to the components of the cover. Sputtering or steaming can not isolate the photoresist. The photoresist is completely isolated. At the moment, a steel metal is formed as shown in Figure 2D 18 Steel 'will therefore belong to the former 18 and the base, in the manner of subtracting the 2C layer 12 from the bracelet. Now that the 18 is not formed into the required layer 20, as shown in the figure below, the metal layer semiconductor cleaning step bottom 10 is less, in the drawing The deposited copper-gold of the anti-trapezoidal copper metal connection is formed, and then the high photoresistance may be caused by the natural residue on the surface of the element layer 12 due to the first 20 and metal pre-clean. The copper layer and the thin patterned light layer 20 and the copper layer 20 which are not shown in FIG. 1 belong to wires. Removal is performed to form the copper member layer 12 and the acrylic layer-containing layer 20, the copper film. The resistive layer 18 on the two wall member layers 12 is formed by using a solvent oxide layer such as copper metal in the subsequent patterning of the photometal layer 20 to form a resistive effect on the photometal layer. Metal photoresist 18, pattern layer 20 and middle
第7頁 564543 發明說明（5) 可一起除去圖案化光阻18及鑛在其上的銅金屬層2〇(即銅 薄膜），此即為光阻浮離的步驟；再經過去離子水 (deionized water)的刷洗(scrubbing)。光阻浮離後 留在元件層12表面的銅金屬層20，即為所需的銅導線圖案 ’亦可在形成銅導線圖案的表面形成一介質層，再重覆形 成銅導線圖案，如此即可形成電感元件線圈的結構，藉以 提升電感的效能。 因此’本發明在基底上完成元件區之後，在元件區表 面形成一圖案化光阻，接著於光阻與未被光阻覆蓋的元件 區表面鑛上一層銅薄膜，經光阻浮離即可在元件區表面形 成銅金屬導線，可充份運用銅材質的低電阻與抗電性遷移 的能力’降低半導體裝置所需的電力，並提升元件的速度 ’藉此增加產品的特性及電性品質，以提升產品的良率。 以上所述之實施例僅係為說明本發明之技術思想及特 ，、’其目，在使熟習此項技藝之人士能夠瞭解本發明之内 容並據以實施，當不能以之限定本發明之專利範圍，即大 ，依本發明所揭示之精神所作之均等變化或修飾，仍應涵 蓋在本發明之專利範圍内。Page 7 564543 Description of the invention (5) The patterned photoresist 18 and the copper metal layer 20 (that is, the copper thin film) on it can be removed together. This is the photoresist floating step; then deionized water ( deionized water) scrubbing. The copper metal layer 20 remaining on the surface of the element layer 12 after the photoresist floats away is the desired copper wire pattern. A dielectric layer can also be formed on the surface of the copper wire pattern, and then the copper wire pattern is repeatedly formed, so that The structure of the coil of the inductive element can be formed, thereby improving the efficiency of the inductor. Therefore, after the present invention completes the element region on the substrate, a patterned photoresist is formed on the surface of the element region, and then a copper thin film is deposited on the surface of the photoresist and the element region not covered by the photoresist, and the photoresist can float away. The copper metal wire is formed on the surface of the element area, which can fully use the low resistance of copper and the ability to resist electrical migration. 'Reducing the power required for semiconductor devices and increasing the speed of components', thereby increasing product characteristics and electrical quality. To improve product yield. The above-mentioned embodiments are only for explaining the technical ideas and features of the present invention, and its purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. It should not be used to limit the scope of the present invention. The scope of patents, that is, large, equal changes or modifications made in accordance with the spirit disclosed by the present invention, should still be covered by the patent scope of the present invention.
564543 圖式簡單說明 第1圖為習知具有内建電感元件矽晶片的剖面示意圖。 第2A圖至第2D圖為本發明製造銅導線結構的剖面示意圖。 mu 第9頁564543 Brief Description of Drawings Figure 1 is a schematic cross-sectional view of a conventional silicon wafer with a built-in inductance element. Figures 2A to 2D are schematic cross-sectional views of a copper wire structure manufactured by the present invention. mu p. 9