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CN112147848A - Preparation method of small-size groove - Google Patents

Preparation method of small-size groove Download PDF

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Publication number
CN112147848A
CN112147848A CN201910563067.9A CN201910563067A CN112147848A CN 112147848 A CN112147848 A CN 112147848A CN 201910563067 A CN201910563067 A CN 201910563067A CN 112147848 A CN112147848 A CN 112147848A
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Prior art keywords
photoresist
chip
baking
layer
groove
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Inventor
王金翠
苏建
任夫洋
陈康
吴萌萌
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Shandong Huaguang Optoelectronics Co Ltd
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Shandong Huaguang Optoelectronics Co Ltd
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G03F7/162—Coating on a rotating support, e.g. using a whirler or a spinner
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G03F7/168—Finishing the coated layer, e.g. drying, baking, soaking
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G03F7/2024—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure of the already developed image
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

The invention discloses a preparation method of a small-size groove, which comprises the following steps of firstly spin-coating a layer of thick positive photoresist on an epitaxial wafer, preparing a photoresist window with a certain width by utilizing a photoetching mask plate in an exposure and development mode, then directly spin-coating a layer of thin photoresist on a bottom with the photoresist to form a photoresist mask layer with a groove-shaped radian, wherein the size of the bottom of the groove-shaped radian is smaller than the width of a photoresist development pattern, finally etching the thinner photoresist at the bottom of the groove by dry etching, and then directly taking the photoresist as a mask to continuously etch to obtain a groove pattern with the size less than or equal to 5 mu m, thereby realizing the preparation of the smaller-size groove. The technical scheme has the advantages of reasonable design and simple operation, not only effectively realizes the preparation of the small-size groove, avoids multiple times of photoetching, can be realized by direct one-time dry etching, has low use cost, simplifies the process steps, and has better practicability.

Description

Preparation method of small-size groove
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a small-size groove.
Background
At present, the bar chip is more and more in demand, because the length of the bar chip is generally 1cm, in order to reduce the current density of the die, the light emitting points of the whole bar need to be increased, the size of a single chip is reduced, and in order to avoid the phenomenon that interference occurs between single dies in the bar, a groove needs to be prepared between the dies. Meanwhile, in order to use the whole bar most effectively, the light-emitting area of a single die is as large as possible, and the smaller the width of the groove is, the better the requirement on the photoetching technology is. However, in the photolithography process, especially in the preparation process of the small-sized pattern, how to accurately copy the small-sized pattern onto the photoresist on the surface of the epitaxial wafer mainly depends on the resolution, the photoresist and the etching technology of the photolithography machine, and the smaller the pattern size is, the higher the resolution requirement of the photolithography machine is, the higher the corresponding requirement on the photolithography machine is, and the more expensive the required equipment is. In the actual operation process, the pattern photoresist with good appearance and narrow line width is difficult to form due to optical diffraction effect and the like.
Chinese patent CN101042536A provides a method for reducing the critical dimension of a photoresist pattern used for forming contact holes during the photolithography process of semiconductor devices, thereby obtaining a contact hole pattern with a critical dimension below 90nm, and the main technique of the patent is to coat a photoacid inhibitor on the exposed photoresist pattern, and obtain a contact hole pattern with a reduced critical dimension through secondary exposure, baking and development. Which needs to be performed before the first exposure without development, cannot first form a pattern on the substrate that conforms to the dimensions of the mask pattern. Chinese patent CN1531018A discloses spin-coating a chemical diffusion layer on a patterned photoresist with a first line width, performing a chemical reaction between chemical substances in the diffusion layer and the patterned photoresist, forming a reaction layer on the surface of the photoresist, and removing the chemical reaction layer to correct the patterned photoresist to obtain a second line width, thereby achieving the effect of reducing the pattern size. The method achieves the purpose of reducing the size of the photoresist by carrying out secondary exposure and development after the first-time exposed pattern photoresist is coated with chemical substances in a spinning mode.
Chinese patent CN103268854B discloses a photoresist groove covering process, which comprises covering photoresist in a groove by adopting two times of photoetching, coating a layer of photoresist on each time of photoetching, wherein the time interval from the completion of the first photoetching development to the second photoetching coating of photoresist is not more than 1 hour, the depth of the groove is 80-90um, and the thickness of the photoresist is 7-8 um. And finally, the effects that the photoresist coverage at the step coverage part is good, no silicon platform is exposed, the surface graph is normal, and no redundant photoresist residue exists on the surface of the graph are achieved.
The first way is to spin a chemical substance on the patterned photoresist after the first exposure, and then perform the second exposure and development to achieve the purpose of reducing the size of the photoresist. The second method is to achieve good coverage of the deep groove step by the secondary photoresist throwing and the secondary photoetching. The required pattern is currently obtained by substantially direct photolithography of the photoresist.
In view of the above problems, a need exists to design a method for manufacturing a small-sized trench, which can not only effectively realize the manufacturing of the small-sized trench, but also needs to have low cost and good etching effect, and is one of the problems to be solved urgently.
Disclosure of Invention
The invention aims to provide a preparation method of a small-size groove, which is used for solving the problems in the prior art.
In order to achieve the purpose, the invention provides the following technical scheme:
a preparation method of a small-size groove comprises the following steps:
1) preparing a chip;
2) spin-coating a photoresist;
3) photoetching a pattern;
4) baking;
5) coating photoresist for the second time;
6) dry etching;
7) and (5) cleaning and finishing the operation.
The optimized scheme comprises the following steps:
1) preparing a chip;
2) spin coating a photoresist: spin-coating a layer of positive photoresist on the surface of the chip epitaxial wafer prepared in the step 1) to form a photoresist layer;
3) baking: baking the chip treated in the step 2) to remove the solvent in the photoresist;
4) and (3) photoetching a pattern: taking the chip baked in the step 3), exposing the photoresist layer by using a photoetching mask, then removing the photoresist on the exposed part through development, and photoetching a required pattern on the epitaxial wafer;
5) baking: baking the chip processed in the step 4) in an oven, and curing the photoresist;
6) and (3) secondary spin coating of photoresist: taking the chip baked in the step 5), and spin-coating a layer of positive photoresist on the surface of the photoresist layer to form a photoresist mask layer with a groove-shaped radian;
7) baking the chip treated in the step 6) to remove the solvent in the photoresist;
8) dry etching: taking the chip processed in the step 7), carrying out dry etching, etching the groove-shaped radian bottom of the photoresist mask layer, and etching downwards to a target depth to form a groove;
9) cleaning: and cleaning and removing the photoresist layer and the photoresist mask layer on the surface of the chip, and finishing the operation.
The optimized scheme comprises the following steps:
1) preparing a chip;
2) spin coating a photoresist: spin-coating a layer of positive photoresist on the surface of the chip epitaxial wafer prepared in the step 1) to form a photoresist layer; wherein the photoresist layer has a thickness of
Figure BDA0002108793420000041
In the step 2) of the technical scheme, firstly, the surface of the epitaxial wafer is rotatedCoating a photoresist to form a photoresist layer, so that an operator can conveniently perform subsequent photoetching, wherein the photoresist layer is relatively thick, so that not only can the chip material be effectively protected, but also the subsequent secondary spin-coating of the photoresist is facilitated, a photoresist mask layer with a groove-shaped radian is formed, and the smooth etching of the whole small-size groove is ensured;
3) baking: baking the chip treated in the step 2) to remove the solvent in the photoresist; baking the chip in the step 3) for removing the flux in the photoresist so as to facilitate subsequent photoetching;
4) and (3) photoetching a pattern: taking the chip baked in the step 3), exposing the photoresist layer by using a photoetching mask, then removing the photoresist on the exposed part through development, and photoetching a required pattern on the epitaxial wafer; wherein the width of the graph in the photoetching mask is 10-25 μm; exposing and developing the photoresist layer in the step 4), preliminarily forming a wider groove, and further determining the position of the groove to be etched finally on the wider groove by subsequent operation;
5) baking: baking the chip processed in the step 4) in an oven, and curing the photoresist; wherein the baking temperature is 90-110 ℃, and the baking time is 5-15 min; baking through an oven in the step 5) and curing the photoresist;
6) and (3) secondary spin coating of photoresist: taking the chip baked in the step 5), and spin-coating a layer of positive photoresist on the surface of the photoresist layer to form a photoresist mask layer with a groove-shaped radian; wherein the photoresist mask layer has a thickness of
Figure BDA0002108793420000051
Step 6) spin-coating a layer of positive photoresist on the wider groove formed in the step 4) again, wherein after the photoresist is uniformly coated, the middle part of the photoresist subjected to secondary spin-coating can sink into the wider groove due to the existence of the wider groove formed after the development in the step 4), so that a photoresist mask layer with a groove-shaped radian is formed; the thickness of the photoresist layer in the step 2) is larger than that of the photoresist mask layer in the step 6), and the thickness of the photoresist layer in the step 2) is selected as
Figure BDA0002108793420000052
The thickness of the photoresist mask layer in the step 6) is selected as
Figure BDA0002108793420000053
The design is that on the premise of protecting the chip, a certain height difference exists between the photoresist layer and the photoresist mask layer, and the groove-shaped radian generated after photoresist throwing is more obvious, so that the subsequent dry etching is convenient for operators, and the width of the etched groove is more accurate;
7) baking the chip treated in the step 6) to remove the solvent in the photoresist; baking the chip in the step 7) for removing the flux in the photoresist so as to facilitate subsequent dry etching;
8) dry etching: taking the chip processed in the step 7), carrying out dry etching, etching the groove-shaped radian bottom of the photoresist mask layer, and etching downwards to a target depth to form a groove; wherein the width of the groove is 2-6 um; etching the bottom of the groove-shaped radian of the photoresist mask layer by using dry etching in the step 8), and extending downwards along the bottom of the groove-shaped radian until reaching the target depth, so that the design can ensure that the size of the obtained groove is obviously smaller than that of the groove formed by photoetching in the step 4);
9) cleaning: and (3) taking the chip processed in the step 8), sequentially cleaning the chip by photoresist removing liquid, acetone, ethanol and pure water, removing the photoresist layer and the photoresist mask layer on the surface of the chip, and finishing the operation. Removing the photoresist layer and the photoresist mask layer on the surface of the chip in the step 9), generally sequentially cleaning by using a photoresist removing solution, acetone, ethanol and pure water, wherein the photoresist can be removed by using the photoresist removing solution, the residual photoresist removing solution on the chip is removed by using the acetone, the residual acetone on the chip is removed by using the ethanol, the ethanol is dissolved in water, and the cleaning by using the pure water is realized;
in an optimized scheme, in the step 3) and the step 7), the chip is placed into an oven during baking, the baking temperature is 90-110 ℃, and the baking time is 15-30 min.
In an optimized scheme, in the step 3) and the step 7), a hot plate is used for baking during baking, the baking temperature is 90-110 ℃, and the baking time is 1-4 min.
The baking method in the technical scheme is designed into two methods, one method is to bake by using an oven, the baking speed is slow, but the baking effect is more uniform; the other method is to bake by using a hot plate, wherein the baking speed of the hot plate is higher, but the baking effect is slightly poorer than that of an oven; in the technical scheme, the solvent in the photoresist is removed by baking in the step 3) and the step 7), so that the adhesion capability between the photoresist and the chip is improved, and the subsequent etching operation is ensured to be smoothly carried out.
According to an optimized scheme, the time interval from the completion of the photoetching development in the step 4) to the second spin coating of the photoresist in the step 6) is 1-12 h.
In the technical scheme, the spin coating of the photoresist is required to be performed for the second time as soon as possible, because interface adhesion exists between the photoresist layer generated in the step 3) and the photoresist mask layer generated in the step 7), and the adhesion effect between two layers of photoresist is reduced due to overlong interval time.
In a more optimized scheme, in the step 8), the etching method is one of ICP dry etching and RIE dry etching.
In the technical scheme, the etching method can be selected from ICP dry etching or RIE dry etching.
Compared with the prior art, the invention has the beneficial effects that:
at present, when a small-size groove is prepared, a photoetching machine is generally used for etching, the technical requirements on the resolution, the photoresist and the etching of the photoetching machine are high, the cost is high, and when the photoetching machine is used for preparing the small-size groove at present, the width of the groove is as low as 5um, and when the width of a target groove is less than 5um, the etching is difficult; according to the technical scheme, a layer of thick positive photoresist is firstly coated on an epitaxial wafer in a spinning mode, a photoresist window with a certain width is prepared by utilizing a photoetching mask plate in an exposure and development mode, then a layer of thin photoresist is directly coated on a bottom with the photoresist in a spinning mode to form a photoresist mask layer with a groove-shaped radian, the size of the bottom of the groove-shaped radian is smaller than the width of a photoresist development graph, finally the thinner photoresist at the bottom of a groove is etched through dry etching, then the photoresist is directly used as a mask to carry out continuous etching, the groove graph with the size smaller than or equal to 5 microns is obtained, and the preparation of the groove with smaller size is realized.
The preparation method of the small-size groove is designed according to the technical scheme, the steps are reasonable in design, the operation is simple, the preparation of the small-size groove is effectively realized, multiple times of photoetching are avoided, direct one-time dry etching can be realized, the production efficiency can be effectively improved, damage to epitaxial materials on an epitaxial wafer is avoided, the use cost is low, the process steps are simplified, and the practicability is good.
Drawings
In order that the present invention may be more readily and clearly understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
FIG. 1 is a process flow diagram of a method for forming a small trench according to the present invention;
FIG. 2 is a cross-sectional view of a pattern obtained after a single photolithography of the present invention;
FIG. 3 is a cross-sectional view of a wafer showing a pattern after a second spin-on of photoresist;
FIG. 4 is a cross-sectional view of the chip after the trench photoresist bottom photoresist has been etched away;
FIG. 5 is a cross-sectional view of a chip after dry etching is completed;
fig. 6 is a cross-sectional view of a chip after removal of the surface mask photoresist.
In the figure: 001-substrate and part of epitaxial layer, 002-relatively thick photoresist spun at one time, 003-relatively thin photoresist spun at the second time, 004-window area formed after etching away photoresist at the bottom of the trench type photoresist, and 005-width of groove formed by etching.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
step 1: firstly, preparing a chip;
step 2: spin-coating a photoresist, and spin-coating a layer of positive photoresist on the surface of the prepared chip epitaxial wafer to form a photoresist layer; baking the chip to remove the solvent in the photoresist; wherein the photoresist layer has a thickness of
Figure BDA0002108793420000081
And step 3: exposing the photoresist layer by using a photoetching mask, removing the photoresist of the exposed part by developing, and photoetching a required pattern photoresist on the epitaxial wafer, wherein the pattern width in the photoetching mask is 10 mu m;
and 4, step 4: then placing the processed chip in an oven for baking at 90 ℃ for 5 min;
and 5: secondly, carrying out secondary spin coating of photoresist, taking the baked chip, and carrying out spin coating of a layer of positive photoresist on the surface of the photoresist layer to form a photoresist mask layer with a groove-shaped radian; baking the chip to remove the solvent in the photoresist; wherein the photoresist mask layer has a thickness of
Figure BDA0002108793420000082
Step 6: performing dry etching, namely performing dry etching on the processed chip, etching away the photoresist at the bottom of the groove-shaped radian of the photoresist mask layer, and etching downwards to a target depth to form a groove; wherein the width of the groove is 2 um;
and 7: and cleaning and removing the photoresist layer and the photoresist mask layer on the surface of the chip, and finishing the operation.
Wherein in the step 2 and the step 5, the chip is placed into an oven when being baked, the baking temperature is 90 ℃, and the baking time is 15 min; in step 6, the etching method is ICP dry etching; and 3, after the photoetching development is finished, the time interval from the step 5 to the step 5 of spin-coating the photoresist for the second time is 1 h.
Example 2:
step 1: firstly, preparing a chip;
step 2: spin-coating a photoresist, and spin-coating a layer of positive photoresist on the surface of the prepared chip epitaxial wafer to form a photoresist layer; baking the chip to remove the solvent in the photoresist; wherein the photoresist layer has a thickness of
Figure BDA0002108793420000091
And step 3: exposing the photoresist layer by using a photoetching mask, removing the photoresist of the exposed part by developing, and photoetching a required pattern photoresist on the epitaxial wafer, wherein the pattern width in the photoetching mask is 18 mu m;
and 4, step 4: then placing the processed chip in an oven for baking at 100 ℃ for 10 min;
and 5: secondly, carrying out secondary spin coating of photoresist, taking the baked chip, and carrying out spin coating of a layer of positive photoresist on the surface of the photoresist layer to form a photoresist mask layer with a groove-shaped radian; baking the chip to remove the solvent in the photoresist; wherein the photoresist mask layer has a thickness of
Figure BDA0002108793420000092
Step 6: performing dry etching, namely performing dry etching on the processed chip, etching away the photoresist at the bottom of the groove-shaped radian of the photoresist mask layer, and etching downwards to a target depth to form a groove; wherein the width of the groove is 4 um;
and 7: and cleaning and removing the photoresist layer and the photoresist mask layer on the surface of the chip, and finishing the operation.
Wherein in the step 2 and the step 5, the chip is placed into an oven when being baked, the baking temperature is 100 ℃, and the baking time is 24 min; in step 6, the etching method is ICP dry etching; and 3, after the photoetching development is completed, the time interval from the step 5 to the step 5 of spin-coating the photoresist for the second time is 6 hours.
Example 3:
step 1: firstly, preparing a chip;
step 2: spin-coating a photoresist, and spin-coating a layer of positive photoresist on the surface of the prepared chip epitaxial wafer to form a photoresist layer; baking the chip to remove the solvent in the photoresist; wherein the photoresist layer has a thickness of
Figure BDA0002108793420000101
And step 3: exposing the photoresist layer by using a photoetching mask, removing the photoresist of the exposed part by developing, and photoetching a required pattern photoresist on the epitaxial wafer, wherein the pattern width in the photoetching mask is 25 mu m;
and 4, step 4: then placing the processed chip in an oven for baking at the baking temperature of 110 ℃ for 15 min;
and 5: secondly, carrying out secondary spin coating of photoresist, taking the baked chip, and carrying out spin coating of a layer of positive photoresist on the surface of the photoresist layer to form a photoresist mask layer with a groove-shaped radian; baking the chip to remove the solvent in the photoresist; wherein the photoresist mask layer has a thickness of
Figure BDA0002108793420000102
Step 6: performing dry etching, namely performing dry etching on the processed chip, etching away the photoresist at the bottom of the groove-shaped radian of the photoresist mask layer, and etching downwards to a target depth to form a groove; wherein the width of the groove is 6 um;
and 7: and cleaning and removing the photoresist layer and the photoresist mask layer on the surface of the chip, and finishing the operation.
Wherein in the step 2 and the step 5, the chip is placed into an oven when being baked, the baking temperature is 110 ℃, and the baking time is 30 min; in step 6, the etching method is ICP dry etching; and 3, after the photoetching development is completed, the time interval from the step 5 to the step 5 of spin-coating the photoresist for the second time is 12 hours.
Example 4:
step 1: firstly, preparing a chip;
step 2: spin-coating a photoresist, and spin-coating a layer of positive photoresist on the surface of the prepared chip epitaxial wafer to form a photoresist layer; baking the chip to remove the solvent in the photoresist; wherein the photoresist layer has a thickness of
Figure BDA0002108793420000111
And step 3: exposing the photoresist layer by using a photoetching mask, removing the photoresist of the exposed part by developing, and photoetching a required pattern photoresist on the epitaxial wafer, wherein the pattern width in the photoetching mask is 18 mu m;
and 4, step 4: then placing the processed chip in an oven for baking at 100 ℃ for 10 min;
and 5: secondly, carrying out secondary spin coating of photoresist, taking the baked chip, and carrying out spin coating of a layer of positive photoresist on the surface of the photoresist layer to form a photoresist mask layer with a groove-shaped radian; baking the chip to remove the solvent in the photoresist; wherein the photoresist mask layer has a thickness of
Figure BDA0002108793420000112
Step 6: performing dry etching, namely performing dry etching on the processed chip, etching away the photoresist at the bottom of the groove-shaped radian of the photoresist mask layer, and etching downwards to a target depth to form a groove; wherein the width of the groove is 4 um;
and 7: and cleaning and removing the photoresist layer and the photoresist mask layer on the surface of the chip, and finishing the operation.
Wherein in the step 2 and the step 5, the chip is placed into an oven when being baked, the baking temperature is 100 ℃, and the baking time is 24 min; in step 6, the etching method is RIE dry etching; and 3, after the photoetching development is completed, the time interval from the step 5 to the step 5 of spin-coating the photoresist for the second time is 6 hours.
Example 5:
the technical scheme of the embodiment 5 is the same as the step of the embodiment 2, and the difference is only that:
and 2, in the step 5, baking by using a hot plate at the baking temperature of 110 ℃ for 1 min.
Example 6:
the technical scheme of the embodiment 6 is the same as the step of the embodiment 2, and the difference is only that:
and 2, in the step 5, baking by using a hot plate at the baking temperature of 100 ℃ for 3 min.
Example 7:
the technical solution of the embodiment 7 is the same as the step of the embodiment 2, and the difference is only that:
and 2, in the step 5, baking by using a hot plate at the baking temperature of 90 ℃ for 4 min.
Comparative example 1:
step 1: firstly, preparing a chip;
step 2: spin-coating a photoresist, and spin-coating a layer of positive photoresist on the surface of the prepared chip epitaxial wafer to form a photoresist layer; baking the chip to remove the solvent in the photoresist; wherein the photoresist layer has a thickness of
Figure BDA0002108793420000121
And step 3: exposing the photoresist layer by using a photoetching mask, removing the photoresist of the exposed part by developing, and photoetching a required pattern photoresist on the epitaxial wafer, wherein the pattern width in the photoetching mask is 18 mu m;
and 4, step 4: then placing the processed chip in an oven for baking at 100 ℃ for 10 min;
and 5: carrying out dry etching, taking the processed chip, carrying out dry etching, and etching downwards to a target depth to form a groove;
step 6: and cleaning and removing the photoresist layer and the photoresist mask layer on the surface of the chip, and finishing the operation.
Wherein in the step 2, the chip is placed into an oven when being baked, the baking temperature is 100 ℃, and the baking time is 24 min; in step 5, the etching method is ICP dry etching.
Comparative example 2:
step 1: firstly, preparing a chip;
step 2: spin-coating a photoresist, and spin-coating a layer of positive photoresist on the surface of the prepared chip epitaxial wafer to form a photoresist layer; baking the chip to remove the solvent in the photoresist; wherein the photoresist layer has a thickness of
Figure BDA0002108793420000131
And step 3: exposing the photoresist layer by using a photoetching mask, removing the photoresist of the exposed part by developing, and photoetching a required pattern photoresist on the epitaxial wafer, wherein the pattern width in the photoetching mask is 18 mu m;
and 4, step 4: then placing the processed chip in an oven for baking at 100 ℃ for 10 min;
and 5: secondly, carrying out secondary spin coating of photoresist, taking the baked chip, and carrying out spin coating of a layer of positive photoresist on the surface of the photoresist layer to form a photoresist mask layer with a groove-shaped radian; baking the chip to remove the solvent in the photoresist; wherein the photoresist mask layer has a thickness of
Figure BDA0002108793420000132
Step 6: performing dry etching, namely performing dry etching on the processed chip, etching away the photoresist at the bottom of the groove-shaped radian of the photoresist mask layer, and etching downwards to a target depth to form a groove; wherein the width of the groove is 4 um;
and 7: and cleaning and removing the photoresist layer and the photoresist mask layer on the surface of the chip, and finishing the operation.
Wherein in the step 2 and the step 5, the chip is placed into an oven when being baked, the baking temperature is 100 ℃, and the baking time is 24 min; in step 6, the etching method is ICP dry etching; and 3, after the photoetching development is completed, the time interval from the step 5 to the step 5 of spin-coating the photoresist for the second time is 6 hours.
And (4) conclusion: the etching method in the embodiments 1 to 3 is ICP dry etching, and the etching method in the embodiment 4 is RIE dry etching; in the examples 1 to 3, the baking operation was completed by using an oven in the step 2 and the step 5, and in the examples 5 to 7, the baking operation was completed by using a hot plate;
in the comparative example 1, a photoresist window with a certain width is prepared by directly utilizing a photoetching mask plate in an exposure and development mode, and then dry etching is carried out; preparing a photoresist window with a certain width in the embodiment 2, directly spin-coating a layer of thin photoresist to form a photoresist mask layer with a groove-shaped radian, and then performing dry etching; example 2 is in contrast to comparative example 1.
Comparative example 2 the first spin-coating of the photoresist layer had a thickness of
Figure BDA0002108793420000141
The thickness of the mask layer formed by the second spin coating is
Figure BDA0002108793420000142
In example 2, the first spin coating has a photoresist layer thickness of
Figure BDA0002108793420000143
The thickness of the mask layer formed by the second spin coating is
Figure BDA0002108793420000144
Example 2 is to be contrasted with comparative example 2;
taking the trenches prepared in examples 1-7 and comparative example 1, comparing their trench widths, it was found that the trench widths in examples 1-7 were 2-6um, whereas the trench widths prepared in comparative example 1 were significantly greater than 6 um. Meanwhile, in the preparation process of the comparative example 2, the groove-shaped radian of the formed photoresist mask layer is found to be small, and the width of the groove after dry etching is smaller than that of the groove etched in the comparative example 1, but is obviously larger than that of the groove etched in the embodiment 2.
The preparation method of the small-size groove is designed according to the technical scheme, the steps are reasonable in design, the operation is simple, the preparation of the small-size groove is effectively realized, multiple times of photoetching are avoided, direct one-time dry etching can be realized, the production efficiency can be effectively improved, damage to epitaxial materials on an epitaxial wafer is avoided, the use cost is low, the process steps are simplified, and the practicability is good.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (7)

1. A preparation method of a small-size groove is characterized by comprising the following steps: the method comprises the following steps:
1) preparing a chip;
2) spin-coating a photoresist;
3) photoetching a pattern;
4) baking;
5) coating photoresist for the second time;
6) dry etching;
7) and (5) cleaning and finishing the operation.
2. The method for forming a small-sized trench according to claim 1, wherein: the method comprises the following steps:
1) preparing a chip;
2) spin coating a photoresist: spin-coating a layer of positive photoresist on the surface of the chip epitaxial wafer prepared in the step 1) to form a photoresist layer;
3) baking: baking the chip treated in the step 2) to remove the solvent in the photoresist;
4) and (3) photoetching a pattern: taking the chip baked in the step 3), exposing the photoresist layer by using a photoetching mask, then removing the photoresist on the exposed part through development, and photoetching a required pattern on the epitaxial wafer;
5) baking: baking the chip processed in the step 4) in an oven, and curing the photoresist;
6) and (3) secondary spin coating of photoresist: taking the chip baked in the step 5), and spin-coating a layer of positive photoresist on the surface of the photoresist layer to form a photoresist mask layer with a groove-shaped radian;
7) baking the chip treated in the step 6) to remove the solvent in the photoresist;
8) dry etching: taking the chip processed in the step 7), carrying out dry etching, etching the groove-shaped radian bottom of the photoresist mask layer, and etching downwards to a target depth to form a groove;
9) cleaning: and cleaning and removing the photoresist layer and the photoresist mask layer on the surface of the chip, and finishing the operation.
3. The method for forming a small-sized trench according to claim 2, wherein: the method comprises the following steps:
1) preparing a chip;
2) spin coating a photoresist: spin-coating a layer of positive photoresist on the surface of the chip epitaxial wafer prepared in the step 1) to form a photoresist layer; wherein the photoresist layer has a thickness of
Figure FDA0002108793410000022
3) Baking: baking the chip treated in the step 2) to remove the solvent in the photoresist;
4) and (3) photoetching a pattern: taking the chip baked in the step 3), exposing the photoresist layer by using a photoetching mask, then removing the photoresist on the exposed part through development, and photoetching a required pattern on the epitaxial wafer; wherein the width of the graph in the photoetching mask is 10-25 μm;
5) baking: baking the chip processed in the step 4) in an oven, and curing the photoresist; wherein the baking temperature is 90-110 ℃, and the baking time is 5-15 min;
6) and (3) secondary spin coating of photoresist: drying in the step 5)Spin-coating a layer of positive photoresist on the surface of the photoresist layer of the baked chip to form a photoresist mask layer with a groove-shaped radian; wherein the photoresist mask layer has a thickness of
Figure FDA0002108793410000021
7) Baking the chip treated in the step 6) to remove the solvent in the photoresist;
8) dry etching: taking the chip processed in the step 7), carrying out dry etching, etching the groove-shaped radian bottom of the photoresist mask layer, and etching downwards to a target depth to form a groove; wherein the width of the groove is 2-6 um;
9) cleaning: and (3) taking the chip processed in the step 8), sequentially cleaning the chip by photoresist removing liquid, acetone, ethanol and pure water, removing the photoresist layer and the photoresist mask layer on the surface of the chip, and finishing the operation.
4. The method for forming a small-sized trench according to claim 2, wherein: in the step 3) and the step 7), the chip is placed into an oven when being baked, the baking temperature is 90-110 ℃, and the baking time is 15-30 min.
5. The method for forming a small-sized trench according to claim 2, wherein: in the step 3) and the step 7), a hot plate is used for baking during baking, the baking temperature is 90-110 ℃, and the baking time is 1-4 min.
6. The method for forming a small-sized trench according to claim 2, wherein: the time interval from the completion of the photoetching development in the step 4) to the second spin coating of the photoresist in the step 6) is 1-12 h.
7. The method for forming a small-sized trench according to claim 2, wherein: in the step 8), the etching method is one of ICP dry etching and RIE dry etching.
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