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TW478130B - Method of manufacturing semiconductor devices, etching composition for manufacturing semiconductor devices, and semiconductor devices made thereby - Google Patents

Method of manufacturing semiconductor devices, etching composition for manufacturing semiconductor devices, and semiconductor devices made thereby Download PDF

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Publication number
TW478130B
TW478130B TW087112709A TW87112709A01A TW478130B TW 478130 B TW478130 B TW 478130B TW 087112709 A TW087112709 A TW 087112709A TW 87112709A01 A TW87112709A01 A TW 87112709A01A TW 478130 B TW478130 B TW 478130B
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TW
Taiwan
Prior art keywords
semiconductor substrate
manufacturing
layer
patent application
etching
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TW087112709A
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Chinese (zh)
Inventor
Gyu-Hwan Kwag
Se-Jong Ko
Kyung-Seuk Hwang
Jun-Ing Gil
Sang-O Park
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Samsung Electronics Co Ltd
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Publication of TW478130B publication Critical patent/TW478130B/en

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    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K13/00—Etching, surface-brightening or pickling compositions
    • C09K13/04—Etching, surface-brightening or pickling compositions containing an inorganic acid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of manufacturing semiconductor devices is provided, including the formation of a conductive plug and the minimizing of the step-height of an interlayer dielectric layer. An etching composition is also provided for such a manufacturing method. The method of manufacturing semiconductor devices includes the steps of forming an insulating layer over a semiconductor substrate, forming contact holes in the insulating layer, forming a conductive layer over the insulating layer to burying the contact holes, rotating the semiconductor substrate, and etching the conductive layer by supplying an etching composition on the rotating semiconductor substrate, and spin-etching the tungsten layer using an etching composition such that the conductive layer remains only inside the contact holes and does not remain over the insulating layer. The etching composition includes at least one oxidant selected form H2O2, O2, IO4, BrO3, ClO3, S2O8, KIO3, H5IO6, KOH and HNO3, at least enhancer selected form HF, NH4OH, H3PO4, H2SO4, NH4F and HCl, and a buffer solution, mixed together in certain amounts.

Description

478130478130

五、發明說明（1 ) 發明背景 本發明係關於半導體元件之製造過程。更特別地，本 發明關於一種製造半導體元件之方法，以藉由利用鎢、銅、 多晶矽及相似物來提供導電線或插塞之形成，以及藉由使 用特定的蝕刻組合物與旋轉蝕刻方法來蝕刻半導體基材上 之薄膜而將層間絕緣層之階梯高度減至最小。本發明亦相 關於一種用以製造半導體元件之蝕刻組合物，及藉此所得 之半導體元件。 經濟部智慧財產局員工消費合作社印製 近來，隨著半導體元件變得更為高度整合積集，對於 半導體元件用之細微圖樣形成技術與供半導體用之多分層 電路結構之使用已有一增加之需求。換言之，半導體元件 之表面構造正變得越來越複雜，而致使各層間之階梯高度 會在半導體元件之製造過程中造成功能異常。 自各種製造處理步驟間的微影過程中，一光阻圖樣藉 由以一光阻塗覆一晶圓而在半導體基材上被形成。一具有 電路形成元件之光罩在晶圓上被對正，藉由以光線照射晶 圓上的光阻而進行曝光程序。 具有相對大的臨界尺寸，即最小的尺寸欲被製造，與 低为層結構之半導體元件可以造成極少的問題。然而，就 目前被使用在半導體基材上之較精細圖樣與多分層結構而 吕’更難於曝光過程中在層與層之間之階梯高度的上位與 下位之間準確地定焦點。結果，難以達到準確的圖樣形成。 因此’用以將在層與層之間的階梯高度減至最小之平 面化方法已變得更為重要。諸如矽於玻璃上（S〇G)層沉 本紙張尺度適用中國國豕標準（CNS)A4規格（21〇 X 297公釐） (請先閱讀背面之注意事項再填寫本頁：> -線- 4 - 478130 經 濟- 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 A7 __B7____ 五、發明說明（2 ) ' · 積、回钱刻、或回流專之各種平面化方法已被採用，以便 克服上述之問題，但這些方法具有其他與其有關之問題。 另一種平面化之方法則為化學機械拋光（CMp)方法。 CMP方法已經發展成一種橫過晶圓之所有表面操作 之平面化程序。當CMP方法被應用於一半導體元件之製 造過程中實，平面化之移除速率與均勻度是重要的CMP 參數。 於二氧化矽（Si〇2)使用氧化層CMP程序被平面化的情 況下，二氧化矽（Si02)之性質經由與鹼性漿液之反應而改 變成親水性許可H20滲透。侵入二氧化矽（si〇2)的水打斷 二氧化矽（Si02)之連接鏈。接著，二氧化矽（si〇2)透過磨 蝕劑之使用藉由物理機構而被移除。 在使用CMP程序平面化金屬層之情況下，然而，在 金屬層之表面上經由漿液内部之氧化劑的化學反應產生一 金屬氧化層，此金屬氧化層與不平坦圖樣之最上層藉由磨 蝕劑之機械（物理）摩擦而被移除。 第1圖係為顯示傳統用以製造半導體元件之CMP裝置 之示意表示。 參考第1圖，CMP裝置包含：拋光頭102、拋光臺104、 及拋光墊108。該CMP程序在拋光臺104上進行。拋光墊1〇8 被行程在拋光臺104上，並且固定一半導體基材1〇〇。漿液 接著被從一漿液供應管線106供應並用來拋光半導體基材 100。拋光頭102將半導體基材固定至拋光墊1〇8上，並且 在一旋轉方向上為可移動的。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 478130 A7 ________ B7 五、發明說明（3 ) 拋光墊108在CMP程序中與半導體基材100接觸。半 導體基材100被拋光頭102旋轉，並且漿液在拋光墊108上 被供應。漿液與半導體基材1〇〇表面互相反應，其係半導 體基材100藉由拋光墊1〇8而被拋光。 第2至7圖係為顯示半導體元件之製造過程之橫截面 圖’俾說明習知用以形成鎢插塞之處理順序。用以形成鎢 插塞部分與對正記號之程序同時被顯示。 第2至7圖所示之半導體元件被劃分成一個單元部分 (C) ’係以電路系統之構件所形成，以及一周邊部分（p)， 係以對正記號、刻晝線等所形成。 如第2圖所示，一層氧化層n4在一半導體基材11〇上 被形成以作為一介電層，該半導體基材係具有複數被形成 呈彼此分離狀態之局部圖樣112。局部圖樣112各可包括一 多晶矽圖樣或金屬圖樣作為導電層。氧化層114係為由傳 統化學氣相沉積（CVD)所形成之二氧化矽層（si〇2)，雖然 磷矽酸鹽（PSG)層或硼磷矽酸鹽（BPSG)層亦可被用作在多 晶矽圖樣層之間或在金屬層之間的介電層。此時，氧化層 114在單元與周邊兩部分上被形成。 如第3圖所示，因為局部圖樣112的存在最初為不平坦 之氧化層114使用第1圖所示與上述之CMp裝置而被平面 化。 如第4圖所不，接觸孔116藉由典型的微影與蝕刻程序 所形成，該蝕刻程序係經由以光阻塗覆氧化層114、形成 光阻圖案、以及接著運用光阻圖樣作為一蝕刻罩幕來蝕刻V. Description of the Invention (1) Background of the Invention The present invention relates to the manufacturing process of semiconductor devices. More particularly, the present invention relates to a method of manufacturing a semiconductor element to provide the formation of conductive wires or plugs by using tungsten, copper, polycrystalline silicon, and the like, and by using a specific etching composition and a rotary etching method. The thin film on the semiconductor substrate is etched to minimize the step height of the interlayer insulating layer. The present invention also relates to an etching composition for manufacturing a semiconductor element, and a semiconductor element obtained therefrom. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Recently, as semiconductor components have become more highly integrated, there has been an increasing demand for the use of fine pattern formation technology for semiconductor components and the use of multi-layer circuit structures for semiconductor . In other words, the surface structure of semiconductor devices is becoming more and more complex, and the step heights between layers will cause functional abnormalities in the manufacturing process of semiconductor devices. From the lithography process between various manufacturing processing steps, a photoresist pattern is formed on a semiconductor substrate by coating a wafer with a photoresist. A photomask having circuit-forming elements is aligned on the wafer, and an exposure process is performed by irradiating a photoresist on the wafer with light. Semiconductor elements with relatively large critical dimensions, i.e. the smallest dimensions to be manufactured, and low layer structures can cause very few problems. However, with the finer patterns and multi-layered structures currently used on semiconductor substrates, it is more difficult to accurately focus the upper and lower positions of the step height between layers during the exposure process. As a result, it is difficult to achieve accurate pattern formation. Therefore, the planarization method to minimize the step height between layers has become more important. Such as silicon on glass (SOG) layer, the size of this paper is applicable to China National Standard (CNS) A4 (21〇X 297 mm) (Please read the precautions on the back before filling in this page:-> line -4-478130 Economy-Printed by A7 __B7____ of the Consumer Cooperatives of the Ministry of Intellectual Property Bureau V. Invention Description (2) '· Various planarization methods of accumulation, cashback, or recirculation have been adopted in order to overcome the above problems, But these methods have other problems related to them. Another method of planarization is the chemical mechanical polishing (CMp) method. The CMP method has been developed into a planarization procedure that operates across all surfaces of the wafer. When the CMP method is applied In the manufacturing process of a semiconductor device, the removal rate and uniformity of planarization are important CMP parameters. In the case where silicon dioxide (SiO2) is planarized using an oxide CMP process, silicon dioxide ( The property of Si02) is changed to be hydrophilic by reacting with the alkaline slurry to allow H20 to penetrate. Water invading the silicon dioxide (si02) breaks the connecting chain of silicon dioxide (Si02). Then, two Siliconized silicon (SiO2) is removed by physical means through the use of an abrasive. In the case of planarizing a metal layer using a CMP process, however, the surface of the metal layer is generated by a chemical reaction of an oxidant inside the slurry. A metal oxide layer, the metal oxide layer and the uppermost layer of the uneven pattern are removed by mechanical (physical) friction of the abrasive. Figure 1 is a schematic representation showing a conventional CMP device for manufacturing semiconductor devices. Referring to FIG. 1, the CMP apparatus includes a polishing head 102, a polishing table 104, and a polishing pad 108. The CMP process is performed on the polishing table 104. The polishing pad 108 is moved on the polishing table 104, and a semiconductor substrate is fixed. The material 100 is then supplied from a slurry supply line 106 and used to polish the semiconductor substrate 100. The polishing head 102 fixes the semiconductor substrate to a polishing pad 108 and is movable in a rotation direction. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------- Installation -------- Order -------- -Line (Please read the notes on the back before filling this page) Ministry of Economy Printed by the Intellectual Property Bureau employee consumer cooperative 478130 A7 ________ B7 V. Description of the invention (3) The polishing pad 108 is in contact with the semiconductor substrate 100 during the CMP process. The semiconductor substrate 100 is rotated by the polishing head 102 and the slurry is on the polishing pad 108 Is supplied. The slurry and the surface of the semiconductor substrate 100 react with each other, and the semiconductor substrate 100 is polished by the polishing pad 108. Figures 2 to 7 are cross-sectional views showing the manufacturing process of the semiconductor element.俾 Explain the processing sequence used to form tungsten plugs. The procedure used to form the tungsten plug portion and the alignment mark is displayed simultaneously. The semiconductor element shown in Figs. 2 to 7 is divided into a unit portion (C) 'formed by components of a circuit system, and a peripheral portion (p) formed by alignment marks, graticules, and the like. As shown in Fig. 2, an oxide layer n4 is formed as a dielectric layer on a semiconductor substrate 110, which has a plurality of partial patterns 112 formed in a separated state from each other. The partial patterns 112 may each include a polycrystalline silicon pattern or a metal pattern as a conductive layer. The oxide layer 114 is a silicon dioxide layer (SiO2) formed by a conventional chemical vapor deposition (CVD), although a phosphosilicate (PSG) layer or a borophosphosilicate (BPSG) layer can also be used. A dielectric layer between polysilicon pattern layers or between metal layers. At this time, the oxide layer 114 is formed on both the cell and the periphery. As shown in FIG. 3, the oxide layer 114, which is initially uneven because of the presence of the partial pattern 112, is planarized using the CMP device shown in FIG. 1 and described above. As shown in FIG. 4, the contact hole 116 is formed by a typical lithography and etching process. The etching process is performed by coating the oxide layer 114 with a photoresist, forming a photoresist pattern, and then applying the photoresist pattern as an etch. Mask to etch

6 478130 . . Α7 Β7 五、發明說明（4 ) 氧化層114。此時，用作一對正記號或刻畫線之周邊孔i i 8 在周邊區域（P)之氧化層114中以較接觸孔116更大的半徑 被形成。 如第5圖所示’在形成鶴層之前，雙鈇/1化鈦（Ti/TiN) 層在氧化層114所有的表面上被形成以作為障壁層12〇。雙 Ti/TiN障壁層包括一層Ti層120a以及一層TiN層120b。Ti 層120a係使用傳統錢鑛方法或CVD方法被形成，並且TiN 層120b係使用典型濺鍍方法被形成。障壁層120減少嫣層 之接觸電阻，並且改善氧化層114與鶴層之黏著性。此外 於隨後移除鎢層的遁程期間，障壁層120被用作一中止層。 此時，障壁層120被形成接觸孔116與周邊孔118上方與之 中。 如第6圖所示，一層鎢層122被形成於所有氧化層114 之上’該氧化層係具有足夠遮蓋接觸孔116且至少部分地 填滿周邊孔118的厚度。然而，周邊孔118具有較單元部分 之接觸孔116大的直徑，且如此周邊部分之周邊孔us不會 被以鎢層122完全地填滿，而是僅有其底部與側壁被覆蓋。 如第7圖所示，具有鎢層122形成於其上之半導體基材 110固定於第1圖之CMP裝置的拋光頭102上，且拋光塾1〇8 在金屬層漿液從漿液供應管線106被供應的同時與嫣層122 接觸。拋光頭102接著被以移除障壁層上之鎢膜122之上部 部分，使得鎢層下部部分123留在接觸孔116内部。然而此 時，鎢層下部部分123亦留在周邊孔118之底部與側壁上。。 在周邊孔118中之殘留鎢層123(即對正記號或刻晝線）之後 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------U5T--- (請先閱讀背面之注意事項再填寫本頁) ί Τ 經_濟部智慧財產局員工消費合作社印製 7 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（5 ) ' 在隨後的微影過程中會造成顆粒的產生。 鎢插塞形成程序典型在間層介電（ILD)層之平面化後 應會被進行。因此，當CMp程序被加至供半導體晶圓表 面用之平面化中時，因為准許交換拋光頭與漿液之短週 期，故CMP程序減少製造產率並增加半導體元件成本之 花費。 此外’在形成鶴插塞期間所使用的乾式回姓程序，因 為電漿之相關聯電氣充能動作，而增加電晶體之接觸電阻 與最差的電氣特性。 因此，以產生需求以發展一種可解決前述問題之方 法。是故，本發明提供一種解決上述問題以改善半導體元 件製造之效率與產量。 發明總結 本發明提供一種製造半導體元件之方法，係相關於運 用藉由在敬轉的半導體基材上供應餘刻組合物之旋轉餘 亥J方法來餘刻依半導體基材上的導電層與間層介電層。 本發明之另一目的藉由在半導體表面上無微刮痕的情 況下平面化間層介電層並形成導電插塞，而提供製造半導 體元件之方法，以避免接觸電阻無必要的增加。 本發明之另一目的提供一種蝕刻組合物，以藉由旋轉 姓刻方法蝕刻導電層或間層介電層。 根據本發明，一種製造半導體元件方法被提供，其係 包含將-絕緣層形成於-半導體基材上方、在絕緣層中形6 478130.. A7 B7 V. Description of the Invention (4) Oxidation layer 114. At this time, peripheral holes i i 8 serving as a pair of positive marks or scribe lines are formed in the oxide layer 114 in the peripheral region (P) with a larger radius than the contact holes 116. As shown in FIG. 5 ', before the crane layer is formed, a double hafnium / 1 titanium nitride (Ti / TiN) layer is formed on all surfaces of the oxide layer 114 as the barrier layer 120. The double Ti / TiN barrier layer includes a Ti layer 120a and a TiN layer 120b. The Ti layer 120a is formed using a conventional money deposit method or a CVD method, and the TiN layer 120b is formed using a typical sputtering method. The barrier layer 120 reduces the contact resistance of the dark layer and improves the adhesion between the oxide layer 114 and the crane layer. In addition, during the subsequent process of removing the tungsten layer, the barrier layer 120 is used as a stop layer. At this time, the barrier layer 120 is formed above and in the contact hole 116 and the peripheral hole 118. As shown in FIG. 6, a tungsten layer 122 is formed on all of the oxide layers 114. The oxide layer has a thickness sufficient to cover the contact hole 116 and at least partially fill the peripheral hole 118. However, the peripheral hole 118 has a larger diameter than the contact hole 116 of the unit portion, and thus the peripheral hole us of the peripheral portion will not be completely filled with the tungsten layer 122, but only the bottom and sidewalls thereof will be covered. As shown in FIG. 7, the semiconductor substrate 110 having the tungsten layer 122 formed thereon is fixed to the polishing head 102 of the CMP apparatus of FIG. 1, and the polishing slurry 108 is removed from the slurry supply line 106 in the metal layer slurry. At the same time of contact with Yan layer 122. The polishing head 102 is then removed to remove the upper portion of the tungsten film 122 on the barrier layer so that the lower portion 123 of the tungsten layer remains inside the contact hole 116. However, at this time, the lower portion 123 of the tungsten layer is also left on the bottom and sidewalls of the peripheral hole 118. . After the residual tungsten layer 123 in the peripheral hole 118 (that is, the alignment mark or graticule), this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ---------- --- U5T --- (Please read the notes on the back before filling out this page) ί Τ Economic_Printed by the Employees 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Invention Note (5) 'particles will be generated in the subsequent lithography process. The tungsten plug formation process should typically be performed after the planarization of the interlayer dielectric (ILD) layer. Therefore, when the CMP procedure is added to the planarization for the surface of the semiconductor wafer, the CMP procedure reduces the manufacturing yield and increases the cost of the semiconductor element because the short period of the exchange of the polishing head and the slurry is allowed. In addition, the dry-type surname procedure used during the formation of the crane plug is due to the associated electrical charging action of the plasma, which increases the contact resistance of the transistor and the worst electrical characteristics. Therefore, to generate demand to develop a method that can solve the aforementioned problems. Therefore, the present invention provides a solution to the above problems to improve the efficiency and yield of semiconductor device manufacturing. SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device, which is related to the use of a rotating Yu Hai J method by supplying an uncut composition on a semiconductor substrate that is turned around, to engrav the conductive layer and the semiconductor layer on the semiconductor substrate. Layer dielectric layer. Another object of the present invention is to provide a method for manufacturing a semiconductor element by planarizing an interlayer dielectric layer and forming a conductive plug without micro scratches on a semiconductor surface, so as to avoid an unnecessary increase in contact resistance. Another object of the present invention is to provide an etching composition for etching a conductive layer or an interlayer dielectric layer by a rotary etching method. According to the present invention, a method for manufacturing a semiconductor element is provided, which comprises forming an insulating layer over a semiconductor substrate, forming the insulating layer in the insulating layer,

8 Γ- 3 1X 8 47 經•濟部智慧財產局員工消費合作社印製 A7 _ B7_ 五、發明說明（6 ) · 成接觸孔、在絕緣·層之上形成一導電層以遮蓋接觸孔、旋 轉半導體基材、以及藉由在旋轉的半導體基材上供應蝕刻 組合物來姓刻導電層。餘刻組合物較好包含至少一種選自 由h2o2、〇2、Ι04·、ΚΙ03、H5I〇6、KOH與hno3所組成之 基團的氧化劑、至少一種選自由HF、ΝΗ4ΟΗ、Η3Ρ04、 H2S04、NH4F與HC1所組成之基團的促進劑、以及一緩衝 溶液之混合物。氧化劑、促進劑、以及緩衝溶液較好具有 一混合比例，使得在蝕刻之後，導電層物質僅出現在接觸 孔内，而不會留在絕緣層之上。 緩衝溶液包含去離子水。導電層會包含選自由鎢 (W)、銅（Cu)、以及多晶矽所組成之群組的物質。 本方法進一步包括在將接觸孔形成於絕緣層中之後， 但在形成導電層之前，形成一障壁金屬層在半導體基材與 絕緣層之上。壁障金屬層會包含一種選自由Ti、TiN、 Ti/TiN、Ta、TaN、及Ta/TaN所組成之群組之物質。 半導體基材的旋轉速度較好每分鐘轉速在200至5000 之間。蝕刻組合物較好以0.1至2.5升/分鐘的速率被供應。 餘刻組合物被一個置放在半導體基材上方的喷嘴供 應，噴嘴係受到噴桿之擺動而至半導體基材中心的右側或 左側。喷桿擺動較好從80mm變化至半導體基材中心的左 側，且從80mm變化至半導體基材中心的右側。噴桿擺動 包含一個長距離的噴桿擺動部分與一個短距離的喷桿擺動 部分，其係貫序地被進行。 蝕刻組合物的處理溫度是在20至90°C的範圍中，並且 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 9 A7 B7 五、發明說明（7) 一 半導體基材被好被加熱至約為蝕刻組合物的處理溫度。 更特別地，蝕刻組合物包含作為一氧化劑重量百分比 為0.01至30之HN〇3、作為一促進劑重量百分比為〇 〇1至3〇 的NHJ、及具有剩餘重量百分比的去離子水◊蝕刻組合 物亦可以包含作為一氧化劑重量百分比為3至55的111^〇3、 作為一促進劑重量百分比為〇2至35的HF、及具有剩餘重 量百分比的去離子水。蝕刻組合物亦可以包含作為一氧化 劑重量百分比為〇 2至3〇的H2〇2、作為一.促進劑重量百分 比為0.01至30的ΝΗβΗ、及具有剩餘重量百分比的去離子 水。蝕刻組合物亦可以包含作為一氧化劑重量百分比為3 至60的HNO3、作為一促進劑重量百分比為〇 〇6至3〇的Ηρ、 及具有剩餘重量百分比的去離子水。 本發明亦提供有一種包含下列步驟之製造半導體元件 方法’該等步驟係為：在一半導體基材上形成一層絕緣層， 在絕緣層中形成接觸孔，在絕緣層之上形成一層導電層以 遮蓋接觸孔，旋轉半導體基材，藉由將第一姓刻組合物供 應至旋轉的半導體基材上來執行具有第一蝕刻速率之第一 蝕刻，以便蝕刻導電層至其總厚度的4〇%至95%之間的厚 度，以及藉由將第二蝕刻組成物供應至旋轉的半導體基材 上來執行具有較第一餘刻速率低的第二蚀刻速率之第二餘 刻，以便餘刻導電層的剩餘部分，其中在第二餘刻後，導 電層僅存在接觸孔之内。 本發明亦提供-種製造半導體之方法，其係包含下列 乂驟·在半導體基材上形成—圖樣結構、在半導體基材 (請先閱讀背面之注意事項再填寫本頁) . --線· 經濟部智慧財產局員工消費合作社印製8 Γ- 3 1X 8 47 Printed by the Ministry of Economic Affairs and Intellectual Property Bureau's Consumer Cooperatives A7 _ B7_ V. Description of the Invention (6) · Form a contact hole, form a conductive layer on top of the insulation layer to cover the contact hole, rotate A semiconductor substrate, and a conductive layer is etched by supplying an etching composition on a rotating semiconductor substrate. The remaining composition preferably includes at least one oxidizing agent selected from the group consisting of h2o2, 02, Ι04 ·, KI03, H5IO06, KOH and hno3, and at least one selected from HF, ΝΗ4ΟΗ, Η3Ρ04, H2S04, NH4F and HC1 is a mixture of accelerators and a buffer solution. The oxidizing agent, the accelerator, and the buffer solution preferably have a mixing ratio so that after the etching, the conductive layer substance appears only in the contact hole and does not remain on the insulating layer. The buffer solution contains deionized water. The conductive layer may include a substance selected from the group consisting of tungsten (W), copper (Cu), and polycrystalline silicon. The method further includes forming a barrier metal layer on the semiconductor substrate and the insulating layer after forming the contact hole in the insulating layer but before forming the conductive layer. The barrier metal layer will include a substance selected from the group consisting of Ti, TiN, Ti / TiN, Ta, TaN, and Ta / TaN. The rotation speed of the semiconductor substrate is preferably between 200 and 5000 per minute. The etching composition is preferably supplied at a rate of 0.1 to 2.5 liters / minute. The remaining composition is supplied by a nozzle placed over the semiconductor substrate, and the nozzle is swung to the right or left of the center of the semiconductor substrate by the swinging of the boom. The boom swing preferably changes from 80 mm to the left side of the center of the semiconductor substrate, and from 80 mm to the right side of the center of the semiconductor substrate. Boom swing consists of a long-distance boom swing section and a short-distance boom swing section, which are performed sequentially. The processing temperature of the etching composition is in the range of 20 to 90 ° C, and the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------- Assembly -------- Order --------- Line (Please read the precautions on the back before filling out this page) 9 A7 B7 V. Description of the invention (7) A semiconductor substrate is well covered Heat to about the processing temperature of the etching composition. More specifically, the etching composition includes HN03 as an oxidizing agent in a weight percentage of 0.01 to 30, NHJ as a promoter in a weight percentage of 0.001 to 30, and a deionized leech etching combination having a remaining weight percentage. The product may also include 111 ^ 03 as an oxidant weight percentage of 3 to 55, HF as a promoter weight percentage of 02 to 35, and deionized water with a remaining weight percentage. The etching composition may also include H202 as a oxidizing agent in a weight percentage of 02 to 30 as N. βΗ as a promoter weight percentage of 0.01 to 30, and deionized water having a remaining weight percentage. The etching composition may also include HNO3 as an oxidant in a weight percentage of 3 to 60, Ηρ as a promoter in a weight percentage of 006 to 30, and deionized water with a remaining weight percentage. The present invention also provides a method for manufacturing a semiconductor element including the following steps: these steps are: forming an insulating layer on a semiconductor substrate, forming a contact hole in the insulating layer, and forming a conductive layer on the insulating layer to Cover the contact holes, rotate the semiconductor substrate, and perform a first etch with a first etch rate by supplying the first scribe composition to the rotated semiconductor substrate so as to etch the conductive layer to 40% of its total thickness A thickness between 95%, and a second etch having a second etch rate lower than the first etch rate is performed by supplying a second etch composition onto the rotating semiconductor substrate so that the conductive layer is etched The remaining part, wherein after the second remaining moment, the conductive layer exists only within the contact hole. The present invention also provides a method for manufacturing a semiconductor, which includes the following steps: forming on a semiconductor substrate-pattern structure, on the semiconductor substrate (please read the precautions on the back before filling this page). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

10 經濟部智慧財產局員工消費合作社印製 478130 A7 ________B7__ 五、發明說明（8 ) 與圖樣結構上形成一層間層介電層、旋轉半導體基材、以 及藉由在旋轉的半導體基材上供應一蝕刻組合物來蝕刻間 層介電層，該#刻組合物係包含至少一種選自由H202、. 02、10/、Br〇3、C103、S208、ΚΙ03、H5I〇6、KOH及 hno3 所組成之基團的氧化劑、至少一種選自由HF、NH4OH、 Η3Ρ04、H2S04、NH4F與HC1所組成的基團之促進劑、以 及緩衝溶液之混合物，其中氧化劑、促進劑與緩衝溶液被 以一定的混合比例混合，使得蝕刻平面化間層介電層。 間層介電層會包含一種選自由氧化物、氮化物、硼填 石夕（borophosphosilicate)、與原石夕酸四乙脂（tetraethylorthosilicate) 所組成之群組的物質。 本發明亦提供一種用以製造半導體元件之蝕刻組合 物，其係包含至少一種選自由H202、02、I04_、Br03、Cl〇3、 s2o8_、κιο3、h5io6、koh與hno3所組成的基團之氧化 劑、至少一種選自由 HF、nh4oh、h3po4、h2so4、nh4f 與HC1所組成的基團之促進劑、以及一緩衝溶液。 蝕刻組合誤會被供應至一旋轉的半導體基材上，以便 蝕刻一層被形成在半導體基材上的特定薄層。此特定薄層 包含一種選自由鎢（W)、銅（Cu)、多晶矽、氧化物、氮化 物、糊填石夕（borophosphosilicate)、或原石夕酸四乙脂 (tetraethylorthosilicate)所組成之群組的物質。 此外，一種半導體基材被提供，係包含一個包括一由 導電材料所組成的導電插塞之晶包區域，以及一個包括一 被用作對正記號或刻畫線其中之一者的孔圖樣之周邊區 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) -11 - 478130 A7 B7 五、發明說明（9 域’其中孔圖樣不含導電材料 (請先閱讀背面之注意事項再填寫本頁) 圖式之簡短說明 在後附圖式中： 第1圖為顯示傳統用以製造半導體元件之CMP裝置之 概要示意圖； 第2至7圖為顯示使用形成鎢插塞與對正記號或刻晝線 用之傳統處理順序的半導體元件製造過程之橫節面圖； 第8圖為藉由重量百分比率顯示供鎢層用之蝕刻組合 物的蝕刻速率傾向之圖形表示圖； 第9圖為顯示被用來進行根據本發明之第一較佳實施 例之半導體元件製程之旋轉蝕刻裝置之概要示意圖； 第10圖為顯示根據喷桿擺動之蝕刻速率圖形表示圖， 該喷#擺動係根據本發明之第一較佳實施例而生者； -線· 第11圖為顯示對於根據本發明之第一較佳實施例之各 種喷桿擺動之蝕刻速率與蝕刻均勻度之圖形表示圖，· 第12至17圖為顯示被用來說明根據本發明第一較佳實 施例之鎢插塞形成過程之處理順序的橫截面圖； 經濟部智慧財產局員工消費合作社印製 第18圖為顯示使用根據本發明第一較佳實施例之製造 半導體元件方法所產生的多層結構之圖式； 第19至23圖為顯示與多晶矽插塞一起運用根據本發明 第二較佳實施例之製造半導體元件方法的單元墊形成過程 之橫截面圖； 第24至28圖為顯示使用根據本發明第三較佳實施例之10 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 478130 A7 ________B7__ V. Description of the Invention (8) An interlayer dielectric layer is formed on the pattern structure, the semiconductor substrate is rotated, and a semiconductor substrate is supplied by rotating the semiconductor substrate. The etching composition is used to etch the interlayer dielectric layer, and the #etching composition comprises at least one selected from the group consisting of H202, .02, 10 /, Br03, C103, S208, KI03, H5IO06, KOH, and hno3. An oxidant of the group, at least one accelerator selected from the group consisting of HF, NH4OH, Η3PO4, H2S04, NH4F and HC1, and a mixture of buffer solutions, wherein the oxidant, the accelerator and the buffer solution are mixed in a certain mixing ratio To etch the planarized interlayer dielectric layer. The interlayer dielectric layer will comprise a substance selected from the group consisting of oxide, nitride, borophosphosilicate, and tetraethylorthosilicate. The present invention also provides an etching composition for manufacturing a semiconductor device, which comprises at least one oxidizing agent selected from the group consisting of H202, 02, I04_, Br03, Cl03, s2o8_, κιο3, h5io6, koh, and hno3. At least one promoter selected from the group consisting of HF, nh4oh, h3po4, h2so4, nh4f and HC1, and a buffer solution. The etch combination is mistakenly supplied to a rotating semiconductor substrate to etch a specific thin layer formed on the semiconductor substrate. This specific thin layer comprises a member selected from the group consisting of tungsten (W), copper (Cu), polycrystalline silicon, oxides, nitrides, borophosphosilicate, or tetraethylorthosilicate. substance. In addition, a semiconductor substrate is provided that includes a cladding region including a conductive plug composed of a conductive material, and a peripheral region including a hole pattern used as one of alignment marks or scribe lines. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------- Installation -------- Order -------- -Line (please read the notes on the back before filling this page) -11-478130 A7 B7 V. Description of the invention (9 fields' where the hole pattern does not contain conductive material (please read the notes on the back before filling this page) Figure The short description of the formula is in the following drawings: Figure 1 is a schematic diagram showing a conventional CMP device for manufacturing semiconductor devices; Figures 2 to 7 are diagrams showing the use of tungsten plugs and alignment marks or daylight lines. A cross-sectional view of a semiconductor device manufacturing process in a conventional processing sequence; FIG. 8 is a graphic representation showing a tendency of an etching rate of an etching composition for a tungsten layer by a percentage by weight; Carrying out the semiconductor device manufacturing process according to the first preferred embodiment of the present invention The schematic diagram of the rotary etching device; Figure 10 is a graphic representation showing the etching rate according to the swing of the spray rod, the spray # swing was born according to the first preferred embodiment of the present invention;-line · Figure 11 shows Graphical representations of the etch rate and etch uniformity of various boom swings according to the first preferred embodiment of the present invention. Figures 12 to 17 are diagrams used to illustrate the first preferred embodiment of the present invention. Cross-sectional view of the processing sequence of the tungsten plug formation process; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 18 is a diagram showing a multilayer structure produced using the method of manufacturing a semiconductor device according to the first preferred embodiment of the present invention. Figures 19 to 23 are cross-sectional views showing a cell pad formation process using a polycrystalline silicon plug according to a second preferred embodiment of the method for manufacturing a semiconductor device according to the present invention; Figures 24 to 28 are views showing the use of a cell pad according to the present invention Of the third preferred embodiment

經•濟部智慧財產局員工消費合作社印製 478130 A7 B7 五、發明說明（1G) 製造半導體元件之方法之平面化過程的橫截面圖。 校佳f施例之掸to說明 本發明現在將會參考後附圖式更詳細地說明於下，其 中顯示本發明之較佳實施例。然而，本發明被以許多不同 的形式具體實施，但不應該被認為是限制於在此陳述的實 施例中。而是，這些實施例被提供，使得此揭露内容將會 更透徹與完全，並且將會對於熟習該項技藝者完全地傳輸 本發明之範圍。 根據本發明，一種新的旋轉蝕刻方法或一種化學增強 拋光（CEP)方法被用來蝕刻具有預定厚度的材料層，材料 層該係諸如銅、鎢、多晶矽、氧化矽、氮化矽、或相似物。 此CEP方法藉由在旋轉半導體晶圓的同時將化學溶液供應 至半導體晶圓表面上來被執行。 · CEP方法亦被用來藉由將化學溶液供應至半導體晶圓 表面上並旋轉半導體晶圓，而製造具有導電線或插塞（被 以銅、鎢、多晶矽等所製成）之半導體元件。 導電線一般作為用以將半導體元件之内部信號平移至 半導體7L件的外侧之互聯線。導電插塞一般從低互聯線將 電氣信號平移至高互聯線。 CEP方法被用來製造具有經平面化或均勻表面之半導 體晶圓，以便更容易便於製造半導體元件之其後處理步驟 的操作。 在CEP方法中，被形成在半導體晶圓表面上的介電材 本紙張尺度適用中國國家輝準（CNS)A4規格（210 X 297公爱） ---------------------訂-----I--- (請先閱讀背面之注意事項再填寫本頁) 13 A7 B7 五、發明說明（11 微n 減切，被平面化，以在移動到其後的 二 半導體晶圓表面上方的階梯高度減至最小。 子用在此程序中的介電材料典型是内層介電（明或 金屬間介電（IMD)者。 根據本發明較佳實_，_溶液域刻組合物包括 、匕劑、-促進劑、以及一緩衝溶液。氧化劑較好包括 至少—種選自由 H2〇2、〇2、I(V、Br〇3、cl〇3、S2(v、Ki〇3、 Η5队、KOH與HN〇3所組成的基團。促進劑較好包含至少 一種選自由HF、NH4〇H、H3P〇4、H2S〇4、聊與腦所 組成的基團之物質。緩衝溶液被用來控制_組成物的濃 度、溫度及接觸角度，並且較好包含去離子水。 一種較佳的蝕刻組成物較好包含作為—氧化劑重量百 分比為0.01至60的冊〇3、作為一促進劑重量百分比為〇〇5 至35的HF、及作為-緩衝溶液具有剩餘重量百分比的去 離子水。此蝕刻組合物，係包括HN03、HF與去離子水的 混合物’可以被用來姓刻導電層（即銅、嫣、與多晶石夕等） 或介電層（即氧化矽、氮化矽等）。 另一種較佳的蝕刻組合物包含作為_氧化劑重量百分 比為0.2至30的札〇2、作為一促進劑重量百分比為〇〇1至3〇 的NHUOH、以及作為一緩衝溶液具有剩餘重量百分比的 去離子水。此蝕刻組合物，係包括H2〇2、NH4〇H與去離 子水的混合物，可以被用來蝕刻導電或介電層，以及障壁 層（即 Ti、Ta、Ti/TiN、Ta/TaN等）。 又另外一種較佳的蝕刻組合物包含作為一氧化劑重量 本紙張尺度適用中國國家谭準（CNS)A4規格（210 x 297公釐） (請先閱讀背面之注意事項再填寫本頁) --線- 經濟部智慧財產局員工消費合作社印製 14 f- 經濟部中央標準局員工消費合作社印製 A7 -~_____B7_ 五、發明説明（12 ) …， 百刀比為0.01至30的HNO3、作為一促進劑重量百分比為 0·01至30的NHJ、以及作為一緩衝溶液具有剩餘重量百 分比的去離子水。此蝕刻組合物，係包括11]^〇3、NH4F與 去離子水的混合物，可以被用來蝕刻導電或介電層，以及 障壁層。 第8圖是根據被用在姓刻組合物中之氧化劑的重量百 刀比顯示鶴層之姓刻組合物之钱刻速率傾向的圖形表示 圖。 如第8圖所示，線A說明一種組成物之蝕刻速率傾向， 該組成物包含作為氧化劑之HNO3、作為促進劑之HF、及 作為緩衝溶液之去離子水的混合物。既然如此，線A顯示 蝕刻速率之增加與總蝕刻組合物中的HN〇3成分之量（重量 百分比）成正比。線B說明一種組成物之姓刻速率傾向，該 組成物係包含一種具有作為氧化劑的％〇2、作為促進劑 的NH4〇H、及作為緩衝溶液的去離子水。線B顯示蚀刻速 率之減少與在總蝕刻組合物中H2〇2成分的量（重量百分比） 成正比。 第9圖為顯示一種被用來進行根據本發明較佳實施例 之半導體元件製程之旋轉蝕刻裝置之概要示意圖。 如第9圖所示，一旋轉蝕刻裝置2〇〇包含一馬達2ιι、 一旋轉夾盤212、一盆器213、複數個喷嘴214、一夾具215、 一排泄管217、一調整器218、即一凡氣體管線219。旋轉 夾盤212被設置在半導體基材21〇的下方，而用以提供蝕刻 組合物之喷嘴214被置放在半導體基材21〇之上。噴嘴214Printed by the Ministry of Economic Affairs and Intellectual Property Bureau's Consumer Cooperative 478130 A7 B7 V. Description of Invention (1G) A cross-sectional view of the planarization process of a method for manufacturing semiconductor components. The explanation of the embodiment of the embodiment of the present invention will now be described in more detail with reference to the accompanying drawings, which shows a preferred embodiment of the present invention. The invention is, however, embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. According to the present invention, a new spin etching method or a chemically enhanced polishing (CEP) method is used to etch a material layer having a predetermined thickness, such as copper, tungsten, polycrystalline silicon, silicon oxide, silicon nitride, or the like Thing. This CEP method is performed by supplying a chemical solution onto the surface of a semiconductor wafer while rotating the semiconductor wafer. The CEP method is also used to manufacture semiconductor components with conductive wires or plugs (made of copper, tungsten, polycrystalline silicon, etc.) by supplying chemical solutions onto the surface of the semiconductor wafer and rotating the semiconductor wafer. The conductive line is generally used as an interconnection line for translating the internal signal of the semiconductor element to the outside of the semiconductor 7L component. Conductive plugs typically translate electrical signals from low interconnect lines to high interconnect lines. The CEP method is used to fabricate a semiconductor wafer having a planarized or uniform surface to make it easier to handle the subsequent processing steps of manufacturing a semiconductor element. In the CEP method, the dielectric material formed on the surface of the semiconductor wafer has a paper size that conforms to China National Standard for Standards (CNS) A4 (210 X 297 public love) ------------- -------- Order ----- I --- (Please read the notes on the back before filling this page) 13 A7 B7 V. Description of the invention (11 micron cut, flattened to The height of the step above the surface of the next two semiconductor wafers is minimized. The dielectric material used in this process is typically an interlayer dielectric (bright or intermetal dielectric (IMD)). According to the present invention, Jiashi _, _ solution domain engraving composition includes, dagger, -promoter, and a buffer solution. The oxidant preferably includes at least one selected from the group consisting of H202, 02, I (V, Br03, cl. 3. S2 (v, Ki03, Η5 team, KOH and HN03. The accelerator preferably contains at least one selected from the group consisting of HF, NH4OH, H3P04, H2S04, chat and brain The composition of the group of substances. The buffer solution is used to control the concentration, temperature and contact angle of the composition, and preferably contains deionized water. A preferred etching composition preferably contains as— The chemical agent has a weight percentage of 0.01 to 60, HF as a promoter weight percentage of 0.05 to 35, and deionized water with a remaining weight percentage as a buffer solution. This etching composition includes HN03 The mixture of HF, HF and deionized water can be used to engrave a conductive layer (ie, copper, copper, polycrystalline stone, etc.) or a dielectric layer (ie, silicon oxide, silicon nitride, etc.). Another preferred The etching composition contains ZrO2 as an oxidant weight percentage of 0.2 to 30, NHUOH as a promoter weight percentage of 0.001 to 30, and deionized water with a remaining weight percentage as a buffer solution. This etch The composition, which is a mixture of H2O2, NH4OH and deionized water, can be used to etch conductive or dielectric layers, and barrier layers (ie, Ti, Ta, Ti / TiN, Ta / TaN, etc.). Another preferred etching composition contains as an oxidant the weight of this paper is applicable to China National Tan Zhun (CNS) A4 specifications (210 x 297 mm) (Please read the precautions on the back before filling this page) --line- Bureau of Intellectual Property, Ministry of Economic Affairs Printed by the Industrial and Consumer Cooperatives 14 f- Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7-~ _____ B7_ V. Description of the Invention (12)… HNO3 with a hundred-to-blade ratio of 0.01 to 30, as a promoter weight percentage of 0 · NHJ from 01 to 30, and deionized water with a remaining weight percentage as a buffer solution. This etching composition includes 11] ^ 3, a mixture of NH4F and deionized water, and can be used to etch conductive or dielectric And the barrier layer. Fig. 8 is a graphic representation showing the tendency of the rate of money engraving of the composition of the crane layer based on the weight-to-weight ratio of the oxidant used in the composition of the last name. As shown in Fig. 8, line A illustrates the etching rate tendency of a composition containing a mixture of HNO3 as an oxidant, HF as a promoter, and deionized water as a buffer solution. In this case, line A shows that the increase in the etching rate is proportional to the amount (% by weight) of the HN03 component in the total etching composition. Line B illustrates the inscription rate tendency of a composition containing a% 02 as an oxidant, NH4OH as a promoter, and deionized water as a buffer solution. Line B shows that the decrease in the etching rate is directly proportional to the amount (weight percentage) of the H2O2 component in the total etching composition. FIG. 9 is a schematic diagram showing a rotary etching apparatus used for a semiconductor device manufacturing process according to a preferred embodiment of the present invention. As shown in FIG. 9, a rotary etching apparatus 200 includes a motor 2m, a rotary chuck 212, a basin 213, a plurality of nozzles 214, a clamp 215, a drain pipe 217, an adjuster 218, that is,一 凡 Gas line 219. The spin chuck 212 is disposed below the semiconductor substrate 21o, and a nozzle 214 for providing an etching composition is disposed on the semiconductor substrate 21o. Nozzle 214

-----------^------訂------線 {請先閱讀背面之注意事項再填寫本頁J----------- ^ ------ Order ------ Line {Please read the notes on the back before filling in this page J

15 478130 A7 ______________ B7 五、發明説明（13 ) … 較好可以被移動至旋轉夾具212的左邊或右邊，並且將蝕 刻組合物供應至半導體基材21〇上。其中一個喷嘴214亦較 好可以供諸如去離子水的清潔溶液使用。 盆被213設置以覆蓋旋轉夾具212，且避免蝕刻組合物 在處理期間流出。透過氣體管線219供應之n2氣體被供應 至故轉夾具212’以舉起半導體基材21〇約2mm。N2氣體係 有用於特別地處理半導體基材212的後側。 揭露在第9圖中較佳的旋轉蝕刻裝置使用加熱器216來 控制％氣體的溫度。此外，此裝置亦具有另一個加熱器（未 顯示）來控制蝕刻組合物的溫度。 雖然A氣體被用在第一較佳實施例中以加熱半導體 基材210，另一種氣體亦可以被使用。然而，較好的是， 使用的氣體為一惰性氣體，使得氣體本身不會干擾蝕刻程 序。 經濟部中央標準局員工消費合作社印製 餘刻組合物的溫度較好是在從2〇至9〇。(：的範圍中。更 好的是，姓刻組合物的溫度是在從3〇至7〇。〇的範圍中，以 加速在半導體基材上材料層的蝕刻速率。氣體較佳的 溫度也是在從30至70°C的範圍中，以加熱在旋轉夾具212 上的半導體基材210。若半導體基材21〇在蝕刻組合物被加 熱的同時未被加熱，則在半導體基材21〇與蝕刻組合物的 温度差將會在所有的材料層（例如，銅、嫣、多晶石夕、氧 化矽、氮化矽）上造成不同的蝕刻速率。這樣依次可以在 姓刻程序後導致半導體基材21〇的不均勻表面。 在一操作中，蝕刻組合物被從喷嘴214供應至半導體 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 16 缓濟部智慧財產局員工消費合作社印製 478130 Α7 Β7 五、發明說明（14) 基材210上時其溫度會改變，即變冷，並且被散佈在半導 體基材210的表面上。因為餘刻組合物的溫度會隨其流動 而改變，所以其溫度會在半導體基材210表面之每一點處 變化。換言之，被應用至半導體基材210上之蝕刻組合物 的溫度會橫跨所有在半導體基材210表面上的接觸點變 化。 由於此溫度差的結果，一個在半導體基材21 〇上姓刻 組合物被第一次應用/接觸之部分具有比蝕刻組合物較晚 被供應/接觸之半導體基材210的一部份更高的蝕刻速率。 蝕刻速率亦會根據蝕刻組合物在半導體基材21〇整個 表面上流動而變化。這些蝕刻變化對於諸如300mm直徑之 晶圓之較大直徑半導體晶圓會更嚴重。因為較大的晶圓， 所以蝕刻組合物之較大溫度差真得會橫過半導體晶圓表面 發生。 所以’本發明之觀念教示各種提供均勻處理條件之方 法，諸如將經加熱的N2氣體供應至基材、在旋轉夾具212 設置一加熱器、一種將一旋轉蝕刻處理腔室包含或封閉在 一密閉、溫度被控制、處理環境中、以及其他相似者。 触刻組合物之供應速度較好是約〇1至2·5升/分鐘，並 且蝕刻組合物可以藉由不同程度的喷桿擺動被供應至半導 體基材210上從中心至右側或左側。 噴桿擺動表不在半導體基材21〇上供應蝕刻組合物之 喷嘴214的移動範圍。為參考目的，從半導體中心至左側 之噴桿擺動被認為是負（_)，而從半導體基材21〇的中心至 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ---------------------訂--------- (請先閱讀背面之注意事項再填寫本頁) 17 478130 A7 B7 五、發明說明（I5 ) 右側之噴桿擺動被認為是正。對於在此揭露中被說明 之較佳實施例，喷桿擺動以單位mm給定。 本發明之喷桿擺動移動範圍較好是從〇至+/_ g〇。換言 之，喷嘴214較好在移動直到半導體基材21〇中心的左側或 右側80mm的同時供應蝕刻組合物。因為喷桿擺動是一個 影響欲被蝕刻之薄層的蝕刻均勻度之參數，故供一給定 CEP過程用之喷桿擺動應被最佳化。 喷桿擺動應較好以一長距離喷桿擺動與一短距離噴桿 擺動兩者被進行，其係被順序地進行。一長距離噴桿擺動 是喷嘴214被移動橫過一個長距離之喷桿擺動，例如直至 喷嘴214可准許之最大可能擺動。一短距離喷桿擺動是喷 最被移動橫過一距離較長喷桿擺動短之喷桿擺動，例如某 些較喷嘴214可准許之最大可能擺動少的距離。 第10圖疋顯示根據橫過基材21〇中各種位置之喷桿擺 動的#刻速率之圖形表示圖。該圖顯示當使用一蝕刻組合 物蝕刻一鎢層時的蝕刻速率，該蝕刻組合物係包含一種作 為氧化劑之HNO3、作為促進劑之HF、及作為緩衝溶液之 去離子水的混合物。 線C顯示當以被固定在半導體基材中心上的喷嘴2 J 4 在半導體基材上供應姓刻組合物時之餘刻速率。如c線所 示，在此情況中，位於半導體基材21〇之中心部分處的蝕 刻速率疋比位於半導體基材21〇之周邊邊緣處之蝕刻速率 相對地高。 線D顯不當以進行一長距離噴桿擺動之喷嘴214在半 本紙張尺度適用中國國家谭準(CNS)A4規格（210 X四7公釐）_ (請先閱讀背面之注意事項再填寫本頁) · 經濟部智慧財產局員工消費合作社印別农 ο 3 1X 8 47 經濟部智慧財產局員工消費合作社印製 A7 ________B7___ 五、發明說明（16 ) ’ ' 導體基材上供應蝕刻組合物時之蝕刻速率。如線D所示， 在此情況中，位於半導體基材21〇之周邊邊緣處的蝕刻速 率比位於半導體基材之中心部分處的蝕刻速率相對地高。 線E顯示當以順序進行一長距離喷桿擺動與一短距離 噴杯擺動之喷嘴214，在半導體基材上供應蝕刻組合物時 的蝕刻速率。如線E所示，在此情況中，位於半導體基材 210的周邊邊緣與中心處的蝕刻速率幾乎是相似的。 第11圖是顯示根據各種喷桿擺動之蝕刻速率與蝕刻均 勻度的圖形表示圖。該圖顯示當使用一種蝕刻組合物來蝕 刻一層鎢層時之蝕刻速率，該蝕刻組合物係包含一種作為 氧化劑之HN〇3、作為促進劑iNHj、及作為緩衝溶液之 去離子水的混合物。特別地，長條圖顯示蝕刻速率，並且 線F顯示蝕刻均勻度。 第11圖之長條圖所示枝蝕刻速率表示欲被一蝕刻溶液 蝕刻一定時間之薄層的厚度。第n圖之線F所示之蝕刻均 勻度表示在蝕刻被完成後，位於多個薄層點處之厚度的偏 差，例如一個中心點、一個邊緣點及一個中間點。所此， 在所示點間的偏差值越低，造成的姓刻越均勻。 如第11圖所示，當順序地並連續地進行長距離喷桿擺 動與短距離喷桿擺動時，蝕刻速率被增加並且蝕刻均勻度 被改進。當喷桿擺動是-20〜〇時，蝕刻速率約是54〇A/min， 其係足以滿足處理條件。然而，均勻度約是1〇%，係太高。 當噴桿擺動是-40〜0時，蝕刻速率降低至一不適合的程度， 並且不均勻度上升至甚至是更無法接受的量。 本纸張尺度適用中國國家槔準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------轉 (請先閱讀背面之注意事項再填寫本頁) 19 478130 A7 B7 五、發明說明（17 ) 然而，當喷桿擺動被以-40〜0與-20〜0順序地進行時， 餘刻速率約是540人/min並且姓刻均勻度約是1%，前述兩 者對於處理條件為可接受者。此即表示第10圖中的線E可 以藉由線D與C的處理條件而被得到。 此外，根據本發明較佳實施例，當有一部份在半導體 基材上的薄層要求較大的蝕刻時，供應蝕刻組合物之喷嘴 214被准許較長的停留，並且蝕刻組合物被准許在欲被蝕 刻的部分上供應一段較長的時間。 旋轉夾具之旋轉速度在供應蝕刻組合物的同時較好是 在每分鐘轉速（rpm)為200至5000的範圍中。 一種使用蝕刻組合物製造半導體元件之方法根據較佳 實施例而被說明於下，但是本發明應不被築構成被限制於 這些下列的實施例中。 第一較佳實施例 經濟部智慧財產局員工消費合作社印製 製造半導體元件以形成一導電插塞之方法的第一較佳 實施例現在將會被說明。此實施例提供一種新的方法，以 便在沒有因CMP程序所造成的表面微刮痕與未增加乾式 回蝕刻程序所造成的接觸電阻之情況下形成一互聯導電插 根據本發明，一種製造半導體元件之方法包括下列步 驟：在一半導體基材上形成一層介電層、在介電層中形成 接觸孔、在介電層上形成一層導電層並填滿接觸孔、旋轉 半導體基材、以及將蝕刻組合物供應旱旋轉的半導體基材 本紙張尺度適用中國國家槔準（CNS)A4規格（210 X 297公釐） 20 經濟部智慧財產局員工消費合作社印製 478130 A7 __—___ B7 五、發明說明（18) 上。蝕刻組合物較好包含一種以一定混合比率混合至少一 種選自由 H202、02、1〇4·、Βγ〇3、cl〇3、S2〇8·、KI〇3、H5I〇6、 KOH與HNO3所組成的基團之氧化劑、至少一種選自由 HF、NHWH、HJO4、h2S04、NH4F與 HC1所組成的基團 之促進劑、以及一緩衝溶液之混合物，使得在蝕刻後導電 層之材料僅留在接觸孔的内部，而不會留在介電層之上。 導電層較好疋一層鶴層（W)或一層銅層（Cu)。導電插 塞較好透過被形成在介電層中的接觸孔連接一層上導電層 與一層下導電層。 在形成導電插塞期間，一具有導電層被形成於其上之 半導體基材210較好被安裝在一個可旋轉的旋轉夾具212 上，並且以一定的速率旋轉。 藉由透過一被置放在半導體基材21〇上的喷嘴214來供 應一蝕刻組合物，在半導體基材210上的導電層接著被蝕 刻’使得導電層僅留在接觸孔之内，而不會留在介電層之 上。 換言之，導電層介層係藉由水平方向上之增加的姓刻 動量以及與導電層有良好反應之蝕刻組合物所被蝕刻，該 姓刻動量為因為旋轉夾具214之旋轉而造成半導體基材21〇 之離心力所生者。 越高的旋轉夾具214之旋轉速度，越多的蝕刻動量將 會在水平方向上增加。結果，藉由此過程，導電層的蝕刻 速度與蝕刻均勻度被改善，並且被形成在導電層上不必要 的空隙之產生被避免。 紙張尺度適用中國國家標準（CNtS)a4規格（210 X 297公餐1 一 " ' ---- -------------裝--------訂---------綠 (請先閱讀背面之注意事項再填寫本頁) 21 478130 A7 B7 五、發明說明（19 ) 將蝕刻組合物供應至半導體基材上之步驟較好以兩步 驟進行。第一步驟包括供應一種包括一具有第一蝕刻速率 之第一餘刻組合物的第一物質。第二步驟包括供應一種包 括一具有比第一蝕刻速率低的第二蝕刻速率之第二蝕刻組 合物。 第12至17圖是顯示使用根據本發明第一較佳實施例之 製造半導體元件之方法的鎢插塞形成過程之處理順序的橫 結面圖。這些圖式顯示導電插塞（例如鎢插塞）之形成，與 一對正記號或刻劃線之形成。在這些圖式中，顯示一個用 以形成電路圖樣之單元部分（C)與一個用以形成對正記號 或刻劃線之周邊部分（P)。 參考第12圖，一層氧化膜224在半導體基材220上被形 成’其係具有複數個彼此相互分離一定距離而被形成於其 上之局部圖樣222。局部圖樣222較好是多晶矽圖樣或是金 屬圖樣以作為低導電層。氧化層224可以是一層二氧化矽 層（Si02)、磷矽玻璃（PSG)、或是硼磷矽玻璃（BPSG)、或 其他相似物，其係較好以典型的CVD方法或旋塗式玻璃 (SOG)法。氧化層224的厚度較好約是4000至15000人。 經濟部智慧財產局員工消費合作社印製 參考第13圖，光阻（未顯示）被塗覆在氧化層224上， 並且猎由一傳統的微影程序而被形成圖案（未顯示）。一部 为的氧化層224接者被傳統的餘刻程序钱刻，以便形成一 接觸孔226以及被作為一對正記號或刻劃線之周邊孔228。 周邊孔228較好具有一個比接觸孔226大的直徑。 參考第14圖，一層障壁層230(例如雙Ti/TiN層）較好 本紙張尺度適用中國國家镡準（CNS)A4規格（210 x 297公釐） 22 經濟部智慧財產局員工消費合作社印製 478130 A7 B7 五、發明說明（20) 在導電層料被沉積潛在接觸孔226與周邊孔228中被形成。 障壁層230較好包括一層下障壁層230a(例如Ti)與一層上 障壁層230b(例如TiN)。當障壁層230在接觸孔226與周邊 孔228中被形成時，障壁層230的厚度較好約是700A。較 好使用一典型的濺鍍或CVD方法形成下障壁層230a與上障 壁層230b。 障壁層230較好被用來減少電極的接觸電阻，並且改 進在導電材料與氧化層224之間的黏著性。障壁層230在其 後程序中移除導電材料期間可被用作中止層。 參考第15圖，一第一導電層232(例如第一鎢層）在半 導體基材220之表面上以及在接觸孔226與周邊孔228中被 形成。因為周邊部分（P)中的周邊孔具有比單元部分（C)中 的接觸孔226大的直徑，所以周邊孔228不會被第一導電層 232完全地填滿，僅有其底部與側壁被覆蓋。 參考第16圖，包括第一導電層232的半導體基材220被 置放在旋轉夾具212上，如第9圖所示。接著，藉由旋轉旋 轉夾具212上的半導體基材並透過一喷嘴214喷灑蝕刻組合 物在半導體基材220與第一導電層上，蝕刻第一導電層232 以形成第二導電層（例如一層第二鎢層）。較佳的是，蝕刻 組合物的供應量為約0.1至2.5升/分鐘，並且蝕刻組合物較 好包含作為一氧化劑重量百分比約為3至55的ΗΝ03、作為 一促進劑重量百分比為0.2至35的HF、及作為一緩衝溶液 具有剩餘重量百分比的去離子水。最佳的是，蝕刻組合物 包含作為一氧化劑重量百分比為10至45的HN〇3、作為一 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------_ (請先閱讀背面之注意事項再填寫本頁) 23 478130 A7 _______ B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（21) 促進劑重量百分比為1至24的HF、及作為一緩衝溶液具有 剩餘重量百分比的去離子水。處理溫度較佳的範圍是從約 20至90°C ’並且最好是從約30至7〇°c。旋轉夾具212的旋 轉速度較好是在從約200至5000rpm的範圍中，最好是從 約 1000至 300〇rpm。 較好是A氣體之經加熱氣體被供應至半導體基材的 後側’較佳是在約30至150°C的溫度下，以便減少在蝕刻 組合物與半導體基材220之間的溫度差，而改善蝕刻過程 的均勻度。第一導電層232的蝕刻速率較好是在從70至 22000A/min。處理時間會依據第一導電層232的厚度而變 化，並且可以根據處理條件而被調整。第一導電層經 姓刻的厚度（即被餘刻掉的第一導電層232之部分的厚度） 車父好約是第一導電層232厚度的40至95%，最好是在約70 至90%的範圍中。 參考第17圖，導電鎢層233接著被蝕刻，以便藉由旋 轉方疋轉炎具212上的半導體基材220，並透過一喷嘴214在 半導體基材220與第二導電層上噴灑蝕刻組合物來形成一 導電插塞235。較佳地，此程序用之供應量約為〇1至2 升/分鐘，並且蝕刻組合物較好包含作為一氧化劑重量 分比為0.2至30的Η"2、作為一促進劑重量百分比為〇〇1 至30的ΝΗβΗ、及作為一緩衝溶液具有剩餘重量百分 的去離子水。更好的是，蝕刻組合物包含作為一氧化劑 畺百分比為1·0至30的H2〇2、作為一促進劑重量百分比 0·01至29的NH4QH、及作為-緩衝溶液具有剩餘重量百分 5 百 比重為 (請先閱讀背面之注意事項再填寫本頁) . -線· 本紙張尺度適用中國國家谭準（CNS)A4規格（210 X 297公釐） 24 經濟部智慧財產局員工消費合作社印·製 478130 A7 ____ B7 五、發明說明（22 ) 比的去離子水。 一較替的較佳蝕刻組合物包含作為一氧化劑重量百分 比為0.01至30的ΗΝ03、作為一促進劑重量百分比為001至 3.0的NHJ、及作為一緩衝溶液具有剩餘重量百分比的去 離子水。 處理溫度較好是在約20至9(TC的範圍中，最好是約30 至70°C ’並且旋轉夾具212的旋轉速度較好是在從約2〇〇至 5000rpm的範圍中。較好是在3〇至i5〇〇c的溫度下例如 氣體之經加·熱氣體被供應至半導體基材22〇的後側，以便 減少在蝕刻組合物與半導體基材220之間的溫度差，藉此 改善蝕刻過程的均勻度。第二導電層233的蝕刻速率較好 是在約300至12000人/min的範圍中。處理時間根據第二導 電層233的厚度而變化，並且可以根據處理條件而被調整。 在此CEP姓刻程序中，在周邊孔中與在周邊孔228中 之部分的障壁層230中之第二導電層233被CEP程序移除。 此外，在單元部分中的氧化層224之頂部表面上的部分障 壁層230亦被CEP程序移除。因為周邊孔228比包含導電插 塞235的接觸孔226大，因此姓刻組合物足以進到周邊孔228 中，以從周邊孔228移除第二導電層233與障壁層230。 另一方面，第二導電層233與障壁層230之移除步驟可 以被進行成兩個連續的階段’即首先移除第二導電層233， 接著移除障壁層230。 如上所述，導電插塞形成程序較好被分成兩個步驟。 第一個步驟為高蝕刻速率步驟，係使用一較好具有一高姓 本紙張尺度適用中國國家镡準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 25 478130 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（23) …· 刻速率之第一蝕刻成份，例如包含HF與hn〇3，被用來蝕 刻第一導電層232厚度的40至95%。接著，一第二步驟為 低姓刻速率步驟，係使用較好具有低姓刻速率之飯刻組合 物，例如包含，札〇2與NH4〇h或1^〇3與1^11/，被用使以 便姓刻第二導電層233之剩餘部分。由於此程序的結果， 導電插塞235被形成使得被沉積作為一第一導電層之導電 材料僅留在接觸孔226之内。 此外，為了形成導電插塞235，第一導電層232的移除 可以透過使用多重步驟而被進行。 根據本發明所製造的半導體元件包含一個包括一導電 插塞之單元區域，以及一個包括一欲被用作一對正記號或 刻劃線之周邊孔圖樣的周邊區域。周邊孔圖樣較好藉由與 導電插塞用之接觸孔圖樣形成程序相同的程序來被形成， 並且沒有導電物質留在周邊孔中的周邊孔圖樣。 此外，根據本發明，可能形成具有例如堆積結構之多 重結構的半導體元件。 第18圖是顯示由一個根據本發明第一較佳實施例之製 造半導體元件之方法所產生的多重結構圖。如第18圖所 示，一個所欲的多重結構（包括三層結構F、8與丁）可以藉 由重複執行插塞形成程序來被創造，一種不可能使用一傳 統CMP程序的處境。在此多重結構中，—層第二層結構⑻ 在一第一層結構（F)上被形成，並且一層第三層結構（1)被 形成在第二層結構上。此多重結構可以在沒有於低層上執 行平面化程序的情況下被有效地創造。此外，多重層結構 (請先閱讀背面之注意事項再填寫本頁) 訂丨 線· 26 經濟部智慧財產局員工消費合作社印製 478130 A7 B7 五、發明說明（24) 未被限制於如第18圖所示之三層結構，可以不同層數進行 變化。 總而言之，上述方法可以被用來形成導電插塞，以及 在一具有多層結構之半島體基材上形成導電線。由於此方 法之結過，半導體元件製程可以被簡化，藉此改進製造過 程的產率。 第^較佳實施例 當半導體元件變得更高度整合積集蝕，接觸孔的深度 變得更深且接觸孔的直徑變得更小。結果，以薄層遮蓋接 觸孔已變得更困難。所以，一墊應該在有接觸孔被形成之 部分上被形成，以使接觸孔的深度減小因而改進接觸孔的 輪靡。 第19至23圖是顯示使用根據本發明第二較佳實施例之 製造半導體元件方法與一多晶石夕插塞一起之單元塾形成程 序之橫截面圖。 參考第19圖，一層第一介電層258在複數個被形成在 半導體基材250上的閘極電極256上被形成。閘極電極256 被相互隔開並且被間隙壁254包圍。在半導體基材250上的 早元被溝渠隔離區域252分成一^固主動區域與一個非主動 區域。當在閘極電極256之間形成單元墊時，第一介電層258 在單元墊之間絕緣。第一介電層258較好是硼磷矽玻璃 (BPSG)層。 參考第20圖，第一介電層258較好被CMP程序平面 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） -------------裝--------訂---------綠 (請先閱讀背面之注意事項再填寫本頁) 27 478130 A7 B7 五、發明說明（25) 化，以形成一第二介電層259。 參考第21圖，接觸孔260接著在經平面化的第二介電 層259中被形成。在此程序中，一光阻（未顯示）被塗覆在 經平面化的第二介電層259上；一光阻圖樣藉由使用典型 的微影程序被形成；以及接觸孔260藉由使用光阻圖樣作 為一蝕刻罩幕之蝕刻程序而被形成。光阻罩幕接著被移 除。 參考第22圖，一層導電層262(例如一多晶石夕層）在第 二介電層259上以一定的厚度被形成，以遮蓋接觸孔260。 參考第23圖，包括導電層262被形成於其上的半導體 基材250被置放在旋轉夾具212上，如第9圖所示。導電層262 接著藉由旋轉旋轉夾具212並在半導體基材250上透過一喷 嘴214噴灑蝕刻組合物來被蝕刻，以移除在第二導電層259 上之部分的導電層262，而僅留下被形成在接觸孔260中的 導電插塞（例如多晶碎插塞）。 在此程序中，蝕刻組合物之供應量較好是從0.1至2.5 升/分鐘。餘刻組合較好包含作為一氧化劑重量百分比為3 至60的HN〇3、作為一促進劑重量百分比為0.06至30之HF、 以及作為一緩衝溶液具有剩餘重量百分比的去離子水。更 好的是，姓刻組合物包含作為一氧化劑重量百分比為8至45 的HN〇3、作為一促進劑重量百分比為0.3至12的HF、以及 作為一緩衝溶液具有剩餘重量百分比的去離子水。餘刻組 合物的溫度較好是在20至9(TC的範圍中。旋轉夾具212的 旋轉速度較好是在從200至5000rpm的範圍中。 本紙張尺度適用中國國家槔準（CNS)A4規格（210 X 297公釐） 請 先， 閱 讀 背· 面 之 注 意 事 項 再 填丨 寫 本 頁 訂 線 經濟部智慧財產局員工消費合作社印製 28 經濟部智慧財產局員工消費合作社印製 478130 A7 _______B7 五、發明說明（26) 導電層262所得的蝕刻速率較好是在從3〇至⑼ 人/min的範圍中。處理時間依據導電層加的厚度而變化， 並且可以根據處理條件而作調整。 由此程序所形成的導電插塞263可以在其後的程序中 被用作一單元塾。 第三較佳實施例 當半導體元件變得更高整合積極度並包括多重層時， 在用以形成元素圖樣之單元部分與在單元部分間的周邊部 分之間的階梯咼度增加。由於此增加的階梯高度之結果， 因為於微影中之曝光用的上部分與下部分之間準確定焦點 上的困難度，所以得到一個精確的圖樣形成會是困難的。 因此，平面化方法逐漸變得重要，以將階梯高度減到最小。 第24至28圖是顯示使用根據本發明第三較佳實施例之 製造半導體元件之方法的平面化程序之橫截面圖。第以圖 顯示一半導體元件之第一階梯高度（Ηι)，該半導體元件係 具有一被形成於一半導體基材270上之電容器電極272。階 梯高度（HJ存在於元素圖樣用之單元部分（c)與一周邊部 分（P)之間。 第25圖為顯示作為一間層介電層之第一氧化層被 形成在半導體基材270上之橫截面圖。因為第一階梯古产 (仏）’所以第一氧化層274在單元部分（c)與周邊部分之間 (p)亦會具有一第二階梯高度（h2)。 第一與第二階梯高度（心與仏)會在其後的程序中造成 -------------裝----I---訂---------線 (請先閱讀背面之注意事項再填寫本頁) 29 經濟部智慧財產局員工消費合作社印製 478130 Α7 _______ Β7 五、發明說明（27) 操作故障，因為階梯高度（仏與札)使用以形成元素圖樣之 微影程序難於精確地定焦點。 第氧化層274最好是一層BPSG層，但其不被限制於 此材料。第一氡化層274較好被CVD方法形成，且更好藉 由低壓化學氣相沉積（LPCVD)方法形成。藉由此程序，一 均勻層可以被沉積。 第26圖是顯示第二氧化層275被由一流動平面化第一 氧化層形成之橫戴面圖。為實現此點，第一氧化層274以 一兩溫下被流動平面化，較好超過750°C，以將第二階梯 高度（H2)減至最小。在流動平面化之後，在單元部份中的 第二氧化層275的厚度（LJ比第一氧化層274的厚度小。換 言之，第二氧化層275之第三階梯高度（仏）比第一氧化層 274的第二階梯高度（H2)小。所以，用以形成第三階梯高 度㈤之第一角度（01)是小的。然而，上述的高溫流動平 面化程序具有限制。 第27圖是顯示第三氧化層276可以藉由使用一旋轉蝕 刻方法平面化第二氧化層275被形成之橫截面圖。 使用此方法，一具有經流動平面化之第二氧化層275 的半導體基材270被置放在旋轉夾具212上，如第9圖所示。 接著，藉由旋轉半導體基材270與旋轉夾具212，並藉由透 過喷嘴214將蝕刻組合物喷灑至半導體基材27〇上，第二氧 化層275被餘刻。 在此程序中，蝕刻組合物較好具有約〇1至2·5升/分鐘 的供應量。蝕刻組合較好包含作為一氧化劑重量百分比為 --------§1 (請先閱讀背面之注意事項再填寫本頁) ·. -線·15 478130 A7 ______________ B7 V. Description of the Invention (13)… It can be moved to the left or right of the rotating jig 212, and the etching composition is supplied to the semiconductor substrate 21. One of the nozzles 214 is also preferably used for a cleaning solution such as deionized water. A tub 213 is provided to cover the rotating jig 212 and to prevent the etching composition from flowing out during processing. The n2 gas supplied through the gas line 219 is supplied to the turning jig 212 'to lift the semiconductor substrate 21 about 2 mm. The N2 gas system is useful for specifically treating the rear side of the semiconductor substrate 212. The preferred rotary etching apparatus disclosed in Figure 9 uses a heater 216 to control the temperature of the gas. In addition, the device has another heater (not shown) to control the temperature of the etching composition. Although A gas is used in the first preferred embodiment to heat the semiconductor substrate 210, another gas may be used. However, it is preferable that the gas used is an inert gas so that the gas itself does not interfere with the etching process. The temperature of the composition printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is preferably from 20 to 90. (: In the range. More preferably, the temperature of the last engraved composition is in the range from 30 to 70.0 to accelerate the etching rate of the material layer on the semiconductor substrate. The preferred temperature of the gas is also In a range from 30 to 70 ° C, the semiconductor substrate 210 on the rotating jig 212 is heated. If the semiconductor substrate 21 is not heated while the etching composition is heated, the semiconductor substrate 21 and the semiconductor substrate 21 are not heated. The temperature difference of the etching composition will cause different etching rates on all material layers (for example, copper, copper, polycrystalline silicon, silicon oxide, silicon nitride). This in turn can lead to semiconductor-based substrates after the engraving process. The uneven surface of the material 21 °. In one operation, the etching composition is supplied from the nozzle 214 to the semiconductor. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). Printing 478130 Α7 Β7 V. Description of the invention (14) The temperature of the substrate 210 will change, that is, it will become cold, and it will be spread on the surface of the semiconductor substrate 210. Because the temperature of the composition at the moment will flow with it Changes, so its temperature will change at every point on the surface of the semiconductor substrate 210. In other words, the temperature of the etching composition applied to the semiconductor substrate 210 will change across all contact points on the surface of the semiconductor substrate 210. As a result of this temperature difference, a portion of the semiconductor substrate 21 where the composition is first applied / contacted is higher than a portion of the semiconductor substrate 210 which is supplied / contacted later than the etching composition. The etching rate will also vary depending on the flow of the etching composition over the entire surface of the semiconductor substrate 21. These etching changes will be more severe for larger diameter semiconductor wafers, such as 300 mm diameter wafers. Wafer, so the large temperature difference of the etching composition really occurs across the surface of the semiconductor wafer. Therefore, the concept of the present invention teaches various methods to provide uniform processing conditions, such as supplying heated N2 gas to the substrate, The rotating fixture 212 is provided with a heater, a type containing a rotary etching processing chamber or enclosed in a closed, temperature-controlled, processing ring The supply speed of the etching composition is preferably about 0-1 to 2.5 liters / minute, and the etching composition can be supplied to the semiconductor substrate 210 by swinging the spray rod to varying degrees. Center to the right or left. The boom swing table is not the movement range of the nozzle 214 that supplies the etching composition on the semiconductor substrate 21. For reference purposes, the boom swing from the semiconductor center to the left is considered negative (_), and From the center of semiconductor substrate 21 to this paper size, China National Standard (CNS) A4 specification (210 X 297 public love) is applied. --------- (Please read the precautions on the back before filling out this page) 17 478130 A7 B7 V. Description of the Invention (I5) The swing of the boom on the right is considered positive. For the preferred embodiment described in this disclosure, the boom swing is given in units of mm. The swing movement range of the spray bar of the present invention is preferably from 0 to + / _ g0. In other words, it is preferable that the nozzle 214 supplies the etching composition while moving to the left or right side of the center of the semiconductor substrate 21 80 mm. Because boom swing is a parameter that affects the etch uniformity of the thin layer to be etched, boom swing for a given CEP process should be optimized. The boom swinging should preferably be performed by both a long-distance boom swing and a short-distance boom swing, which are performed sequentially. A long-distance boom swing is when the nozzle 214 is moved across a long distance boom, for example, up to the maximum possible swing of the nozzle 214. A short-distance boom swing is the shortest boom swing that has been moved across a longer boom, such as some that may be less than the maximum possible swing of the nozzle 214. Figure 10 (a) shows a graphical representation of the #engraving rate according to the pendulum swinging across various positions in the substrate 21o. The figure shows the etching rate when an tungsten layer is etched using an etching composition containing a mixture of HNO3 as an oxidizing agent, HF as a promoter, and deionized water as a buffer solution. Line C shows the remaining moment rate when the surname composition is supplied on the semiconductor substrate with a nozzle 2 J 4 fixed on the center of the semiconductor substrate. As shown by line c, in this case, the etching rate at the central portion of the semiconductor substrate 21o is relatively higher than the etching rate at the peripheral edge of the semiconductor substrate 21o. Line D is improperly displayed for a long-distance boom swinging nozzle 214. Applies to China National Standard Tan (CNS) A4 (210 X 4 7 mm) at half the paper size. (Please read the precautions on the back before filling in this Page) · Printed by the Consumers 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 1X 8 47 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ________B7___ V. Description of the Invention (16) '' When the etching composition is supplied on the conductor substrate Etching rate. As shown by line D, in this case, the etching rate at the peripheral edge of the semiconductor substrate 21 is relatively higher than the etching rate at the center portion of the semiconductor substrate. Line E shows the etching rate when the nozzle 214 of a long-distance boom swing and a short-distance spray cup swing is sequentially supplied on the semiconductor substrate. As shown by line E, in this case, the etching rates at the peripheral edge and the center of the semiconductor substrate 210 are almost similar. Fig. 11 is a graphic representation showing an etching rate and an etching uniformity according to various boom swings. This figure shows the etch rate when an tungsten layer is etched using an etching composition containing a mixture of HN03 as an oxidizing agent, iNHj as a promoter, and deionized water as a buffer solution. In particular, the bar graph shows the etch rate, and the line F shows the etch uniformity. The branch etch rate shown in the bar graph of Fig. 11 represents the thickness of a thin layer to be etched by an etching solution for a certain period of time. The uniformity of the etching shown by the line F in the n-th figure indicates the deviation of the thicknesses at a plurality of thin layer points after the etching is completed, such as a center point, an edge point, and an intermediate point. Therefore, the lower the deviation between the points shown, the more uniform the resulting surname engraving. As shown in Fig. 11, when the long-distance boom swing and the short-distance boom swing are performed sequentially and continuously, the etching rate is increased and the etching uniformity is improved. When the boom swing is -20 ~ 0, the etching rate is about 54.0 A / min, which is sufficient to meet the processing conditions. However, the uniformity is about 10%, which is too high. When the boom swing is -40 ~ 0, the etching rate is reduced to an unsuitable level, and the unevenness is increased to an even more unacceptable amount. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------- Installation -------- Order ------ --- Turn (Please read the precautions on the back before filling this page) 19 478130 A7 B7 V. Description of the invention (17) However, when the boom swing is performed in the order of -40 ~ 0 and -20 ~ 0, The remaining rate is about 540 persons / min and the uniformity of the last name is about 1%. The foregoing two are acceptable for the processing conditions. This means that line E in Fig. 10 can be obtained by processing conditions of lines D and C. In addition, according to a preferred embodiment of the present invention, when a part of the thin layer on the semiconductor substrate requires greater etching, the nozzle 214 supplying the etching composition is allowed to stay longer, and the etching composition is allowed to The portion to be etched is supplied for a longer period of time. The rotation speed of the rotary jig is preferably in the range of 200 to 5000 when the rotational speed (rpm) is supplied while the etching composition is supplied. A method for manufacturing a semiconductor element using an etching composition is described below based on a preferred embodiment, but the present invention should not be limited to the following embodiments. First Preferred Embodiment A first preferred embodiment of a method for manufacturing a semiconductor element to form a conductive plug by a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs will now be described. This embodiment provides a new method to form an interconnected conductive plug without micro scratches on the surface caused by the CMP process and without increasing the contact resistance caused by the dry etch-back process. According to the present invention, a semiconductor device is manufactured. The method includes the following steps: forming a dielectric layer on a semiconductor substrate, forming a contact hole in the dielectric layer, forming a conductive layer on the dielectric layer and filling the contact hole, rotating the semiconductor substrate, and etching Composition supply dry-rotated semiconductor substrate This paper is sized for China National Standards (CNS) A4 (210 X 297 mm). 20 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 478130 A7 ______ B7 V. Description of the invention (18) On. The etching composition preferably includes a mixture of at least one selected from the group consisting of H202, 02, 1104, Bγ0, cl03, S2008, KIO3, H5IO6, KOH and HNO3 in a certain mixing ratio. An oxidant of a group consisting of at least one promoter selected from the group consisting of HF, NHWH, HJO4, h2S04, NH4F and HC1, and a mixture of a buffer solution so that the material of the conductive layer remains in contact only after etching The inside of the hole without remaining on top of the dielectric layer. The conductive layer is preferably a crane layer (W) or a copper layer (Cu). The conductive plug preferably connects one upper conductive layer and one lower conductive layer through a contact hole formed in the dielectric layer. During the formation of the conductive plug, a semiconductor substrate 210 having a conductive layer formed thereon is preferably mounted on a rotatable rotary jig 212 and rotated at a certain rate. By supplying an etching composition through a nozzle 214 disposed on the semiconductor substrate 21o, the conductive layer on the semiconductor substrate 210 is then etched so that the conductive layer remains only within the contact hole without Will remain on the dielectric layer. In other words, the conductive layer interlayer is etched by the increasing momentum in the horizontal direction and the etching composition that has a good reaction with the conductive layer, which is the semiconductor substrate 21 caused by the rotation of the rotating jig 214 〇 born of centrifugal force. The higher the rotation speed of the rotating jig 214, the more the etching momentum will increase in the horizontal direction. As a result, by this process, the etching speed and etching uniformity of the conductive layer are improved, and the generation of unnecessary voids formed on the conductive layer is avoided. Paper size applies to China National Standard (CNtS) a4 specifications (210 X 297 meals 1 1 " '---- ------------- installation -------- order- -------- Green (Please read the notes on the back before filling this page) 21 478130 A7 B7 V. Description of the invention (19) The step of supplying the etching composition to the semiconductor substrate is preferably two steps The first step includes supplying a first substance including a first etch composition having a first etch rate. The second step includes supplying a second substance including a second etch rate that is lower than the first etch rate. Etching composition. FIGS. 12 to 17 are cross-sectional views showing a processing sequence of a tungsten plug formation process using the method of manufacturing a semiconductor element according to the first preferred embodiment of the present invention. These drawings show conductive plugs ( (For example, tungsten plugs) and a pair of positive marks or scribe lines. In these drawings, a unit part (C) for forming a circuit pattern and a mark or scribe for alignment are shown. The peripheral portion (P) of the line. Referring to FIG. 12, an oxide film 224 is on the semiconductor substrate 220. It is formed, which has a plurality of partial patterns 222 formed thereon at a distance from each other. The partial pattern 222 is preferably a polycrystalline silicon pattern or a metal pattern as a low conductive layer. The oxide layer 224 may be a layer of dioxide Silicon layer (Si02), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG), or the like, which is preferably a typical CVD method or a spin-on-glass (SOG) method. Oxide layer 224 The thickness is preferably about 4,000 to 15,000 people. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a reference to Figure 13, a photoresist (not shown) was coated on the oxide layer 224, and a conventional lithography process was used. A pattern (not shown) is formed. A portion of the oxide layer 224 is engraved by a conventional engraving process to form a contact hole 226 and a peripheral hole 228 that is used as a pair of positive marks or scribe lines. The hole 228 preferably has a larger diameter than the contact hole 226. Referring to FIG. 14, a barrier layer 230 (such as a double Ti / TiN layer) is better. The paper size is applicable to China National Standard (CNS) A4 (210 x 297). Mm) 22 Ministry of Economy Wisdom Printed by the Consumer Cooperative of the Bureau of Production and Industry 478130 A7 B7 V. Description of the invention (20) It is formed in the potential contact hole 226 and the peripheral hole 228 where the conductive layer is deposited. The barrier layer 230 preferably includes a lower barrier layer 230a (such as Ti) And an upper barrier layer 230b (such as TiN). When the barrier layer 230 is formed in the contact hole 226 and the peripheral hole 228, the thickness of the barrier layer 230 is preferably about 700 A. A typical sputtering or CVD method is preferably used A lower barrier layer 230a and an upper barrier layer 230b are formed. The barrier layer 230 is preferably used to reduce the contact resistance of the electrode and improve the adhesion between the conductive material and the oxide layer 224. The barrier layer 230 may be used as a stop layer during the subsequent removal of the conductive material. Referring to FIG. 15, a first conductive layer 232 (e.g., a first tungsten layer) is formed on the surface of the semiconductor substrate 220 and in the contact holes 226 and the peripheral holes 228. Because the peripheral hole in the peripheral portion (P) has a larger diameter than the contact hole 226 in the unit portion (C), the peripheral hole 228 will not be completely filled by the first conductive layer 232, and only the bottom and sidewalls thereof will be filled. cover. Referring to FIG. 16, a semiconductor substrate 220 including a first conductive layer 232 is placed on a rotating jig 212, as shown in FIG. Next, the semiconductor substrate on the rotating fixture 212 is rotated and the etching composition is sprayed through a nozzle 214 on the semiconductor substrate 220 and the first conductive layer, and the first conductive layer 232 is etched to form a second conductive layer (for example, a layer Second tungsten layer). Preferably, the supply amount of the etching composition is about 0.1 to 2.5 liters / minute, and the etching composition preferably contains ΝΝ03 as an oxidant in a weight percentage of about 3 to 55, and as a promoter in a weight percentage of 0.2 to 35. HF, and deionized water with a remaining weight percentage as a buffer solution. Most preferably, the etching composition contains HN03 as an oxidizing agent with a weight percentage of 10 to 45, and as a paper size, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied ------ ------- Installation -------- Order ---------_ (Please read the notes on the back before filling this page) 23 478130 A7 _______ B7 Intellectual Property Bureau, Ministry of Economic Affairs Printed by the Employee Consumption Cooperative. V. Description of the Invention (21) HF with a promoter weight percentage of 1 to 24, and deionized water with a remaining weight percentage as a buffer solution. The preferred processing temperature is from about 20 to 90 ° C 'and most preferably from about 30 to 70 ° C. The rotation speed of the rotary jig 212 is preferably in a range from about 200 to 5000 rpm, and most preferably from about 1,000 to 300 rpm. Preferably, the heated gas of A gas is supplied to the rear side of the semiconductor substrate ', preferably at a temperature of about 30 to 150 ° C in order to reduce the temperature difference between the etching composition and the semiconductor substrate 220, And improve the uniformity of the etching process. The etching rate of the first conductive layer 232 is preferably from 70 to 22000 A / min. The processing time varies depending on the thickness of the first conductive layer 232, and can be adjusted according to the processing conditions. The thickness of the first conductive layer engraved by the last name (that is, the thickness of the part of the first conductive layer 232 that has been engraved). The rider is about 40 to 95% of the thickness of the first conductive layer 232, and preferably about 70 to In the 90% range. Referring to FIG. 17, the conductive tungsten layer 233 is then etched, so that the semiconductor substrate 220 on the inflammation tool 212 is transferred by rotating the square, and the etching composition is sprayed on the semiconductor substrate 220 and the second conductive layer through a nozzle 214. To form a conductive plug 235. Preferably, the supply amount for this procedure is about 0.01 to 2 liters / minute, and the etching composition preferably contains Η as an oxidant in a weight ratio of 0.2 to 30, and ² as a promoter in a weight percentage of 0. Νββ30 of 0 to 30, and deionized water with a remaining weight percentage as a buffer solution. More preferably, the etching composition contains H20 as an oxidant with a hafnium percentage of 1.0 to 30, NH4QH as a promoter weight percentage of 0.01 to 29, and as a buffer solution having a remaining weight percentage of 5 The percentage is (Please read the precautions on the back before filling this page). -Line · This paper size is applicable to China National Tan Zhun (CNS) A4 specification (210 X 297 mm) 24 Printed by the Intellectual Property Bureau Staff Consumer Cooperatives · Manufacture 478130 A7 ____ B7 V. Description of the invention (22) Deionized water. An alternative preferred etching composition comprises ΝΝ03 as an oxidant in a weight percentage of 0.01 to 30, NHJ as a promoter in a weight percentage of 001 to 3.0, and deionized water with a remaining weight percentage as a buffer solution. The processing temperature is preferably in a range of about 20 to 9 ° C., preferably about 30 to 70 ° C. and the rotation speed of the rotary jig 212 is preferably in a range of about 2000 to 5000 rpm. It is at a temperature of 30 to 500 ° C. For example, heated gas is supplied to the rear side of the semiconductor substrate 22o to reduce the temperature difference between the etching composition and the semiconductor substrate 220. This improves the uniformity of the etching process. The etching rate of the second conductive layer 233 is preferably in a range of about 300 to 12,000 people / min. The processing time varies according to the thickness of the second conductive layer 233, and can be changed according to the processing conditions. In this CEP last engraving process, the second conductive layer 233 in the barrier layer 230 in the peripheral hole and a part in the peripheral hole 228 is removed by the CEP process. In addition, the oxide layer 224 in the cell part Part of the barrier layer 230 on the top surface of the top surface was also removed by the CEP procedure. Because the peripheral hole 228 is larger than the contact hole 226 containing the conductive plug 235, the composition of the engraving is sufficient to enter the peripheral hole 228 to pass from the peripheral hole 228. The second conductive layer 233 and the barrier layer 230 are removed. On the one hand, the step of removing the second conductive layer 233 and the barrier layer 230 may be performed in two consecutive stages, that is, the second conductive layer 233 is first removed, and then the barrier layer 230 is removed. As described above, the conductive plug The forming process is preferably divided into two steps. The first step is a high etch rate step, which uses a better paper size with a high surname and applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)- ------------ Installation -------- Order --------- line (please read the precautions on the back before filling this page) 25 478130 Ministry of Economy Wisdom Printed by A7 B7, Consumer Cooperative of the Property Bureau. 5. Description of the Invention (23)…. The first etching component at the etch rate, such as HF and HNO3, is used to etch 40 to 95% of the thickness of the first conductive layer 232. Next, a second step is a low-lasting engraving rate step, which uses a rice-engraving composition that preferably has a low lasting engraving rate. The remaining part of the second conductive layer 233 is engraved. As a result of this procedure, the conductive plug 235 is formed so as to be deposited as a first conductive layer. The layer of conductive material remains only within the contact hole 226. In addition, in order to form the conductive plug 235, the removal of the first conductive layer 232 can be performed by using multiple steps. A semiconductor device manufactured according to the present invention includes a semiconductor device including A cell area of a conductive plug, and a peripheral area including a peripheral hole pattern to be used as a pair of positive marks or scribe lines. The peripheral hole pattern is preferably formed by a contact hole pattern forming procedure with the conductive plug. The same procedure is used to form a peripheral hole pattern without a conductive substance remaining in the peripheral hole. Further, according to the present invention, it is possible to form a semiconductor element having a multiple structure such as a stacked structure. Fig. 18 is a diagram showing a multiple structure produced by a method of manufacturing a semiconductor device according to a first preferred embodiment of the present invention. As shown in Figure 18, a desired multiple structure (including the three-layer structure F, 8 and D) can be created by repeatedly executing the plug-forming procedure, a situation where it is impossible to use a traditional CMP procedure. In this multiple structure, a layer of the second layer structure 形成 is formed on a first layer structure (F), and a layer of the third layer structure (1) is formed on the second layer structure. This multiple structure can be efficiently created without performing a flattening procedure on the lower layers. In addition, the multi-layer structure (please read the precautions on the back before filling out this page) Ordering · 26 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 478130 A7 B7 V. Description of the invention (24) is not limited to as in Section 18 The three-layer structure shown in the figure can be changed with different layers. In summary, the above method can be used to form conductive plugs and to form conductive wires on a peninsula substrate having a multilayer structure. As a result of this method, the manufacturing process of semiconductor devices can be simplified, thereby improving the yield of the manufacturing process. Third Preferred Embodiment As the semiconductor device becomes more highly integrated and integrated, the depth of the contact hole becomes deeper and the diameter of the contact hole becomes smaller. As a result, it has become more difficult to cover the contact holes with a thin layer. Therefore, a pad should be formed on the portion where the contact hole is formed, so that the depth of the contact hole is reduced and thus the contact hole is improved. 19 to 23 are cross-sectional views showing a cell formation process using a method for manufacturing a semiconductor device according to a second preferred embodiment of the present invention together with a polycrystalline silicon plug. Referring to FIG. 19, a first dielectric layer 258 is formed on a plurality of gate electrodes 256 formed on a semiconductor substrate 250. The gate electrodes 256 are spaced apart from each other and surrounded by a partition wall 254. The early element on the semiconductor substrate 250 is divided by a trench isolation region 252 into a solid active region and a non-active region. When a cell pad is formed between the gate electrodes 256, the first dielectric layer 258 is insulated between the cell pads. The first dielectric layer 258 is preferably a borophosphosilicate glass (BPSG) layer. Referring to FIG. 20, the first dielectric layer 258 is preferably used by the CMP process. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm). ------ Order --------- Green (Please read the notes on the back before filling this page) 27 478130 A7 B7 V. Description of the invention (25) to form a second dielectric Layer 259. Referring to FIG. 21, a contact hole 260 is then formed in the planarized second dielectric layer 259. In this procedure, a photoresist (not shown) is coated on the planarized second dielectric layer 259; a photoresist pattern is formed by using a typical lithography process; and a contact hole 260 is used by The photoresist pattern is formed as an etching process of an etching mask. The photoresist mask is then removed. Referring to FIG. 22, a conductive layer 262 (such as a polycrystalline silicon layer) is formed on the second dielectric layer 259 with a certain thickness to cover the contact hole 260. Referring to FIG. 23, a semiconductor substrate 250 including a conductive layer 262 formed thereon is placed on a rotating jig 212, as shown in FIG. The conductive layer 262 is then etched by rotating the rotating fixture 212 and spraying the etching composition through a nozzle 214 on the semiconductor substrate 250 to remove a portion of the conductive layer 262 on the second conductive layer 259, leaving only the A conductive plug (for example, a polycrystalline crush plug) is formed in the contact hole 260. In this procedure, the supply amount of the etching composition is preferably from 0.1 to 2.5 liters / minute. The remaining combination preferably includes HNO3 as an oxidizing agent in a weight percentage of 3 to 60, HF as a promoter in a weight percentage of 0.06 to 30, and deionized water having a remaining weight percentage as a buffer solution. More preferably, the composition includes HN03 as an oxidant in a weight percentage of 8 to 45, HF as a promoter in a weight percentage of 0.3 to 12, and deionized water with a remaining weight percentage as a buffer solution. . The temperature of the remaining composition is preferably in the range of 20 to 9 ° C. The rotation speed of the rotary jig 212 is preferably in the range of 200 to 5000 rpm. This paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) Please read the notes on the back and fill in this page. 丨 Write this page. Printed on the printed page by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Explanation of the invention (26) The etching rate obtained by the conductive layer 262 is preferably in a range from 30 to ⑼ / min. The processing time varies depending on the thickness of the conductive layer, and can be adjusted according to the processing conditions. The conductive plug 263 formed by this process can be used as a unit in subsequent processes. Third preferred embodiment When a semiconductor device becomes more integrated and includes multiple layers, it is used to form an element The step angle between the cell portion of the pattern and the peripheral portion between the cell portions is increased. As a result of this increased step height, the upper portion for exposure in the lithography is increased. It is difficult to accurately determine the focus from the lower part, so it can be difficult to obtain an accurate pattern. Therefore, the planarization method has gradually become important to minimize the height of the steps. Figures 24 to 28 show the A cross-sectional view of a planarization process using a method of manufacturing a semiconductor device according to a third preferred embodiment of the present invention. The figure shows a first step height (Ηι) of a semiconductor device having a A capacitor electrode 272 on a semiconductor substrate 270. The step height (HJ exists between the cell portion (c) and a peripheral portion (P) for the element pattern.) Figure 25 shows the first layer as a dielectric layer. A cross-sectional view of an oxide layer formed on the semiconductor substrate 270. Because of the first step ancient product (仏) ', the first oxide layer 274 will also have a distance between the cell portion (c) and the peripheral portion (p). The height of the second step (h2). The height of the first and second steps (heart and tadpoles) will cause ------------- installation ---- I --- Order --------- Line (Please read the precautions on the back before filling out this page) 29 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 478130 Α7 _______ Β7 V. Description of the invention (27) Operation failure, because the lithography program using step heights (仏 and)) to form element patterns is difficult to accurately focus. 274 is preferably a BPSG layer, but it is not limited to this material. The first halide layer 274 is preferably formed by a CVD method, and more preferably formed by a low pressure chemical vapor deposition (LPCVD) method. By this procedure A uniform layer can be deposited. FIG. 26 is a cross-sectional view showing that the second oxide layer 275 is formed by a flow planarizing the first oxide layer. To achieve this, the first oxide layer 274 is planarized by the flow at one or two temperatures, preferably over 750 ° C, to minimize the second step height (H2). After the flow is planarized, the thickness of the second oxide layer 275 (LJ is smaller than the thickness of the first oxide layer 274 in the cell portion. In other words, the third step height (仏) of the second oxide layer 275 is greater than the first oxide layer 275. The second step height (H2) of the layer 274 is small. Therefore, the first angle (01) used to form the third step height ㈤ is small. However, the above-mentioned high-temperature flow planarization procedure has limitations. Fig. 27 shows The third oxide layer 276 can be formed by using a rotary etching method to planarize the cross-sectional view of the second oxide layer 275. Using this method, a semiconductor substrate 270 having a flow-planarized second oxide layer 275 is placed It is placed on the rotating jig 212, as shown in Fig. 9. Next, the semiconductor substrate 270 and the rotating jig 212 are rotated, and the etching composition is sprayed on the semiconductor substrate 27 through the nozzle 214. The second The oxide layer 275 is etched. In this procedure, the etching composition preferably has a supply of about 0.01 to 2.5 liters / minute. The etching combination preferably includes as an oxidant a weight percentage of ------- -§1 (Please read the note on the back first Items and then Complete this page) * - Line

30 478130 經濟部智慧財產局員工消費合作社印制π A7 ______B7 五、發明說明（28 ) ..... 0.01至60的HN〇3、作為一促進劑重量百分比為〇〇5至25之 HF、以及作為一緩衝溶液具有剩餘重量百分比的去離子 水更好的疋，蝕刻組合物包含作為一氧化劑重量百分比 為〇·〇1至60的HNO3、作為一促進劑重量百分比為〇 5至12 的HF、以及作為一緩衝溶液具有剩餘重量百分比的去離 子水。處理溫度較好是在2〇至9〇〇〇的範圍中，並且旋轉夾 具212的旋轉速度較好是在約2〇〇至5〇〇〇卬爪的範圍中。 第一氧化層275的蝕刻速率較好是在約3〇至52〇〇〇 Α/min的範圍中。處理時間依據第二氧化層2乃的厚度而 變化，並且可以根據處理條件而被調整。 比較第27圖所示之第三氧化層276，其俦與第26圖之 第二氧化層275—起被旋轉蝕刻方法平面化，下列的關係 式疋真貫的。H3>H4、L2>L4、LfL# 0丨> 0 2。結果，第 四階梯高度（Η。與第二角度<9 2都藉由進行因旋轉蝕刻方 法所造成之平面作用而被減至最小。 第四階梯高度（HO可以被進一步減到最小，並且角度 02在旋轉夾具之旋轉速度被增加時變得更小。然而，旋 轉速度具有一限制，且如此旋轉速度的增加範圍被與第二 氧化層275之姓刻組合物足夠的反應之需求而被侷限。被 旋轉姓刻移除之第二氧化層275的厚度是1^2 置。 第28圖為顯示光阻圖樣278在第三氧化層276上被形成 之橫截面圖’其係被旋轉蝕刻方法平面化。光阻圖樣278 在將一光阻沉積在第三氧化層276上並進行一微影程序之 後被形成。 ^ 張尺^適 各⑵〇 x 297 m--- 裝·-------訂·--------_ (請先閱讀背面之注意事項再填寫本頁) 31 478130 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（29) . · 藉由將在第一氧化層274之上位置與下位置之間的階 梯回度（HJ減至最小，在之後的微影程序中的深焦（d〇f) 可以被改善。 研九本發明之較果顯示數個改良。上述本發明之導電 插塞形成方法其特徵在於：此方法使用一種旋轉蝕刻程序 而被進行’該旋轉蝕刻程序藉由採用一種與導電層有良好 反應之蝕刻組合物，並藉由迅速地旋轉半導體基材以便藉 由在水平方向上增加蝕刻動量而進行蝕刻，該蝕刻動量係 借助因半導體基材之高速旋轉而產生的離心力。此與傳統 的CMP方法不同，其中一個拋光裝置透過應用一定的壓 力與供應漿液而與一半導體基材接觸。 本發明提供即使於其形成期間沒有間層介電層平坦化 步驟仍形成足夠品質之導電插塞，因此改善製造過程之產 率〇 此外，在周邊部分之孔圖樣内的導電層，係諸如一對 正記號或是在刻晝線上的各種不平坦圖樣，在CEp程序期 間被完全地移除。此避免在稍後程序中顆粒的產生，並避 免因為漿液所造成在半導體基材上微刮痕的發生，結果改 進微影程序之對正度。根據本發明，蝕刻性質可以藉由調 整半導體基材的旋轉速度、變化蝕刻組合物的供應量、改 變噴灑壓力、變更喷嘴之噴桿擺動等而被容易地改變。 因此，本發明獲得半導體元件製造程序之簡化、增加 的半導體元件之可靠度、並減少處理的花費之優點。 對熟習此技者本發明其他優點與修改將是容易進行 本紙張尺度適用中國國家桿準（CNS)A4規格（210 X 297公爱） --------餐—丨 (請先閱讀背面之注意事項再填寫本頁) 1 - -線· 32 478130 經濟部智慧財產局員工消費合作社印製 A? B? 五、發明說明（30) ’… 者。因此本發明就其廣義態樣而言非僅限於在此顯示與說 明之特定細節與代表性元件。如此可未悖離如隨附之申請 專利範圍所界定之概略發明構想之精髓與範圍及其相當範 圍而做出各種修改。 元件標號對照表 100 半導體基材 102 拋光頭 104 抛光臺 106 漿液供應管線 108 拋光塾 110 半導體基材 112 局部圖樣 114 氧化層 116 接觸孔 118 周邊孔 120 障壁層 120a Ti層 120b TiN層 122 鎢層 123 下部部分 200 旋轉蝕刻裝置 211 馬達 212 旋轉夾盤 213 盆器 214 喷嘴 215 夾具 216 加熱器 217 排泄管 218 調整器 219 队氣體管線 220 半導體基材 222 局部圖樣 224 氧化膜 226 接觸孔 228 周邊孔 230 障壁層 230a 下障壁層 本纸張尺度適用中國國家槔準（CNS)A4規格（210x297公f ) -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) -33 478130 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（31 ) 230b 上障壁層 232 導電層 233 導電鎢層 235 導電插塞 250 半導體基材 252 溝渠隔離區域 254 間隙壁 256 閘極電極 258 介電層 259 第二介電層 260 接觸孔 262 導電層 263 導電插塞 270 半導體基材 272 電容器電極 274 第一氧化層 275 第二氧化層 276 第三氧化層 278 光阻圖樣 (請先閱讀背面之注意事項再填寫本頁) 訂---------線 « 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 3430 478130 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs π A7 ______B7 V. Description of the invention (28) .... HN03 from 0.01 to 60, HF as a promoter weight percentage from 0.05 to 25, And as a buffer solution, the remaining weight percent of deionized water is better. The etching composition contains HNO3 as an oxidant in a weight percentage of 0.001 to 60, and HF as a promoter in a weight percentage of 0.05 to 12. And deionized water with a remaining weight percentage as a buffer solution. The treatment temperature is preferably in a range of 20 to 9,000, and the rotation speed of the rotary clamp 212 is preferably in a range of about 2000 to 50000 claws. The etching rate of the first oxide layer 275 is preferably in a range of about 30 to 520,000 A / min. The processing time varies depending on the thickness of the second oxide layer 2 and can be adjusted according to the processing conditions. Comparing the third oxide layer 276 shown in FIG. 27 and the second oxide layer 275 shown in FIG. 26, they are planarized by the spin etching method. The following relationship is true. H3 > H4, L2 > L4, LfL # 0 丨 > 0 2. As a result, both the fourth step height (Η. And the second angle < 92) are minimized by performing a planar effect due to the rotary etching method. The fourth step height (HO can be further minimized, and The angle 02 becomes smaller as the rotation speed of the rotating jig is increased. However, the rotation speed has a limit, and the increase range of such a rotation speed is required by the need to sufficiently react with the composition of the second oxide layer 275. Limitation. The thickness of the second oxide layer 275 removed by the rotary engraving is 1 ^ 2. Figure 28 is a cross-sectional view showing the photoresist pattern 278 formed on the third oxide layer 276. It is a rotary etch The method is planarized. The photoresist pattern 278 is formed after a photoresist is deposited on the third oxide layer 276 and a lithography process is performed. ^ Zhang ^ ^ each ⑵〇x 297 m --- --- ---- ---- Order · --------_ (Please read the notes on the back before filling out this page) 31 478130 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (29). With the step between the upper and lower positions of the first oxide layer 274 The degree of return (HJ is minimized, and the deep focus (d0f) in the subsequent lithography process can be improved. The research results of the present invention show several improvements. The method of forming the conductive plug of the present invention has the characteristics The reason is that this method is performed using a spin-etching process by using an etching composition that reacts well with a conductive layer, and by rapidly rotating a semiconductor substrate so as to increase etching by horizontally. Etching is performed with momentum, which is based on the centrifugal force generated by the high-speed rotation of the semiconductor substrate. This is different from the traditional CMP method, in which a polishing device contacts a semiconductor substrate by applying a certain pressure and supplying a slurry. The present invention provides a conductive plug of sufficient quality even without an interlayer dielectric layer planarization step during its formation, thereby improving the yield of the manufacturing process. In addition, the conductive layer in the hole pattern in the peripheral portion is, for example, a The alignment marks or various uneven patterns on the graticule are completely removed during the CEp procedure. Avoid this The generation of particles in the process and the avoidance of micro-scratches on the semiconductor substrate caused by the slurry results in improved alignment of the lithography process. According to the present invention, the etching properties can be adjusted by adjusting the rotation speed of the semiconductor substrate, It can be easily changed by changing the supply amount of the etching composition, changing the spraying pressure, changing the nozzle swing of the nozzle, etc. Therefore, the present invention obtains a simplified semiconductor device manufacturing process, increases the reliability of the semiconductor device, and reduces the cost of processing For those skilled in the art, other advantages and modifications of the present invention will be easy to carry out. This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 public love). -------- Meal— 丨 ( Please read the notes on the back before filling out this page) 1--Line · 32 478130 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A? B? V. Description of Invention (30) '... The invention, therefore, in its broader aspects, is not limited to the specific details and representative elements shown and described herein. In this way, various modifications can be made without departing from the essence and scope of the broad invention concept as defined by the scope of the attached application patent and its considerable scope. Component reference table 100 Semiconductor substrate 102 Polishing head 104 Polishing table 106 Slurry supply line 108 Polishing 110 Semiconductor substrate 112 Partial pattern 114 Oxidation layer 116 Contact hole 118 Peripheral hole 120 Barrier layer 120a Ti layer 120b TiN layer 122 Tungsten layer 123 Lower part 200 Rotary etching device 211 Motor 212 Rotating chuck 213 Pot 214 Nozzle 215 Fixture 216 Heater 217 Drain pipe 218 Adjuster 219 Gas line 220 Semiconductor substrate 222 Partial pattern 224 Oxide film 226 Contact hole 228 Peripheral hole 230 Barrier Layer 230a Lower barrier layer This paper size is applicable to China National Standard (CNS) A4 specification (210x297 male f) ------------- Installation -------- Order --- ------ line (please read the precautions on the back before filling this page) -33 478130 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (31) 230b Upper barrier layer 232 Conductive layer 233 Conductive tungsten layer 235 conductive plug 250 semiconductor substrate 252 trench isolation region 254 gap wall 256 gate electrode 258 dielectric layer 259 second dielectric layer 260 contact hole 262 conductive layer 263 conductive Plug 270 Semiconductor substrate 272 Capacitor electrode 274 First oxide layer 275 Second oxide layer 276 Third oxide layer 278 Photoresist pattern (Please read the precautions on the back before filling this page) Order --------- Line «This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 34

Claims (1)

478130 A8 B8 C8 D8 六、申請專利範圍 1· 一種製造半導體元件之方法，係包含： 在一半導體基材上形成一絕緣層； 在該絕緣層中形成多個接觸孔； 在該絕緣層之上形成一導電層以遮蓋該等接觸 孔； 旋轉該半導體基材；以及 藉由在該旋轉的半導體基材上供應一蝕刻組合物 來蝕刻該導電層， 其中該蝕刻組合物包含一種有至少一種選自由 H202、02、I04、Br〇3、C103、s208·、ΚΙ〇3、Η5Ι06、 ΚΟΗ及ΗΝΟ3所組成之基團的氧化劑、至少一種選自 由 HF、NH4OH、H3P04、H2S04、丽4F與 HC1所組成 的基團之促進劑、以及一緩衝溶液之混合物，並且 其中該氧化劑、該促進劑與該緩衝溶液具有一混 合比例，使得在蝕刻之後，該導電層之物質僅出現在 該等接觸孔之内，而不會留在該絕緣層中。 經濟部智慧財產局員工消費合作社印製 2·如申請專利範圍第1項所述之製造半導體元件之方 法’其中該緩衝溶液包含一去離子水。 3*如申請專利範圍第1項所述之製造半導體元件之方 法，其中該導電層包含一種選自由鎢（W)、銅（Cu)、 以及多晶石夕所組成之群組之物質。 4.如申請專利範圍第3項所述之製造半導體元件之方 法’其係進一步包含在該絕緣層中形成接觸孔之後， 但在形成該絕緣層之前，在該半導體基材與該絕緣層 本紙張尺度適财_緖準（c叫㈣緣（21Qx297公董） -35- 478130 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 · 上形成一層障壁層之步驟。 5·如申請專利範圍第4項所述之製造半導體元件之方 法，其中該障壁層包含一種選自由Ti、TiN、Ti/TiN、 Ta、TaN、及Ta/TaN所組成之群組之物質。 6·如申請專利範圍第1項所述之製造半導體元件之方 法，其中該蝕刻組合物被一個被置放在該半導體基材 上方之喷嘴供應，該喷嘴係受到喷桿擺動而至該半導 體基材中心的右側或該半導體基材中心的左侧。 7·如申請專利範圍第1項所述之製造半導體元件之方 法，其中該蝕刻組合物的處理溫度是在2〇至9〇。(^的範 圍中。 8·如申請專利範圍第7項所述之製造半導體元件之方 法，其中該半導體基材被加熱至約該蝕刻組合物的處 理溫度。 9·如申請專利範圍第3項所述之製造半導體元件之方 法，其中該蝕刻組合物包含作為一氧化劑重量百分比 為〇·〇1至30的HNO3、作為一促進劑重量百分比為〇〇1 至30的NHJ、及具有剩餘重量百分比的去離子水。 10·如申請專利範圍第3項所述之製造半導體元件之方 法，其中該蝕刻組合物包含作為一氧化劑重量百分比 為3至55的HNO3、作為一促進劑重量百分比為〇2至35 的HF、及具有剩餘重量百分比的去離子水。 11·如申請專利範圍第3項所述之製造半導體元件之方 法，其中該蝕刻組合物包含作為一氧化劑重量百分比 i紙張尺度適用中國國家標準（CNS)八4驗（2i〇>^^y-- 11111 n I 1111 n 線 (請先閱讀背面之注意事項再填寫本頁) 36 為〇·2至30的H2〇2、作為一促進劑重量百分比為〇〇1至 30的NH4〇H、及具有剩餘重量百分比的去離子水。 12.如申清專利範圍第3項所述之製造半導體元件之方 法，其中該蝕刻組合物包含作為一氧化劑重量百分比 為3至60的HNO3、作為一促進劑重量百分比為〇〇6至 30的HF、及具有剩餘重量百分比的去離子水。 13·如申請專利範圍第丨項所述之製造半導體元件之方 法，其中該導電層之蝕刻步驟藉由至少兩個蝕刻程序 進行。 14. 一種製造半導體元件之方法，係包含下列步驟： 在一半導體基材上形成一圖樣結構； 在該半導體基材與該圖樣結構上形成一層間層介 電層； 旋轉該半導體基材；以及 經濟部智慧財產局員工消費合作社印製 藉由在該旋轉的半導體基材上供應一餘刻組合物 來蝕刻該間層介電層，該蝕刻組合物係包含一種有至 少一種選自由 H202、〇2、I04·、Br〇3、cl〇3、s2()8-、 KI〇3、仏1〇6、KOH及HN〇3所組成之基團的氧化劑、. 至少一種選自由 HF、NEUOH、II3P04、H2S04、NH4f 與HC1所組成的基團之促進劑、以及缓衝溶液之混合 物， 其中該氧化劑、該促進劑與該緩衝溶液以一定的 混合比例^^^^得蝕刻平面化該間層介電層。 15.如申請專項所述之製.造半導體元件之方 本紙張尺;ΐ適用中國國家標準（CNS ) A4規格（210X297公釐） 37 478130 8 8 8 8 ABCD 經儕部智慧財產局員工消費合作社印製 申請專利範圍 法，其中該間層介電層包含一種選自由氧化物、氮化 物、硼磷矽（borophosphosilicate)、與原矽酸四乙脂 (tetraethylc^^^cate)所組成之群組的物質。 16·如申請專森項所述之製造半導體元件之方 法，其中該其蝕刻組合物包含作為一氧化劑重量 百分比為0.01至60的HNO3、作為一促進劑重量百分 比為0.05至25的HF、及具有剩餘重量百分比的去離子 水。 17.如申請專利範圍第15項所述之製造半導體元件之方 法，其中該姓刻組合物包含作為一氧化劑重量百分比 為0.01至30的HNO3、作為一促進劑重量百分比為〇 〇 1 至3 0的ΝΗβ、及具有剩餘重量百分比的去離子水。 18·如申請專利範圍第14項所述之製造半導體元件之方 法’其中該半導體基材的旋轉速度每分鐘轉速（rpm) 是200至5000 。 19·如申請專利範圍第14項所述之製造半導體元件之方 法，其中該蝕刻組合物被一個被置放在該半導體基材 上方之喷嘴供應，該喷嘴係受到喷桿擺動而至該半導. 體基材中心的右側或該半導體基材中心的左側。 20·如申請專利範圍第19項所述之製造半導體元件之方 法’其中該喷桿擺動包含長距離喷桿擺動部分與短距 離噴桿擺動部分，其係貫序地被進行。 21·如申請專利範圍第14項所述之製造半導體元件之方 法’其中該半導體基材被加熱至約該蚀刻纟且合物之處 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） ---------0------t------^ (請先閱讀背面之注意事項再填寫本頁) 38 ABCD 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 理溫度。 22· —種製造半導體元件之方法，係包含·· 在一半導體基材上形成一絕緣層； 在該絕緣層中形成多個接觸孔； 在該絕緣層上形成-覆蓋層以遮蓋該等接觸孔； 旋轉該半導體基材； 藉由供應熱氣體至該半導縣材之後側而加熱該 半導體基材；以及 藉在該旋轉的半導體基材上供應一蝕刻組合物來 蝕刻該覆蓋層， 其中該覆蓋材之物質在該蝕刻程序之後僅出現於 該接觸孔之内而不會存在該絕緣層之上。 23.如申請專利範圍第22項所述之製造半導體元件之方 法’該餘刻組合物係包含一種有至少一種選自由 H2〇2、〇2、I〇4、Br〇3、C103、S2CV、ΚΙ03、Η5Ι06、 KOH及HN03所組成之基團的氧化劑、至少一種選自 由 HF、NH4OH、H3P04、H2S04、NH4F與 HC1所組成 的基團之促進劑、以及一緩衝溶液之混合物。 24·如申請專利範圍第23項所述之製造半導體元件之方 法’其中該緩衝溶液包含一去離子水。 25.如申請專利範圍第22項所述之製造半導體元件之方 法’其中該覆蓋層包含一層導電層或一層間層介電 層。 26·如申請專利範圍第22項所述之製·造半導體元件之方 本纸張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐）478130 A8 B8 C8 D8 VI. Application for Patent Scope 1. A method for manufacturing a semiconductor element includes: forming an insulating layer on a semiconductor substrate; forming a plurality of contact holes in the insulating layer; on the insulating layer Forming a conductive layer to cover the contact holes; rotating the semiconductor substrate; and etching the conductive layer by supplying an etching composition on the rotated semiconductor substrate, wherein the etching composition includes at least one selected An oxidizing agent consisting of a group consisting of H202, 02, I04, Br03, C103, s208 ·, KI03, Η5Ι06, ΚΟΗ, and ΝΝΟ3, at least one selected from the group consisting of HF, NH4OH, H3P04, H2S04, Li 4F and HC1 A combination of a promoter of the group and a buffer solution, and wherein the oxidant, the promoter and the buffer solution have a mixing ratio, so that after etching, the substance of the conductive layer appears only in the contact holes Inside without leaving in the insulating layer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. The method for manufacturing a semiconductor device as described in the first scope of the patent application ', wherein the buffer solution contains a deionized water. 3 * The method for manufacturing a semiconductor device according to item 1 of the scope of the patent application, wherein the conductive layer includes a substance selected from the group consisting of tungsten (W), copper (Cu), and polycrystalline stone. 4. The method for manufacturing a semiconductor device according to item 3 of the scope of the patent application, which further includes after forming a contact hole in the insulating layer, but before forming the insulating layer, before the semiconductor substrate and the insulating layer are formed. Paper size is suitable for money_Xu Zhun (c is called Yuan Yuan (21Qx297)) -35- 478130 Printed by A8 B8 C8 D8 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Scope of patent application · Steps to form a barrier layer. 5 The method for manufacturing a semiconductor device according to item 4 of the scope of patent application, wherein the barrier layer comprises a substance selected from the group consisting of Ti, TiN, Ti / TiN, Ta, TaN, and Ta / TaN. 6 The method for manufacturing a semiconductor element according to item 1 of the scope of the patent application, wherein the etching composition is supplied by a nozzle placed above the semiconductor substrate, and the nozzle is swinged to the semiconductor substrate by a nozzle The right side of the center or the left side of the center of the semiconductor substrate. 7. The method for manufacturing a semiconductor element as described in item 1 of the scope of the patent application, wherein the processing temperature of the etching composition is 2 °. In the range of 90 ° (^). 8. The method for manufacturing a semiconductor element as described in item 7 of the scope of patent application, wherein the semiconductor substrate is heated to about the processing temperature of the etching composition. The method for manufacturing a semiconductor device according to the third item, wherein the etching composition includes HNO3 as an oxidizing agent in a weight percentage of 0.001 to 30, NHJ as a promoter in a weight percentage of 0.001 to 30, and Deionized water with a remaining weight percentage. 10. The method for manufacturing a semiconductor device as described in item 3 of the scope of the patent application, wherein the etching composition contains HNO3 as an oxidant in a weight percentage of 3 to 55, and weight as a promoter. HF with a percentage of 02 to 35, and deionized water with a remaining weight percentage. 11. The method of manufacturing a semiconductor device as described in item 3 of the patent application scope, wherein the etching composition includes paper as a oxidant weight percentage The scale is applicable to China National Standards (CNS) 8-4 test (2i〇 &^; ^^ y-- 11111 n I 1111 n line (please read the precautions on the back before filling this page) 36 H 2 0 2 to 30, NH 4 0 H as a promoter with a weight percentage of 001 to 30, and deionized water with a remaining weight percentage. The method for manufacturing a semiconductor device as described above, wherein the etching composition comprises HNO3 as an oxidant in a weight percentage of 3 to 60, HF as a promoter in a weight percentage of 006 to 30, and deionized water having a remaining weight percentage. 13. The method for manufacturing a semiconductor device according to item 丨 of the scope of the patent application, wherein the etching step of the conductive layer is performed by at least two etching procedures. 14. A method of manufacturing a semiconductor device, comprising the steps of: forming a pattern structure on a semiconductor substrate; forming an interlayer dielectric layer on the semiconductor substrate and the pattern structure; rotating the semiconductor substrate; and The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs etches the interlayer dielectric layer by supplying a composition on the rotating semiconductor substrate for a short period of time. The etching composition contains at least one selected from H202, 2. I04 ·, Br03, cl03, s2 () 8-, KI03, 仏 106, KOH, and HN03, at least one selected from the group consisting of HF, NEUOH, II3P04, H2S04, NH4f and HC1 group of accelerator and buffer solution mixture, wherein the oxidant, the accelerator and the buffer solution in a certain mixing ratio ^^^^ to etch the planarization of the interlayer Dielectric layer. 15. The system described in the application. The paper ruler for semiconductor components; ΐ Applicable to China National Standard (CNS) A4 (210X297 mm) 37 478130 8 8 8 8 ABCD Method for printing patent application, wherein the interlayer dielectric layer comprises a group selected from the group consisting of oxide, nitride, borophosphosilicate, and tetraethylc ^^^ cate The substance. 16. The method for manufacturing a semiconductor device as described in the application item, wherein the etching composition comprises HNO3 as an oxidant in a weight percentage of 0.01 to 60, HF as a promoter in a weight percentage of 0.05 to 25, and having The remaining weight percent of deionized water. 17. The method for manufacturing a semiconductor device according to item 15 of the scope of the patent application, wherein the composition of the last name contains HNO3 as an oxidizing agent in an amount of 0.01 to 30% by weight, and as a promoter in an amount of 0.01 to 30% by weight. NΗβ, and deionized water with a remaining weight percentage. 18. The method for manufacturing a semiconductor element according to item 14 of the scope of the patent application, wherein the rotation speed (rpm) of the semiconductor substrate is 200 to 5000. 19. The method for manufacturing a semiconductor device according to item 14 of the scope of the patent application, wherein the etching composition is supplied by a nozzle placed above the semiconductor substrate, and the nozzle is swinged by the spray rod to the semiconductor. The right side of the center of the bulk substrate or the left side of the center of the semiconductor substrate. 20. The method for manufacturing a semiconductor device according to item 19 of the scope of the patent application, wherein the boom swing includes a long-distance boom swing section and a short-distance boom swing section, which are sequentially performed. 21 · The method for manufacturing a semiconductor device as described in item 14 of the scope of the patent application, wherein the semiconductor substrate is heated to about the etched spot and the composition. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 Mm) --------- 0 ------ t ------ ^ (Please read the notes on the back before filling out this page) 38 ABCD Employee Consumer Cooperatives, Ministry of Economic Affairs Printing 6. The temperature range of patent application. 22 · —A method for manufacturing a semiconductor element, comprising: forming an insulating layer on a semiconductor substrate; forming a plurality of contact holes in the insulating layer; forming a cover layer on the insulating layer to cover the contacts Holes; rotating the semiconductor substrate; heating the semiconductor substrate by supplying hot gas to the rear side of the semiconductor material; and etching the cover layer by supplying an etching composition on the rotating semiconductor substrate, wherein The material of the covering material only appears inside the contact hole after the etching process and does not exist on the insulating layer. 23. The method for manufacturing a semiconductor device according to item 22 of the scope of the patent application. 'The afterglow composition comprises at least one member selected from the group consisting of H202, 02, I04, Br03, C103, S2CV, An oxidant of a group consisting of KI03, Η5Ι06, KOH and HN03, at least one accelerator selected from the group consisting of HF, NH4OH, H3P04, H2S04, NH4F and HC1, and a mixture of a buffer solution. 24. The method for manufacturing a semiconductor device according to item 23 of the scope of the patent application, wherein the buffer solution contains deionized water. 25. The method for manufacturing a semiconductor device according to item 22 of the scope of patent application, wherein the cover layer includes a conductive layer or an interlayer dielectric layer. 26. The method of manufacturing and manufacturing semiconductor components as described in item 22 of the scope of the patent application. The paper size is applicable to China National Standard (CNS) A4 (210X297 mm). 39 478130 經请部智慧財產局員工消費合作社印製 Α8 Β8 C8 D8 六、申請專利範圍 ’ 一 法’其中該熱氣體包含一種惰性氣體，並該熱氣體之 溫度是在20至90°C的範圍中。 27·如申請專利範圍第22項所述之製造半導體元件之方 法，其中該蝕刻組合物被一個被置放在該半導體基材 上方之喷嘴供應，該喷嘴係受到喷桿擺動而至該半導 體基材中心的右側或該半導體基材中心的左側。 28.如申請專利範圍第22項所述之製造半導體元件之方 法，其中該姓刻組合物的處理溫度是在2〇至9〇π的範 圍中。 29. —種半導體基材，係包含： 一單元區域，係包括一個由一導電材料所組成的 導電插塞；以及 一周邊區域，係包括一個供一對準記號或一刻晝 線之其中一者用的孔圖案， 其中該孔圖樣沒有包含導電材料。 30·如申請專利範圍第29項所述之半導體基材，其中該導 電材料包含一種選自由鎢（W)、銅（Cu)、或多晶矽所 組成之群組之物質。 ---------¾------、p------Μ (請先閱讀背面之注意事項再填寫本頁}39 478130 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of A8, B8, C8, and D8. 6. Patent application scope 'One method', where the hot gas contains an inert gas, and the temperature of the hot gas is in the range of 20 to 90 ° C. in. 27. The method for manufacturing a semiconductor device according to item 22 of the scope of the patent application, wherein the etching composition is supplied by a nozzle placed above the semiconductor substrate, and the nozzle is swinged to the semiconductor substrate Right side of the center of the material or left side of the center of the semiconductor substrate. 28. The method for manufacturing a semiconductor device according to item 22 of the scope of patent application, wherein the processing temperature of the engraved composition is in a range of 20 to 90 π. 29. A semiconductor substrate comprising: a unit region including a conductive plug composed of a conductive material; and a peripheral region including one of an alignment mark or a daylight Used hole pattern, wherein the hole pattern does not include a conductive material. 30. The semiconductor substrate according to item 29 of the scope of patent application, wherein the conductive material comprises a substance selected from the group consisting of tungsten (W), copper (Cu), or polycrystalline silicon. --------- ¾ ------, p ------ Μ (Please read the notes on the back before filling this page} 4040
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI614804B (en) * 2011-12-27 2018-02-11 富士軟片股份有限公司 Producing method of semiconductor substrate products and etching method used by the same

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4240424B2 (en) 1998-10-23 2009-03-18 エルジー ディスプレイ カンパニー リミテッド Etching agent and method for manufacturing substrate for electronic device using the same
US20010054706A1 (en) * 1999-07-19 2001-12-27 Joseph A. Levert Compositions and processes for spin etch planarization
KR100641950B1 (en) * 2000-06-27 2006-11-02 주식회사 하이닉스반도체 A method for forming a contact plug of a semiconductor device
JP2002043201A (en) * 2000-07-28 2002-02-08 Mitsubishi Electric Corp Method of manufacturing semiconductor device and semiconductor device
KR100372647B1 (en) * 2000-10-13 2003-02-19 주식회사 하이닉스반도체 Method for forming damascene metal gate
AU2001296420A1 (en) * 2000-11-28 2002-06-11 Lightcross, Inc Formation of a smooth surface on an optical component
JP3609761B2 (en) 2001-07-19 2005-01-12 三洋電機株式会社 Manufacturing method of semiconductor device
KR100881388B1 (en) * 2002-11-04 2009-02-05 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
KR100536593B1 (en) * 2002-12-05 2005-12-14 삼성전자주식회사 Cleaning solution for selectively removing a layer and method for selectively removing the layer in silicide process using the cleaning solution
JP4355201B2 (en) * 2003-12-02 2009-10-28 関東化学株式会社 Tungsten metal removing liquid and tungsten metal removing method using the same
US7351642B2 (en) 2005-01-14 2008-04-01 Infineon Technologies Richmond, Lp Deglaze route to compensate for film non-uniformities after STI oxide processing
KR100624089B1 (en) 2005-07-12 2006-09-15 삼성전자주식회사 Method of forming a pattern, method of manufacturing a multi gate oxide layer and flash memory cell using the same
KR101264421B1 (en) 2005-12-09 2013-05-14 동우 화인켐 주식회사 Etchant for metal layer
EP1981072A4 (en) * 2006-01-31 2009-01-21 Sumco Corp Single wafer etching method
JP4906417B2 (en) * 2006-07-11 2012-03-28 ラピスセミコンダクタ株式会社 Manufacturing method of semiconductor device
KR100860367B1 (en) 2006-08-21 2008-09-25 제일모직주식회사 Wet etching solution having high selectivity for silicon oxide
JP5017709B2 (en) 2006-09-07 2012-09-05 ジルトロニック アクチエンゲゼルシャフト Silicon wafer etching method and semiconductor silicon wafer manufacturing method
JP5047881B2 (en) * 2007-07-13 2012-10-10 東京応化工業株式会社 Titanium nitride stripping solution and method for stripping titanium nitride coating
US8623236B2 (en) 2007-07-13 2014-01-07 Tokyo Ohka Kogyo Co., Ltd. Titanium nitride-stripping liquid, and method for stripping titanium nitride coating film
JP5439466B2 (en) * 2011-12-26 2014-03-12 富士フイルム株式会社 Silicon etching method, silicon etching solution used therefor, and kit thereof
JP2014146623A (en) * 2013-01-25 2014-08-14 Fujifilm Corp Method of etching semiconductor substrate, etchant, and method of manufacturing semiconductor element
JP6454605B2 (en) 2015-06-01 2019-01-16 東芝メモリ株式会社 Substrate processing method and substrate processing apparatus
JP6917807B2 (en) * 2017-07-03 2021-08-11 東京エレクトロン株式会社 Substrate processing method
JP7398969B2 (en) * 2019-03-01 2023-12-15 東京エレクトロン株式会社 Substrate processing method, substrate processing apparatus and storage medium

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5217995B2 (en) * 1972-02-18 1977-05-19
JPS524140A (en) * 1975-06-28 1977-01-13 Victor Co Of Japan Ltd Data presentation system
US4345969A (en) * 1981-03-23 1982-08-24 Motorola, Inc. Metal etch solution and method
US4415606A (en) * 1983-01-10 1983-11-15 Ncr Corporation Method of reworking upper metal in multilayer metal integrated circuits
US4806504A (en) * 1986-09-11 1989-02-21 Fairchild Semiconductor Corporation Planarization method
GB2212979A (en) * 1987-12-02 1989-08-02 Philips Nv Fabricating electrical connections,particularly in integrated circuit manufacture
US4804438A (en) * 1988-02-08 1989-02-14 Eastman Kodak Company Method of providing a pattern of conductive platinum silicide
JPH0322428A (en) * 1989-06-19 1991-01-30 Nec Kyushu Ltd Manufacturing apparatus for semiconductor device
US5279704A (en) * 1991-04-23 1994-01-18 Honda Giken Kogyo Kabushiki Kaisha Method of fabricating semiconductor device
US5486234A (en) * 1993-07-16 1996-01-23 The United States Of America As Represented By The United States Department Of Energy Removal of field and embedded metal by spin spray etching
US5340437A (en) * 1993-10-08 1994-08-23 Memc Electronic Materials, Inc. Process and apparatus for etching semiconductor wafers
KR950019922A (en) * 1993-12-28 1995-07-24 김주용 Polycrystalline Silicon Wet Etch Solution
US5449639A (en) * 1994-10-24 1995-09-12 Taiwan Semiconductor Manufacturing Company Ltd. Disposable metal anti-reflection coating process used together with metal dry/wet etch
JP3459137B2 (en) * 1995-04-06 2003-10-20 日曹エンジニアリング株式会社 Single wafer spin etching method
US5863828A (en) * 1996-09-25 1999-01-26 National Semiconductor Corporation Trench planarization technique
KR100205321B1 (en) * 1996-12-30 1999-07-01 구본준 Method for manufacture of device having crack prevented pattern

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI614804B (en) * 2011-12-27 2018-02-11 富士軟片股份有限公司 Producing method of semiconductor substrate products and etching method used by the same

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