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TW202213554A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW202213554A
TW202213554A TW110102842A TW110102842A TW202213554A TW 202213554 A TW202213554 A TW 202213554A TW 110102842 A TW110102842 A TW 110102842A TW 110102842 A TW110102842 A TW 110102842A TW 202213554 A TW202213554 A TW 202213554A
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TW
Taiwan
Prior art keywords
insulating film
substrate
semiconductor device
opening
plug
Prior art date
Application number
TW110102842A
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English (en)
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TWI782400B (zh
Inventor
冨松孝宏
荒井伸也
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日商鎧俠股份有限公司
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Publication of TW202213554A publication Critical patent/TW202213554A/zh
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Publication of TWI782400B publication Critical patent/TWI782400B/zh

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract

實施形態提供一種可以適宜之態樣將接合墊電性連接於通孔插塞的半導體裝置及其製造方法。 根據一實施形態，半導體裝置具備第1基板、及設置於上述第1基板上之第1絕緣膜。上述裝置進而具備：第1插塞，其設置於上述第1絕緣膜內；及第2基板，其設置於上述第1絕緣膜上。上述裝置進而具備第1配線，其包含：第1部分，該第1部分設置於上述第2基板內，且設置於上述第1插塞上；及第2部分，該第2部分設置於上述第2基板上，包含接合墊，且以與上述第1部分之材料相同之材料形成。

Description

半導體裝置及其製造方法
本發明之實施形態係關於一種半導體裝置及其製造方法。
於基板上形成通孔插塞與接合墊之情形時，期望以較適宜之態樣將接合墊電性連接於通孔插塞。
實施形態提供一種可以適宜之態樣將接合墊電性連接於通孔插塞之半導體裝置及其製造方法。
根據一實施形態，半導體裝置具備第1基板、及設置於上述第1基板上之第1絕緣膜。上述裝置進而具備：第1插塞，其設置於上述第1絕緣膜內；及第2基板，其設置於上述第1絕緣膜上。上述裝置進而具備第1配線，其包含：第1部分，其設置於上述第2基板內，且設置於上述第1插塞上；及第2部分，其設置於上述第2基板上，包含接合墊，且以與上述第1部分之材料相同之材料形成。
以下，參照圖式說明本發明之實施形態。圖1至圖9中，對相同構成附注相同符號，省略重複之說明。
(第1實施形態) 圖1係顯示第1實施形態之半導體裝置之構造之剖視圖。圖1之半導體裝置係將陣列晶片1與電路晶片2加以貼合之3維記憶體。
圖1表示互相垂直之X方向、Y方向及Z方向。本說明書中，將+Z方向作為上方向處理，將-Z方向作為下方向處理。-Z方向可與重力方向一致，亦可不與重力方向一致。
陣列晶片1具備包含複數個記憶胞之記憶胞陣列11、記憶胞陣列11上之基板12、及記憶胞陣列11下之層間絕緣膜13。基板12例如為矽基板等半導體基板。圖1顯示形成於基板12內之井(well)區域12a。層間絕緣膜13例如為氧化矽膜、或包含氧化矽膜與其他絕緣膜之積層膜。基板12為第2基板之例。層間絕緣膜13為第1絕緣膜之例。
電路晶片2設置於陣列晶片1下。圖1顯示陣列晶片1與電路晶片2之貼合面S。電路晶片2具備層間絕緣膜14、與層間絕緣膜14下之基板15。層間絕緣膜14例如為氧化矽膜、或包含氧化矽膜與其他絕緣膜之積層膜。基板15例如為矽基板等半導體基板。層間絕緣膜14與層間絕緣膜13皆為第1絕緣膜之例。基板15為第1基板之例。
陣列晶片1具備複數條字元線WL作為記憶胞陣列11內之電極層。圖1顯示記憶胞陣列11內之階差構造部21。各字元線WL經由接觸插塞22及通孔插塞23與字元配線層WI電性連接。圖1中進而顯示貫通上述複數條字元線WL之複數個柱狀部CL中之一個。各柱狀部CL經由通孔插塞24與位元線BL電性連接。
電路晶片2具備複數個電晶體31。圖1顯示該等電晶體31中之1個。各電晶體31具備介隔閘極絕緣膜設置於基板15上之閘極電極32、及設置於基板15內之未圖示之源極擴散層及汲極擴散層。又，電路晶片2具備：複數個接觸插塞33，其等設置於該等電晶體31之閘極電極32、源極擴散層或汲極擴散層上；配線層34，其設置於該等接觸插塞33上，包含複數條配線；及複數個通孔插塞35，其設置於配線層34上。
電路晶片2進而具備：配線層36，其設置於該等通孔插塞35上，包含複數條配線；複數個通孔插塞37，其等設置於配線層36上；及複數個金屬焊墊38，其等設置於該等通孔插塞37上。金屬焊墊38例如為包含Cu層或Al層之金屬層(Cu表示銅，Al表示鋁)。電路晶片2作為控制陣列晶片1之動作之控制電路(邏輯電路)發揮功能。該控制電路由電晶體31等構成，電性連接於金屬焊墊38。
陣列晶片1具備：複數個金屬焊墊41，其等設置於金屬焊墊38上；及複數個通孔插塞42，其等設置於金屬焊墊41上。又，陣列晶片1具備：配線層43，其設置於該等通孔插塞42上，包含複數條配線；及複數個通孔插塞44，其等設置於配線層43上。金屬焊墊41例如為包含Cu層或Al層之金屬層。上述位元線BL或字元配線層WI包含於配線層43。又，上述控制電路經由金屬焊墊41、38等電性連接於記憶胞陣列11，且經由金屬焊墊41、38等控制記憶胞陣列11之動作。
陣列晶片1進而具備設置於上述複數個通孔插塞44上之複數個通孔插塞45。圖1顯示該等通孔插塞45中之2個。通孔插塞45設置於層間絕緣膜13內，設置於記憶胞陣列11之側方。通孔插塞45例如為包含W層之金屬層(W表示鎢)。通孔插塞45為第1插塞之例。
陣列晶片1進而具備依序形成於基板12上之絕緣膜46、絕緣膜47及金屬配線48。絕緣膜46例如為氧化矽膜。絕緣膜47例如為氧化矽膜。金屬配線48例如為包含Al層之金屬層。絕緣膜46為第2絕緣膜或第1膜之例。絕緣膜47為第2絕緣膜或第2膜之例。金屬配線48為第1配線之例。
絕緣膜47包含：側方部47a，其形成於基板12及絕緣膜46之側面；上方部47b，其形成於絕緣膜46之上表面；及埋入部47c，其埋入於基板12及絕緣膜46內。側方部47a及埋入部47c形成於基板12及絕緣膜46之內部，上方部47b形成於基板12及絕緣膜46之外部。本實施形態中，側方部47a作為基板12及絕緣膜46之側面之側壁絕緣膜發揮功能，埋入膜47c作為基板12及絕緣膜46內之元件分離絕緣膜發揮功能。本實施形態之埋入部47c包含將埋入部47埋入於基板12及絕緣膜46內時形成之氣隙AG。側方部47a為第3部分之例。埋入部47c為與第3部分不同之第4部分之例。
金屬配線48包含：上方部48a，其形成於層間絕緣膜13及上述複數個通孔插塞45之上表面；側方部48b，其形成於絕緣膜47之側面；及上方部48c，其形成於絕緣膜47之上表面。金屬配線48電性連接於上述複數個通孔插塞45。上方部48a及側方部48b形成於基板12、絕緣膜46及絕緣膜47之內部，上方部48c形成於基板12、絕緣膜46及絕緣膜47之外部。因本實施形態之上方部48a、側方部48b及上方部48c由相同之配線層同時形成，故以相同之材料(例如鋁)形成。本實施形態之上方部48a、側方部48b及上方部48c形成連續之1條配線。上方部48a及側方部48b為第1部分之例。上方部48c為第2部分之例。
陣列晶片1進而具備形成於絕緣膜47及金屬配線48上之鈍化膜49。鈍化膜49為第3絕緣膜之例。
鈍化膜49包含依序形成於絕緣膜47及金屬配線48上之絕緣膜49a、絕緣膜49b、及絕緣膜49c。絕緣膜49a例如為氧化矽膜。絕緣膜49b例如為氮化矽膜。絕緣膜49c例如為聚醯亞胺膜。本實施形態之鈍化膜49如圖1所示包含介隔絕緣膜47(側方部47a)與金屬配線48(側方部48a)形成於基板12及絕緣膜46內之部分。
鈍化膜49例如具有使金屬層48之上方部48c之上表面露出之開口部P。於開口部P內露出之上方部48c作為圖1之半導體裝置之外部連接墊(接合墊)發揮功能。上方部48c可經由開口部P利用接合線、焊料球、金屬凸塊等連接於安裝基板或其他裝置。
本實施形態之金屬配線48包含：上方部48a，其設置於上述複數個通孔插塞45上；及上方部48c，其包含接合墊；且作為電性連接該等通孔插塞45與接合墊之連接配線發揮功能。與該1條金屬配線48電性連接之通孔插塞45之個數可為任意個，例如為100～10000個。
陣列晶片1內之記憶胞陣列11包含與上述複數條字元線WL交替積層之複數個絕緣層51。絕緣層51例如為氧化矽膜。
陣列晶片1內之各柱狀部CL包含記憶體絕緣膜52、通道半導體層53、芯絕緣膜54、半導體層55及半導體層56。記憶體絕緣膜52、通道半導體層53、及芯絕緣膜54依序形成於字元線WL及絕緣層51內。半導體層55形成於通道半導體層53上，電性連接通道半導體層53與基板12。半導體層56於芯絕緣膜54下形成於通道半導體層53之側面，且電性連接通道半導體層53與通孔插塞24。
圖2係顯示第1實施形態之各柱狀部CL之構造之剖視圖。圖2相當於圖1之剖視圖之放大圖。
如圖2所示，記憶體絕緣膜52包含依序形成於字元線WL及絕緣層51內之阻擋絕緣膜52a、電荷蓄積層52b、及穿隧絕緣膜52c。阻擋絕緣膜52a、穿隧絕緣膜52c、及芯絕緣膜54例如為氧化矽膜或金屬絕緣膜。電荷蓄積層52b例如為氮化矽膜。電荷蓄積層52b亦可為多晶矽層等半導體層。通道半導體層53、半導體層55(圖1)及半導體層56(圖1)例如為多晶矽層或單晶矽層。
圖3係用於比較第1實施形態之半導體裝置及其比較例之半導體裝置之剖視圖。
圖3(a)顯示比較例之半導體裝置之構造。比較例之半導體裝置具有與本實施形態之半導體裝置大致相同之構造。但，比較例中，於上述複數個通孔插塞45上形成有複數個通孔插塞61，於該等通孔插塞61上形成有金屬配線48之上方部48c。比較例之金屬配線48不具備上方部48a或側方部48b。
圖3(a)所示之通孔插塞61與金屬配線48例如以如下方式形成。首先，於基板12內形成複數個通孔，於該等通孔內，使複數個通孔插塞45露出。接著，於該等通孔內介隔絕緣膜47形成通孔插塞61，於通孔插塞45上配置通孔插塞61。接著，於通孔插塞61上形成金屬配線48。
另一方面，圖3(b)顯示第1實施形態之半導體裝置之構造。圖3(b)所示之金屬配線48例如以如下方式形成。首先，於基板12內形成1個開口部，於該開口部內，使複數個通孔插塞45露出。接著，遍及該開口部之內部與外部形成金屬配線48，於通孔插塞45上形成金屬配線48。
比較例中，為了將接合墊(金屬配線48之上方部48c)電性連接於通孔插塞45，需要進行形成通孔之步驟、形成通孔插塞61之步驟、及形成金屬配線48之步驟。另一方面，根據本實施形態，藉由進行形成開口部之步驟與形成金屬配線48之步驟，可將接合墊(金屬配線48之上方部48c)電性連接於通孔插塞45。如此，根據本實施形態，可省略形成通孔插塞61之步驟，藉此，可削減半導體裝置之製造步驟數、製造成本。
另外，比較例之上述通孔之縱橫比高，相對於此，本實施形態之上述開口部之縱橫比降低。因此，根據本實施形態，可於基板12內同時形成上述開口部與元件分離槽，藉此，可進一步削減半導體裝置之製造步驟數、製造成本。
本實施形態中，於該元件分離槽內埋入有元件分離絕緣膜(絕緣膜47之埋入部47c)。根據本實施形態，可與上述開口部之側面之側壁絕緣膜(絕緣膜47之側方部47a)同時形成該元件分離絕緣膜，藉此，可進一步削減半導體裝置之製造步驟數、製造成本。
又，比較例之金屬配線48經由通孔插塞61電性連接於通孔插塞45，相對於此，本實施形態之金屬配線48不經由其他層電性連接於通孔插塞45。因此，根據本實施形態，可減少通孔插塞45與金屬配線48間之電阻，藉此，可減少通孔插塞45與接合墊間之電阻。
圖4至圖9係顯示第1實施形態之半導體裝置之製造方法之剖視圖。本實施形態之半導體裝置如後文所述，藉由將包含複數個陣列晶片1之陣列晶圓W1、與包含複數個電路晶片2之電路晶圓W2貼合而製造。
首先，準備基板12，於基板12內形成井區域12a(圖4(a))。圖4(a)顯示基板12內之井區域12a與其他區域12b。接著，於基板12上形成記憶胞陣列11、層間絕緣膜13、通孔插塞45、通孔插塞44、配線層43、通孔插塞42、金屬焊墊41等(圖4(a))。圖4(a)進而顯示記憶胞陣列11所含之字元線WL、絕緣層51、柱狀部CL、階差構造部21等。例如，複數個通孔插塞45於層間絕緣膜13內形成於基板12(井區域12a)上。如此，製造陣列晶圓W1。圖4(a)顯示陣列晶圓W1之上表面S1。
接著，準備基板15，於基板15上形成層間絕緣膜14、電晶體31、閘極電極32、接觸插塞33、配線層34、通孔插塞35、配線層36、通孔插塞37、金屬焊墊38等(圖4(b))。如此，製造電路晶圓W2。圖4(b)顯示電路晶圓W2之上表面S2。
接著，將陣列晶圓W1與電路晶圓W2貼合(圖5(a))。具體而言，將基板12與基板15介隔記憶胞陣列11、層間絕緣膜13、層間絕緣膜14、電晶體31、通孔插塞45等貼合。圖5(a)中，使陣列晶圓W1之上下方向反轉，將陣列晶圓W1貼合於電路晶圓W2。其結果，將基板12配置於基板15之上方。於該貼合步驟中，層間絕緣膜13與層間絕緣膜14藉由機械壓力而接著，金屬焊墊41與金屬焊墊38藉由退火而接合。
接著，藉由濕蝕刻將基板12薄膜化(圖5(b))。其結果，基板12之厚度變薄。圖5(b)中，基板12內之井區域12a於薄膜化後仍殘留，基板12內之其他區域12b藉由薄膜化而去除。
接著，於基板12上形成絕緣膜46(圖6(a))。接著，藉由RIE(Reactive Ion Etching：反應離子蝕刻)蝕刻絕緣膜46及基板12(圖6(b))。其結果，於絕緣膜46及基板12內形成開口部H1，於開口部H1內，層間絕緣膜13與上述複數個通孔插塞45露出。再者，於絕緣膜46及基板12內形成開口部H2，於開口部H2內，層間絕緣膜13露出。本實施形態之開口部H2為元件分離槽。圖6(b)之步驟中，藉由上述RIE同時形成開口部H1與開口部H2。開口部H1為第1開口部之例。開口部H2為與第1開口部不同之第2開口部之例。絕緣膜46為第1膜之例。
接著，於基板12之整面形成絕緣膜47(圖7(a))。其結果，於絕緣膜46、基板12、層間絕緣膜13、及通孔插塞45之表面形成絕緣膜47。具體而言，開口部H1之側面及底面由絕緣膜47覆蓋，開口部H2由絕緣膜47填滿。本實施形態中，以圖7(a)之步驟，於開口部H2內之絕緣膜47內形成氣隙AG。接著，於基板12之整面形成抗蝕劑層71，自開口部H1之底面去除抗蝕劑層71(圖7(a))。
接著，使用抗蝕劑層71作為遮罩，藉由RIE蝕刻絕緣膜47(圖7(b))。其結果，自開口部H1之底面去除絕緣膜47，於開口部H1內，層間絕緣膜13與上述複數個通孔插塞45再次露出。再者，將絕緣膜47加工成包含以下三部分之形狀，上述三部分指開口部H1之側面之側方部47a、絕緣膜46之上表面之上方側47b、及開口部H2內之埋入部47c。本實施形態中，側方部47a作為側壁絕緣膜發揮功能，埋入膜47c作為元件分離絕緣膜發揮功能。如此，根據本實施形態，可同時形成側壁絕緣膜與元件分離絕緣膜。絕緣膜47為第2膜之例。
接著，於基板12之整面，形成作為金屬配線48之材料之金屬配線層48(圖8(a))。其結果，於絕緣膜47、層間絕緣膜13及通孔插塞45之表面形成金屬配線層48。具體而言，開口部H1之側面介隔絕緣膜47由金屬配線層48覆蓋，開口部H1之底面由金屬配線層48覆蓋。金屬配線層48例如為包含Al層之金屬層。接著，於基板12之整面形成抗蝕劑層72，其後去除抗蝕劑層72之一部分(圖8(a))。
接著，使用抗蝕劑層72作為遮罩，藉由RIE蝕刻金屬配線層48(圖8(b))。其結果，金屬配線層48被加工成包含開口部H1之底面之上方部48a、開口部H1之側面之側方部48b、及絕緣膜47之上表面之上方部48c之金屬配線48。因上方部48a形成於上述複數個通孔插塞45上，故金屬配線48電性連接於該等通孔插塞45。因本實施形態之上方部48a、側方部48b及上方部48c由相同之金屬配線層48同時形成，故可由相同材料(例如鋁)形成。本實施形態之上方部48a、側方部48b及上方部48c形成連續之1條配線。
接著，於基板12之整面，依序形成鈍化膜49之絕緣膜49a、49b、49c(圖9(a))。其結果，於絕緣膜47及金屬配線48之表面形成鈍化膜49。本實施形態之鈍化膜49包含介隔絕緣膜47(側方部47a)與金屬配線48(側方部48a)形成於開口部H1內之部分。
接著，去除上方部48c之上表面之鈍化膜49之一部分(圖9(b))。其結果，於鈍化膜49內形成開口部P，於開口部P內，上方部48c之上表面露出。於開口部P內露出之上方部48c作為接合墊發揮功能。因此，本實施形態之金屬配線48包含與通孔插塞45相接之部分、及作為接合墊發揮功能之部分之兩者。
其後，藉由切割將陣列晶圓W1及電路晶圓W2切斷成複數個晶片。該等晶片以各晶片包含1個陣列晶片1與1個電路晶片2之方式被切斷。如此，製造圖1之半導體裝置。
如以上所述，本實施形態之金屬配線48包含設置於通孔插塞45上之上方部48a、及包含接合墊之上方部48c。因此，根據本實施形態，可以適宜之態樣將接合墊電性連接於通孔插塞45。例如，可不使用如比較例之通孔插塞61而將接合墊電性連接於通孔插塞45，或可減少接合墊與通孔插塞45間之電阻。藉此，可削減半導體裝置之製造步驟數、製造成本。
以上，已說明若干實施形態，但該等實施形態僅作為例而提示，並非旨在限定發明範圍者。本說明書中說明之新穎之裝置及方法可以其他各種形態實施。又，對於本說明書中說明之裝置及方法之形態，可於不脫離發明主旨之範圍內進行各種省略、置換、變更。隨附之專利申請範圍及與其均等之範圍旨在包含發明範圍或主旨所含之此種形態或變化例。
[相關申請案] 本申請案享有以日本專利申請案第2020-156645號(申請日：2020年9月17日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之所有內容。
1:陣列晶片 2:電路晶片 11:記憶胞陣列 12:基板 12a:井區域 12b:其他區域 13:層間絕緣膜 14:層間絕緣膜 15:基板 21:階差構造部 22:接觸插塞 23:通孔插塞 24:通孔插塞 31:電晶體 32:閘極電極 33:接觸插塞 34:配線層 35:通孔插塞 36:配線層 37:通孔插塞 38:金屬焊墊 41:金屬焊墊 42:通孔插塞 43:配線層 44:通孔插塞 45:通孔插塞 46:絕緣膜 47:絕緣膜 47a:側方部 47b:上方部 47c:埋入部 48:金屬配線/金屬配線層 48a:上方部 48b:側方部 48c:上方部 49:鈍化膜 49a:絕緣膜 49b:絕緣膜 49c:絕緣膜 51:絕緣層 52:記憶體絕緣膜 52a:阻擋絕緣膜 52b:電荷蓄積層 52c:穿隧絕緣膜 53:通道半導體層 54:芯絕緣膜 55:半導體層 56:半導體層 61:通孔插塞 71:抗蝕劑層 72:抗蝕劑層 AG:氣隙 BL:位元線 CL:柱狀部 H1:開口部 H2:開口部 P:開口部 S:貼合面 S1:上表面 S2:上表面 WL:字元線 WI:字元配線層 W1:陣列晶圓 W2:電路晶圓
圖1係顯示第1實施形態之半導體裝置之構造之剖視圖。 圖2係顯示第1實施形態之各柱狀部之構造之剖視圖。 圖3(a)、(b)係用以比較第1實施形態之半導體裝置與其之比較例之半導體裝置之剖視圖。 圖4(a)～9(b)係顯示第1實施形態之半導體裝置之製造方法之剖視圖。
1:陣列晶片
2:電路晶片
11:記憶胞陣列
12:基板
12a:井區域
13:層間絕緣膜
14:層間絕緣膜
15:基板
21:階差構造部
22:接觸插塞
23:通孔插塞
24:通孔插塞
31:電晶體
32:閘極電極
33:接觸插塞
34:配線層
35:通孔插塞
36:配線層
37:通孔插塞
38:金屬焊墊
41:金屬焊墊
42:通孔插塞
43:配線層
44:通孔插塞
45:通孔插塞
46:絕緣膜
47:絕緣膜
47a:側方部
47b:上方部
47c:埋入部
48:金屬配線/金屬配線層
48a:上方部
48b:側方部
48c:上方部
49:鈍化膜
49a:絕緣膜
49b:絕緣膜
49c:絕緣膜
51:絕緣層
52:記憶體絕緣膜
53:通道半導體層
54:芯絕緣膜
55:半導體層
56:半導體層
AG:氣隙
BL:位元線
CL:柱狀部
P:開口部
S:貼合面
WL:字元線
WI:字元配線層

Claims (12)

  1. 一種半導體裝置，其具備： 第1基板； 第1絕緣膜，其設置於上述第1基板上； 第1插塞，其設置於上述第1絕緣膜內； 第2基板，其設置於上述第1絕緣上；及 第1配線，其包含：第1部分，其設置於上述第2基板內，且設置於上述第1插塞上；及第2部分，其設置於上述第2基板上，包含接合墊，以與上述第1部分之材料相同之材料形成。
  2. 如請求項1之半導體裝置，其進而具備： 第2絕緣膜，其設置於上述第2基板上；且 上述第1部分設置於上述第2基板及上述第2絕緣膜內； 上述第2部分介隔上述第2絕緣膜設置於上述第2基板上。
  3. 如請求項2之半導體裝置，其中 上述第2絕緣膜包含：第3部分，其設置於上述第2基板內，且設置於上述第2基板與上述第1部分之間；及第4部分，其設置於上述第2基板內，與上述第3部分不同。
  4. 如請求項3之半導體裝置，其中上述第4部分包含氣隙。
  5. 如請求項1至4中任一項之半導體裝置，其進而具備： 第3絕緣膜，其設置於上述第1配線上； 上述第3絕緣膜包含設置於上述第2基板內之部分。
  6. 如請求項5之半導體裝置，其中上述接合墊在設置於上述第3絕緣膜內之開口部內露出。
  7. 如請求項1至4中任一項之半導體裝置，其中 具備複數個插塞作為上述第1插塞； 具備設置於上述複數個插塞上之1條配線，作為上述第1配線。
  8. 一種半導體裝置之製造方法，其包含： 準備第1基板與第2基板； 於上述第2基板上形成第1絕緣膜； 於上述第1絕緣膜內形成第1插塞； 將上述第1基板與上述第2基板介隔上述第1絕緣膜及上述第1插塞貼合，於上述第1基板之上方配置上述第2基板； 於上述第2基板內形成第1開口部，於上述第1開口部內，使上述第1插塞露出； 形成第1配線，其包含：第1部分，其設置於上述第1開口部內，且設置於上述第1插塞上；第2部分，其設置於上述第2基板上，包含接合墊，以與上述第1部分之材料相同之材料形成。
  9. 如請求項8之半導體裝置之製造方法，其中上述第1配線介隔第2絕緣膜形成於上述第2基板上。
  10. 如請求項9之半導體裝置之製造方法，其進而包含：於上述第2基板內，形成與上述第1開口部不同之第2開口部； 上述第2絕緣膜包含：第3部分，其設置於上述第1開口部內；及第4部分，其設置於上述第2開口部內。
  11. 如請求項10之半導體裝置之製造方法，其中 上述第2絕緣膜包含： 第1膜，其於形成上述第1及第2開口部前，形成於上述第2基板上；及 第2膜，其於形成上述第1及第2開口部後，形成於上述第1膜上與上述第1及第2開口部內。
  12. 如請求項8至11中任一項之半導體裝置之製造方法，其進而包含：於上述第1配線上形成第3絕緣膜； 上述第3絕緣膜包含設置於上述第1開口部內之部分。
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JP6203152B2 (ja) * 2014-09-12 2017-09-27 東芝メモリ株式会社 半導体記憶装置の製造方法
JP2020145231A (ja) * 2019-03-04 2020-09-10 キオクシア株式会社 半導体装置およびその製造方法
JP2020145351A (ja) * 2019-03-07 2020-09-10 キオクシア株式会社 半導体装置およびその製造方法
JP2020150037A (ja) * 2019-03-11 2020-09-17 キオクシア株式会社 半導体装置およびその製造方法
US11211370B2 (en) * 2020-01-28 2021-12-28 Sandisk Technologies Llc Bonded assembly with vertical power and control signal connection adjacent to sense amplifier regions and methods of forming the same
US11444039B2 (en) * 2020-05-29 2022-09-13 Sandisk Technologies Llc Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same

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