TW201533866A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

This invention provides a manufacturing method of a semiconductor package, firstly providing a carrier, which is provided with a first and a second semiconductor elements stacked, and then a support material is formed to cover the periphery of the first semiconductor element; further forming an encapsulation layer on the carrier, and then removing the carrier and the support material, so that the encapsulation layer is formed a concave area, and the first semiconductor element is located in the concave area; finally forming an insulating material in the concave area, and forming an electrical trace layer on the insulating material, and forming a plurality of conductive blind holes in the insulating material so as to be electrically connected to the electric trace layer, the first and the second semiconductor elements. First, removing the support material, and then forming the insulating material, enabling the support material to address the conductive blind hole misalignment. This invention further provides a semiconductor package.

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package, and more particularly to a semiconductor package having a stacked structure and a method of fabricating the same.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. The early multi-chip package structure used a side-by-side multi-chip package structure in which two or more wafers were mounted side by side on a main mounting surface of a common substrate. The connection between the wafer and the conductive traces on the common substrate is typically achieved by wire bonding. However, the side-by-side multi-chip package construction has the disadvantage that the package cost is too high and the package structure size is too large, since the area of the common substrate increases as the number of wafers increases.

In order to solve the above conventional problems, in recent years, the stacked wafers have been mounted using a vertical stacking method as shown in FIG. 1G.

1A to 1G are schematic cross-sectional views showing a method of fabricating the conventional semiconductor package 1.

As shown in FIG. 1A, a carrier 10 is provided, which bonds the plurality of first semiconductor elements 11 with an adhesive layer 100, and then stacks the second with the bonding layer 14. The semiconductor element 12 is on the first semiconductor element 11, and the width r of the second semiconductor element 12 is greater than the width w of the first semiconductor element 11.

As shown in FIG. 1B, a support adhesive 15 is formed between the second semiconductor component 12 and the adhesive layer 100. The support adhesive 15 is located at the edge of the second semiconductor component 12, and the support adhesive 15 and the first A gap 13 is formed between the side faces 11c of the semiconductor element 11.

As shown in FIG. 1C, an encapsulation layer 16 is formed on the carrier 10 to cover the support paste 15 and the second semiconductor component 12, and the gap 13 is maintained.

As shown in FIG. 1D, the carrier 10 and the adhesive layer 100 are removed, the package layer 16 is exposed, and the gap 13 becomes a concave region 160, so that the first semiconductor component 11 is located in the concave region 160, and the The second semiconductor component 12 is exposed to the concave region 160.

As shown in FIG. 1E, an insulating material 17 is formed on the encapsulating layer 16 and the supporting adhesive 15 and in the concave region 160, so that the insulating material 17 covers the first semiconductor element 11 and covers the second semiconductor element. 12.

As shown in FIG. 1F, a plurality of first conductive vias 181 and a plurality of second conductive vias 182 are formed in the insulating material 17, and a wiring layer 18 is formed on the insulating material 17, so that the wiring layer 18 is The first conductive vias 181 are electrically connected to the first semiconductor device 11 , and the second conductive vias 182 are electrically connected to the second semiconductor component 12 .

Next, a plurality of conductive elements 19, such as solder balls, are formed on the wiring layer 18, and are connected to other electronic devices.

As shown in Fig. 1G, along the cutting path S as shown in Fig. 1F The single process is diced to form a plurality of semiconductor packages 1.

In the manufacturing method of the conventional semiconductor package 1, the support layer 15 is disposed to form the concave region 160, thereby facilitating filling of the insulating material 17 therein, and forming the first and the first in the insulating material 17. The second conductive vias 181, 182 enable the circuit layer 18 to be electrically connected to the first and second semiconductor components 11, 12.

However, after the encapsulation layer 16 is formed, the support adhesive 15 is easily deformed and deformed by the lateral force of the encapsulation layer 16, as shown in FIG. 1G', thereby covering the electrode pads of the second semiconductor component 12. 120, causing the concave region 160 to be deformed, so that the first and second conductive blind holes 181, 182 cannot be accurately aligned with the electrode pads 120 of the second semiconductor component 12, resulting in a decrease in process yield and even product loss.

Furthermore, the supporting adhesive 15 is formed on the edge of the second semiconductor component 12 by means of dispensing, so that a void V is easily generated, and the supporting adhesive 15 is more susceptible to the lateral force of the encapsulating layer 16. Compression and displacement and deformation, resulting in a decline in process yield.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a semiconductor package comprising: an encapsulation layer having opposite first and second surfaces, and a portion of the first surface is a concave region; a semiconductor device embedded in the concave region, and the second semiconductor device has a second active surface and a second non-active surface; at least one first semiconductor element The first semiconductor element has a first active surface and a first non-active surface, and the second semiconductor element has a width greater than the first portion. a semiconductor device having a width such that a portion of the surface of the second semiconductor component is exposed to the concave region; an insulating material is disposed in the concave region, the insulating material covering the first semiconductor component and covering the second semiconductor The plurality of conductive blind vias are disposed in the insulating material and electrically connected to the first and second semiconductor components respectively; and the circuit layer is disposed on the insulating material and electrically connected to the conductive blind vias.

The present invention provides a method of fabricating a semiconductor package, comprising: providing a carrier on which at least one first semiconductor component is disposed, a second semiconductor component is stacked on the first semiconductor component, and the second semiconductor component is The width is greater than the width of the first semiconductor component, and the first semiconductor component has a first active surface and a first non-active surface, and the second semiconductor component has a second active surface and a second non-active surface; Forming a support material between the carrier and the second semiconductor component, and the support material covers the periphery of the first semiconductor component; forming an encapsulation layer on the carrier to cover the support material and the second semiconductor component The encapsulation layer has a first surface and a second surface opposite to each other, the first surface is coupled to the carrier; the carrier and the support are removed, the first surface of the encapsulation layer is exposed, and the encapsulation layer is The first surface is formed with a concave region, such that the first semiconductor component is exposed in the concave region to expose the first surface of the encapsulation layer, and the second semiconductor component is exposed on the concave surface ; Forming an insulating material in the concave area, so that the first insulating material covering the semiconductor element and covering the second semiconductor element And forming a plurality of conductive blind holes in the insulating material, and forming a wiring layer on the insulating material, the conductive blind vias are electrically connected to the circuit layer, the first and second semiconductor elements.

In the foregoing semiconductor package and method of fabricating the same, the position of the first semiconductor element is within an area of the second semiconductor element.

In the foregoing semiconductor package and method of manufacturing the same, the first active surface is coupled to the carrier, and the first non-active surface is coupled to the second semiconductor component, and after the carrier is removed, the first active surface The first surface of the encapsulation layer is exposed to electrically connect the conductive blind holes.

In the foregoing semiconductor package and method of manufacturing the same, the second active surface is coupled to the first semiconductor component, and after removing the carrier and the support material, the second active surface is exposed to the concave region to be electrically Connect the conductive blind holes. For example, the second non-active surface of the second semiconductor component is exposed on the second surface of the encapsulation layer.

In the above semiconductor package and method of manufacturing the same, the insulating material is disposed on the first surface of the encapsulation layer, and the width of the second semiconductor element is smaller than the maximum width of the concave region.

In addition, in the foregoing semiconductor package and the manufacturing method thereof, the circuit re-wiring structure is formed on the circuit layer and the insulating material, and the circuit redistribution structure is electrically connected to the circuit layer.

As can be seen from the above, the semiconductor package of the present invention and the method for fabricating the same are mainly used to cover the periphery of the first semiconductor component by forming a temporary support material. After the package layer is formed, the carrier and the support material are removed to form the support material. a concave area, which is formed in the concave area, thereby avoiding the support material The method of covering the electrode pads of the second semiconductor component can effectively electrically connect the conductive vias to the first and second semiconductor components to improve the process yield.

1,2,2',2",3‧‧‧ semiconductor packages

10,20‧‧‧Carrier

100,200‧‧‧Adhesive layer

11,21,31,31'‧‧‧First semiconductor component

11c, 21c‧‧‧ side

12,22‧‧‧Second semiconductor components

120‧‧‧electrode pads

13‧‧‧ gap

14,24‧‧‧ bonding layer

15‧‧‧Support glue

16,26‧‧‧Encapsulation layer

160,260,260’‧‧‧ concave area

17,27‧‧‧Insulation

18, 28‧‧‧ circuit layer

181,281‧‧‧First conductive blind hole

182,282‧‧‧Second conductive blind hole

19,29’‧‧‧Conducting components

21a‧‧‧First action surface

21b‧‧‧First non-active surface

210‧‧‧First electrode pad

22a‧‧‧second action surface

22b‧‧‧Second non-active surface

220‧‧‧Second electrode pad

23‧‧‧Semiconductor structure

25‧‧‧Support materials

26a‧‧‧ first surface

26b, 26b’‧‧‧ second surface

260a‧‧‧ side

260b‧‧‧ bottom

260c‧‧‧ openings

271‧‧‧ first blind hole

272‧‧‧Second blind hole

29‧‧‧Line redistribution structure

290‧‧‧ dielectric layer

291‧‧‧ lines

292‧‧‧conductive blind holes

30‧‧‧Insulating protective layer

A, w, r, r’‧‧‧ width

D‧‧‧ caliber

S‧‧‧ cutting path

V‧‧‧ air chamber

1A to 1G are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; wherein, the 1st G' is the actual case of FIG. 1C; and the 2A to 2H are the first embodiment of the semiconductor package of the present invention. A cross-sectional view of an implementation; wherein the 2C' is a second aspect of the 2C, the 2H' and 2H's are other different aspects of the 2H; and the 3A to 3B are A cross-sectional view of a second embodiment of the method of fabricating a semiconductor package of the invention; wherein the 3A' is another aspect of FIG. 3A.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. At the same time, the terms "upper", "first", "second" and "one" as quoted in this specification are also for convenience only. It is to be understood that the scope of the invention is not limited by the scope of the invention.

2A to 2H are schematic cross-sectional views showing a first embodiment of the method of fabricating the semiconductor package 2 of the present invention.

As shown in FIG. 2A, a carrier 20 carrying a semiconductor structure 23 is provided, which is a stack of a first semiconductor component 21 and a second semiconductor component 22, and the second semiconductor component 22 The width r (or area) is greater than the width w (or area) of the first semiconductor element 21.

In this embodiment, the carrier 20 has an adhesive layer 200 for bonding the semiconductor structure 23, and the first semiconductor component 21 is placed on the adhesive layer 200, and then the second semiconductor component 22 is stacked. Single on the first semiconductor element 21.

Furthermore, the first semiconductor component 21 is a wafer having a first active surface 21a and a first non-active surface 21b. The first active surface 21a has a plurality of first electrode pads 210, and the first semiconductor component 21 bonds the adhesive layer 200 of the carrier 20 with the first active surface 21a.

Moreover, the second semiconductor component 22 is a wafer having a second active surface 22a and a second non-active surface 22b. The second active surface 22a has a plurality of second electrode pads 220, and the second semiconductor component 22 The first non-active surface 21b of the first semiconductor element 21 is bonded by its second active surface 22a. Preferably, the second active surface 22a of the second semiconductor component 22 is bonded to the first non-active surface 21b of the first semiconductor component 21 by a bonding layer 24. The bonding layer 24 may be formed on a partial region (as shown in FIG. 2A) or all regions (shown in FIG. 3A) of the first non-active surface 21b.

In addition, the material forming the adhesive layer 200 is a release material such as a Thermal Release Tape or a UV Release Tape, and the material forming the bonding layer 24 is an acrylic type ( Acryclic) glue.

As shown in FIG. 2B, a support member 25 is formed between the second active surface 22a of the second semiconductor element 22 and the adhesive layer 200, and the support member 25 covers the periphery of the first semiconductor element 21.

In this embodiment, the support material 25 extends beyond the width r of the second semiconductor component 22 to support the second semiconductor component 22, and the support material 25 is coupled to the side surface 21c of the first semiconductor component 21, That is, there is no gap between the support member 25 and the side surface 21c of the first semiconductor element 21, which is more advantageous for supporting the second semiconductor element 22.

Furthermore, the support material 25 is formed by Dispensing, and is made of a temporary material such as a photoresist or an Acryclic adhesive material, wherein the adjustability of the photoresist is higher. Large, so in the subsequent process, the support material 25 can be easily displaced and deformed.

As shown in FIG. 2C, an encapsulation layer 26 is formed on the adhesive layer 200 of the carrier 20 to encapsulate the support material 25 and the second semiconductor component 22, and the encapsulation layer 26 has a first surface 26a opposite thereto. The second surface 26b is bonded to the adhesive layer 200 of the carrier 20.

In this embodiment, the first surface 26a of the encapsulation layer 26 is flush with the first active surface 21a of the first semiconductor component 21, and the second semiconductor element The member 22 is embedded inside the second surface 26b of the encapsulation layer 26 such that the second surface 26b of the encapsulation layer 26 covers the second non-active surface 22b of the second semiconductor component 22.

Moreover, in another aspect, the second surface 26b' of the encapsulation layer 26 can expose the second non-active surface 22b of the second semiconductor component 22. As shown in FIG. 2C', the second surface 26b' of the encapsulation layer 26 is flush with the second non-active surface 22b of the second semiconductor component 22, exposing the second non-active surface 22b of the second semiconductor component 22. On the second surface 26b' of the encapsulation layer 26.

As shown in FIG. 2D, the carrier 20, the adhesive layer 200 and the support member 25 are removed, and the first surface 26a of the encapsulation layer 26 is exposed, and the first surface 26a of the encapsulation layer 26 is formed with a concave region 260. The first semiconductor component 21 is disposed in the concave region 260, and the second active surface 22a of the second semiconductor component 22 is exposed to the concave region 260.

In the present embodiment, the carrier member 20 is removed by the release property of the adhesive layer 200, and the support member 25 is removed by chemical stripping (Stripper Chemicals) or plasma cleaning.

Furthermore, the concave region 260 has a side portion 260a and a bottom portion 260b and an opening 260c opposite to the bottom portion 260b, and the concave portion 260 is caused by the support member 25, and the support member 25 extends beyond The width R of the second semiconductor element 22 is such that the aperture D of the opening 260c is greater than the width A of the bottom portion 260b, and the width r of the second semiconductor element 22 is less than or equal to the width A of the bottom portion 260b, that is, the first The width r of the second semiconductor component 22 is less than the maximum width of the concave region 260 (e.g., aperture D).

The first active surface 21a of the first semiconductor component 21 (including the first electrode pad 210) is exposed on the first surface 26a of the encapsulation layer 26, and the second active surface 22a of the second semiconductor component 22 ( The second electrode pad 220 is exposed to the bottom surface 260b of the concave region 260 and the first surface 26a of the encapsulation layer 26.

In addition, the second active surface 22a of the second semiconductor component 22 protrudes from the bottom 260b of the concave region 260 according to the layout of the support member 25; in other embodiments, the second semiconductor component 22 is second. The active surface 22a can also be flush with the bottom 260b of the concave region 260' as shown in the 2H" diagram.

As shown in FIG. 2E, the insulating material 27 is formed on the first surface 26a of the encapsulation layer 26 and in the concave surface 260, so that the insulating material 27 covers the first active surface 21a of the first semiconductor element 21 and The side surface 21c covers the second active surface 22a of the second semiconductor element 22, and the second active surface 22a of the second semiconductor element is bonded to the insulating material 27.

In the present embodiment, the insulating material 27 is formed by coating or other means, and the insulating material 27 is a single structure, that is, a structure completed by using one material in a single process. In other embodiments, the insulating material 27 may be formed of a plurality of materials, that is, the concave region 260 is first filled with one material, and the first surface 26a of the encapsulating layer 26 is formed of another material.

Further, the insulating material 27 is a liquid organic material such as polyimide (PI) or other materials (such as SiO ₂ , SiN _X ), which can be regarded as a passivation layer.

As shown in FIG. 2F, a plurality of first blind vias 271 and second blind vias 272 are formed in the insulating material 27, and the first semiconductor element 21 is first The electrode pad 210 is exposed to the first blind via 271 , and the second electrode pad 220 of the second semiconductor component 22 is exposed to the second blind via 272 .

In the embodiment, the first blind via 271 and the second blind via 272 are formed by an exposure and development process.

Furthermore, the first blind via 271 having a shallower hole depth may be formed first, and then the second blind via 272 having a deeper hole depth may be formed; or the first blind via 271 and the second blind via 272 may be simultaneously fabricated. .

As shown in FIG. 2G, a plurality of first conductive blind vias 281 are formed in the first blind vias 271, and a plurality of second conductive vias 282 are formed in the second blind vias 272, and a wiring layer 28 is formed thereon. On the insulating material 27, the circuit layer 28 is electrically connected to the first electrode pad 210 by the first conductive vias 281, and electrically connected to the second electrode pad 220 by the second conductive vias 282. .

Then, an insulating protective layer 30 is formed on the circuit layer 28 and the insulating material 27, and the circuit layer 28 is exposed to form a plurality of conductive elements 29' such as solder balls on the exposed surface of the circuit layer 28 for external connection. Other electronic components.

As shown in Fig. 2H, a singulation process is performed along the dicing path S as shown in Fig. 2G to fabricate a plurality of semiconductor packages 2.

Further, when the process of the 2C' drawing is continued, the semiconductor package 2' shown in Fig. 2H' is formed.

Moreover, in another embodiment, as shown in the second semiconductor package 2", a circuit redistribution structure 29 may be formed on the circuit layer 28 and the insulating material 27, and the circuit re-arrangement structure 29 electrically connecting the circuit layer 28, The conductive elements 29' are then formed and a singulation process is performed. In detail, the circuit redistribution structure 29 has at least one dielectric layer 290, a circuit 291 coupled to the dielectric layer 290, and a conductive via 292 located in the dielectric layer 290, such that the line 291 is formed by the conductive via hole. The circuit layer 28 is electrically connected to the circuit layer 28, and the insulating protection layer 30 is formed on the circuit redistribution structure 29 to expose the circuit 291 so that the conductive elements 29' are disposed on the exposed surface of the line 291.

3A to 3B are schematic cross-sectional views showing a second embodiment of the method of fabricating the semiconductor package 3 of the present invention. The difference between this embodiment and the first embodiment is only in the aspect of the semiconductor structure 23, and other processes are substantially the same, so only the differences will be described below.

As shown in FIG. 3A, a plurality of first semiconductor elements 31 are disposed on the carrier 20, and the second semiconductor elements 22 are stacked on the first semiconductor elements 31 to support the first semiconductor elements 31. The second semiconductor element 22.

In this embodiment, the positions of the first semiconductor elements 31 are within the width r' of the second semiconductor elements 22.

Further, the first semiconductor elements 31 are of the same specification; or, as shown in Fig. 3A', at least two of the first semiconductor elements 31, 31' are of different specifications.

As shown in FIG. 3B, a process as shown in FIGS. 2B to 2H is performed to fabricate the semiconductor package 3.

In the manufacturing method of the present invention, the support material 25 is used as a temporary material, so that after the encapsulation layer 26 is formed, the support material 25 is removed, and the support material is filled. The insulating material 27 is in the concave surface 260, 260'. Therefore, when the first blind hole 271 and the second blind hole 272 are formed, the support material 25 does not cover the second electrode pad 220 of the second semiconductor component 22, so that the The first blind hole 271 and the second blind hole 272 can be accurately aligned with the first and second electrode pads 210, 220.

Moreover, even if the support material 25 is displaced and deformed by the lateral force of the encapsulation layer 26, when the first blind hole 271 and the second blind hole 272 are formed, since the support material 25 has been removed, the support material 25 is removed. The second electrode pad 220 is still not covered by the support material 25.

Moreover, the support member 25 is bonded to the side surface 21c of the first semiconductor element 21 to provide the support member 25 having a strong structural strength. Therefore, even if the support member 25 is pressed by the lateral force of the encapsulation layer 26, only A slight deformation is produced, that is, the amount of deformation of the concave regions 260, 260' is within an error range, so that the encapsulation layer 26 still does not cover the second electrode pad 220 of the second semiconductor component 22.

Therefore, compared with the prior art, the method of the present invention removes the support material 25 and then forms the insulating material 27, thereby preventing the support material 25 from covering the second electrode pad 220 of the second semiconductor element 22. The first blind hole 271 and the second blind hole 272 can be accurately aligned with the first and second electrode pads 210, 220, so that the first and second conductive blind holes 281, 282 can be electrically connected. The first and second electrode pads 210, 220 are used to increase the process yield.

The present invention provides a semiconductor package 2, 2', 2", 3, comprising: a package layer 26 having a concave region 260, 260', a second semiconductor component 22 embedded in the concave region 260, 260', At least one first semiconductor located in the concave region 260, 260' and superposed on the second semiconductor element 22 The element 21, the insulating material 27 disposed in the concave regions 260, 260', the plurality of first and second conductive blind holes 281, 282 disposed in the insulating material 27, and one of the wiring layers 28 disposed on the insulating material 27.

The encapsulation layer 26 has opposite first and second surfaces 26a, 26b, and the concave regions 260, 260' are disposed on the first surface 26a.

The first semiconductor component 21 has a first active surface 21a and a first non-active surface 21b. The first active surface 21a is on the same side as the first surface 26a of the encapsulation layer 26.

The second semiconductor component 22 is embedded in the encapsulation layer 26 and has a second active surface 22a and a second non-active surface 22b. The second active surface 22a is bonded to the first non-active surface 21b. The width r, r' of the second semiconductor component 22 is greater than the width w of the first semiconductor component 21 and less than or equal to the width A of the bottom portion 260b, so that the second active surface 22a of the second semiconductor component 22 is exposed. The concave regions 260, 260' are joined to the insulating material 27.

The insulating material 27 is disposed on the first surface 26a of the encapsulation layer 26 and covers the first semiconductor element 21 and the second active surface 22a covering the second semiconductor element 22.

The first conductive via 281 is electrically connected to the first active surface 21a of the first semiconductor component 21.

The second conductive via 282 is electrically connected to the second active surface 22a of the second semiconductor component 22.

The circuit layer 28 is electrically connected to the first and second conductive blind holes 281, 282.

In one embodiment, the concave region 260 is provided with a plurality of the first semiconductor elements 31, 31', and the first semiconductor elements 31, 31' support the second semiconductor element 22, and the first semiconductors The position of the elements 31, 31' is within the width r' (or area) of the second semiconductor element 22.

In one embodiment, the second non-active surface 22b' of the second semiconductor component 22 is exposed on the second surface 26b of the encapsulation layer 26.

In one embodiment, the semiconductor package 2 ′′ includes a line redistribution structure 29 , which is disposed on the circuit layer 28 and the insulating material 27 and electrically connected to the circuit layer 28 .

In summary, the semiconductor package of the present invention and the method for fabricating the same, the first semiconductor element is coated by the support material as a temporary material to provide a structure with high strength, so that it is difficult to form the package layer. Displaced and deformed by the lateral force of the encapsulation layer, and the support material is removed first, and then the insulating material is formed, thereby preventing the support material from covering the second electrode pad of the second semiconductor component, so that The first and second conductive blind vias can be electrically connected to the first and second electrode pads to improve process yield.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Semiconductor package

21‧‧‧First semiconductor component

21a‧‧‧First action surface

21b‧‧‧First non-active surface

22‧‧‧Second semiconductor component

22a‧‧‧second action surface

22b‧‧‧Second non-active surface

26‧‧‧Encapsulation layer

26a‧‧‧ first surface

26b‧‧‧ second surface

260‧‧‧ concave area

27‧‧‧Insulation

28‧‧‧Line layer

281‧‧‧First conductive blind hole

282‧‧‧Second conductive blind hole

29’‧‧‧Conducting components

30‧‧‧Insulating protective layer

w, r‧‧‧Width

Claims (16)

A semiconductor package comprising: an encapsulation layer having opposite first and second surfaces, wherein a portion of the first surface is a concave region; a second semiconductor component embedded in the concave region, and The second semiconductor component has a second active surface and a second non-active surface; at least one first semiconductor component is disposed in the recessed region and is stacked on the second semiconductor component, and the first semiconductor component has The first active surface and the first non-active surface are opposite to each other, and the width of the second semiconductor component is greater than the width of the first semiconductor component to expose a portion of the surface of the second semiconductor component to the concave region; Provided in the concave region, the insulating material covers the first semiconductor component and covers the second semiconductor component; the plurality of conductive blind vias are disposed in the insulating material and electrically connected to the first and second semiconductors respectively And a circuit layer disposed on the insulating material and electrically connected to the conductive blind holes. The semiconductor package of claim 1, wherein the position of the first semiconductor element is within an area of the second semiconductor element. The semiconductor package of claim 1, wherein the first active surface is on the same side of the first surface of the encapsulation layer, and the first active surface is electrically connected to the conductive blind holes, and the Second non-active surface The second semiconductor component is bonded. The semiconductor package of claim 1, wherein the second active surface is bonded to the first semiconductor component and covered with the insulating material, and the second active surface is electrically connected to the conductive blind vias. The semiconductor package of claim 4, wherein the second non-active surface of the second semiconductor component is exposed on the second surface of the encapsulation layer. The semiconductor package of claim 1, wherein the insulating material is disposed on the first surface of the encapsulation layer. The semiconductor package of claim 1, wherein the width of the second semiconductor component is less than a maximum width of the concave region. The semiconductor package of claim 1, further comprising a circuit redistribution structure disposed on the circuit layer and the insulating material and electrically connected to the circuit layer. A method of fabricating a semiconductor package, comprising: providing a carrier on which at least one first semiconductor component is disposed, a second semiconductor component is stacked on the first semiconductor component, and a width of the second semiconductor component is greater than the first a width of a semiconductor component, the first semiconductor component having a first active surface and a first non-active surface, and the second semiconductor component having a second active surface and a second non-active surface; forming a support material Between the carrier and the second semiconductor component, and the support material covers the periphery of the first semiconductor component; forming an encapsulation layer on the carrier to cover the support material and the first a second semiconductor component, the encapsulation layer has a first surface and a second surface opposite to each other, the first surface is coupled to the carrier; the carrier and the support are removed, the first surface of the encapsulation layer is exposed, and the a first surface of the encapsulation layer is formed with a concave region, wherein the first semiconductor component is exposed in the concave region to expose the first surface of the encapsulation layer, and the second semiconductor component is exposed to the concave region; In the concave region, the insulating material covers the first semiconductor element and covers the second semiconductor element; and a plurality of conductive blind holes are formed in the insulating material, and a wiring layer is formed on the insulating material to make the conductive materials The blind via is electrically connected to the circuit layer, the first and second semiconductor elements. The method of fabricating a semiconductor package according to claim 9, wherein the position of the first semiconductor element is within an area of the second semiconductor element. The method of manufacturing the semiconductor package of claim 9, wherein the first active surface is coupled to the carrier, and the first non-active surface is coupled to the second semiconductor component, and the carrier is removed After the device is exposed, the first active surface is exposed on the first surface of the encapsulation layer to electrically connect the conductive blind vias. The method of manufacturing the semiconductor package of claim 9, wherein the second active surface is combined with the first semiconductor component, and after the carrier and the support material are removed, the second active surface is The concave area is exposed to electrically connect the conductive blind holes. The method of manufacturing a semiconductor package as described in claim 12, The second non-active surface of the second semiconductor component is exposed on the second surface of the encapsulation layer. The method of fabricating a semiconductor package according to claim 9, wherein the insulating material is disposed on the first surface of the encapsulation layer. The method of fabricating a semiconductor package according to claim 9 wherein the width of the second semiconductor component is less than a maximum width of the concave region. The method of fabricating a semiconductor package according to claim 9 further comprises forming a line redistribution structure on the circuit layer and the insulating material, and the circuit redistribution structure is electrically connected to the circuit layer.