TW201508840A - Thin film transistor and matrix circuit - Google Patents

Abstract

This thin film transistor (10) is a bottom-gate thin film transistor that is provided with a gate electrode (30), a gate insulating film (40), a semiconductor layer (60), a source electrode (70) and a drain electrode (80). This thin film transistor (10) is also provided with electrode wiring lines (71, 81) that extend respectively from the source electrode (70) and the drain electrode (80), and an insulating resin part (50) that is provided on the gate insulating film (40) so as to intervene between the electrode wiring lines (71, 81) and the gate insulating film (40). The insulating resin part (50) is provided at least at a position where the outer peripheral portion of the gate electrode (30) and the electrode wiring lines (71, 81) overlap each other.

Description

Thin film transistor and matrix circuit

The present invention relates to thin film transistors and matrix circuits including thin film transistors.

On the insulating substrate, a gate electrode type thin film transistor composed of a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, and a drain electrode is known (for example, refer to Patent Document 1).

[advance technical documents]

[Patent Document 1] Patent No. 4194436

In the above-mentioned thin film transistor, when the gate insulating film is formed by ink coating, the film at the end of the gate electrode is likely to be thin. Therefore, the electric field concentration at the tip end portion of the gate electrode is short-circuited between the gate electrode and the source/drain electrode wiring, and the response speed is lowered because a large parasitic capacitance is generated. On the other hand, when a thick gate insulating film is formed, the output characteristics of the thin film transistor are damaged due to a decrease in gate storage capacitance.

The problem to be solved by the present invention is to provide a thin film transistor, and a matrix circuit including the thin film transistor, while maintaining output characteristics, Strong suppression of short circuit failure or reduced parasitic capacitance.

[1] The thin film transistor according to the present invention is a lower gate type thin film transistor including a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, and a drain electrode, including the source electrode and the source electrode, respectively An electrode wiring extending from the drain electrode, and an insulating resin portion interposed between the electrode wiring and the gate insulating film provided on the gate insulating film, wherein the insulating resin portion is provided at least outside the gate electrode The edge portion is overlapped with the electrode wiring described above.

[2] In the above invention, the insulating resin portion protrudes convexly from a surface on which the gate insulating film is formed, and the forming surface is a surface on which at least the semiconductor layer is formed.

[3] In the above invention, the topmost portion of the insulating resin portion may be relatively high with respect to the topmost portion of the semiconductor layer.

[4] In the above invention, the insulating resin portion may have a first inclined surface and become higher as it goes away from the semiconductor layer; and the second inclined surface may be located outside the first inclined surface and may change from the semiconductor layer. low.

[5] In the above invention, the inclination angle of the second inclined surface may be relatively large with respect to the inclination angle of the first inclined surface.

[6] In the above invention, the gate insulating film has an inclined surface located outside the forming surface, and an inclination angle of the second inclined surface may be relatively large with respect to an inclination angle of the inclined surface of the gate insulating film.

[7] In the above invention, the gate insulating film has the above An inclined surface on the outer side of the surface and a flat surface on the outer side of the inclined surface are formed, and an end of the second inclined surface may be located on the flat surface of the gate insulating film.

[8] In the above invention, the electrode wiring includes the source a source electrode line extending from the electrode and a drain electrode line extending from the drain electrode; and the insulating resin portion may include a first portion provided on a portion overlapping the outer edge portion of the gate electrode and the source electrode line An insulating resin portion and a second insulating resin portion provided on a portion where the outer edge portion of the gate electrode and the gate electrode wiring overlap.

[9] In the above invention, the insulating resin portion has a rectangular frame shape as viewed in plan, and the semiconductor layer may be surrounded by the insulating resin portion.

[10] A matrix circuit according to the present invention, comprising: m × n of said thin film transistors, wherein m × n of said thin film transistors are arranged in m rows and n columns along first and second directions, said insulating resin portion Individually disposed in m × n of the above thin film transistors.

[11] In the above aspect of the invention, the matrix circuit further includes n first connection wires electrically connecting the source electrode or the drain electrode of the m thin film transistors arranged along the first direction; and m The second connection wiring electrically connects the gate electrodes of the n thin film transistors arranged along the second direction, and the insulating resin portion is interposed between the first connection wiring and the second connection wiring. It may be provided at an intersection of the first connection wiring and the second connection wiring.

According to the present invention, since the insulating resin portion is provided at least at the gate The overlapping portion of the outer edge portion of the pole and the electrode wiring can enlarge the interval between the outer edge portion of the gate electrode and the electrode wiring even if the gate insulating film is not thickened. Therefore, while maintaining the output characteristics of the thin film transistor, it is possible to enhance suppression of short-circuit defects or reduce parasitic capacitance.

10‧‧‧film transistor

20‧‧‧Insulating substrate

30‧‧‧gate electrode

31‧‧‧gate electrode wiring

40‧‧‧gate insulating film

41‧‧‧Formation

42‧‧‧Sloping surface

43‧‧‧flat surface

50, 50B‧‧‧Insulating Resin Department

501‧‧‧ openings

51‧‧‧1st Insulating Resin Department

511‧‧‧1st inclined surface

512‧‧‧2nd inclined surface

513‧‧‧ top

52‧‧‧2nd Insulating Resin Department

521, 522‧‧‧ sloped surface

523‧‧‧ top

53‧‧‧3rd Insulating Resin Department

54‧‧‧4th Insulating Resin Department

60‧‧‧Semiconductor layer

61‧‧‧ top

70‧‧‧Source electrode

71‧‧‧Source electrode wiring

80‧‧‧汲electrode

81‧‧‧汲 electrode wiring

100‧‧‧Matrix circuit

110‧‧‧1st scan wiring

120‧‧‧2nd scan wiring

130‧‧‧3rd scan wiring

h ₁ ‧‧‧height

h ₂ ‧‧‧height

‧‧‧‧ tilt angle

‧‧‧‧ tilt angle

Γ‧‧‧ tilt angle

[Fig. 1] Fig. 1 is a cross-sectional view showing a thin film transistor in an embodiment of the present invention; [Fig. 2] Fig. 2 is a plan view showing a thin film transistor in an embodiment of the present invention; [Fig. 3] 3 is a plan view showing a first modification of the thin film transistor in the embodiment of the present invention; and FIG. 4 is a cross-sectional view showing a second modification of the thin film transistor in the embodiment of the present invention; And [Fig. 5] Fig. 5 is a plan view showing a matrix circuit in the embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described based on the drawings.

1 and 2 are a cross-sectional view and a plan view showing a thin film transistor in an embodiment of the present invention, and Fig. 3 is a plan view showing a first modification of the thin film transistor in the present embodiment, and Fig. 4 is a view showing the present invention. A cross-sectional view of a second modification of the thin film transistor in the embodiment.

The thin film transistor (TFT: thin film transistor) 10 of the present embodiment, as shown in FIGS. 1 and 2, includes a gate electrode 30, a gate insulating film 40, and a gate electrode. The edge resin portion 50, the semiconductor layer 60, the source electrode 70, and the drain electrode 80 are sequentially laminated on the insulating substrate 20.

Insulating substrate 20 is made of polyethylene naphthalate (PEN) The substrate is formed to have a thickness of about 100 μm. The material constituting the insulating substrate 20 is not particularly limited to the above, and is, for example, a resin material such as polyethylene terephthalate (PET) or polyamidamine (PI), and is made of glass. Ceramics and the like may also be used. Moreover, the thickness of the insulating substrate 20 is not particularly limited to the above, and can be arbitrarily set.

The gate electrode 30 is provided on the insulating substrate 20. This gate The electrode 30 is formed by, for example, printing a conductive ink by gravure printing and hardening. The conductive ink constituting the gate electrode 30 may, for example, be a nano metal particle containing, for example, silver (Ag) or gold (Au). Further, the printing method of the gate electrode 30 is not particularly limited to the above, and may be, for example, screen printing or gravure lithography.

Further, in place of the conductive ink, gold (Au), silver (Ag), and the like are used. Conductive paste such as carbon (C), organic resin hydrochloric acid of a paste-forming organometallic compound, or an organic conductive material such as PEDOT (poly 3,4-ethylenedioxythiophene), etc., and the gate electrode 30 is also formed. can.

Further, the method of manufacturing the gate electrode 30 is not particularly limited to the printing method. The gate electrode 30 may be formed by a sputtering method, a vacuum deposition method, a chemical vapor deposition method (CVD method), an electroless plating method, an electrolytic plating method, or a combination thereof. In this case, the material constituting the gate electrode 30 may be exemplified by, for example, chromium (Cr), titanium (Ti), copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), and nickel (Ni). ), gold (Au), palladium (Pd), platinum (Pt), silver (Ag), tin (Sn), tantalum (Ta) or an alloy containing at least one of them.

As shown in Fig. 2, the gate electrode wiring 31 is connected to the gate electrode. In the pole 30, the gate electrode wiring 31 extends from the gate electrode 30 to the outside of the thin film transistor 10. This gate electrode wiring 31 is formed integrally with the gate electrode 30 at the same time.

Further, the gate electrode 30 and the gate electrode wiring 31 may be individually form. Both of the gate electrode 30 and the gate electrode wiring 31 may be made of the above materials, and the material constituting the gate electrode 30 may be the same as or different from the material constituting the gate electrode wiring 31. Further, the gate electrode 30 and the gate electrode wiring 31 may be formed by the above-described manufacturing method, and the method of manufacturing the gate electrode 30 and the method of manufacturing the gate electrode wiring 31 may be the same or different from each other.

As shown in FIG. 1, the gate insulating film 40 covers the gate electrode 30 and is laminated on the insulating substrate 20. The gate insulating film 40 has a forming surface 41 on which the semiconductor layer 60 is formed, an inclined surface 42 located outside the forming surface 41, and a flat surface 43 located further outside the inclined surface 42. Further, in the present embodiment, the maximum range of the formation surface 41 of the gate insulating film 40 is the same as that of the upper surface of the gate electrode 30. This gate insulating film 40 is formed by, for example, coating a polyvinylphenol (PVP) ink by a bar coat method and hardening. Moreover, the resin material constituting the gate insulating film 40 is not particularly limited to the above. Furthermore, if the material constituting the gate insulating film 40 is not limited to the resin material, for example, the gate electrode 41 using an aluminum (Al), aluminum oxide, this may be a surface (AlO _X) covered film. Further, the method of applying the gate insulating film 40 is not particularly limited, and may be, for example, screen printing, gravure printing, or gravure lithography.

The insulating resin portion 50 is composed of two insulating resin portions 51 and 52 provided on the gate insulating film 40. This insulating resin portion 50 is, for example, intaglio The printing method prints a phenol resin ink and hardens it. Further, the resin material constituting the insulating resin portion 50 is not particularly limited to the above, and for example, polyester, polyvinyl alcohol, polyvinyl ether, polyimide or polyimide may be used. ), polyamide, cellulose, Epoxy resin, acrylic resin, urethane resin, enamel resin, and the like. Moreover, the printing method of the insulating resin portion 50 is not particularly limited, and may be, for example, screen printing or gravure printing. Further, the insulating resin portion 50 of the present embodiment has a hardness substantially equal to that of the gate insulating film 40, but the insulating resin portion 50 can be harder than the gate insulating film 40, and the gate insulating film is not limited thereto. 40 may be harder than the insulating resin portion 50.

In this embodiment, as shown in FIG. 2, the first and second insulating trees The grease portions 51 and 52 are respectively provided in a portion overlapping the outer edge portion of the gate electrode 30 and the electrode wires 71 and 81 (described later) as viewed in a plan view. Specifically, the first insulating resin portion 50A is planar. A portion (intersection portion) which is overlapped between the outer edge portion of the gate electrode 30 and the source electrode wiring 71 is provided. On the other hand, the second insulating resin portion 50B is provided at a portion (intersection portion) where the outer edge portion of the gate electrode 30 and the drain electrode wiring 81 overlap each other as viewed in plan.

Thus, in the present embodiment, the outer edge portion of the gate electrode 30 is electrically In the overlapping portions of the pole wirings 71 and 81, the first and second insulating resin portions 51 and 52 are provided, and the gate insulating film 40 can be enlarged, and the outer edge portion of the gate electrode 30 and the electrode wiring 71 can be enlarged. The interval between 81. Therefore, while maintaining the output characteristics of the thin film transistor 10, it is possible to enhance suppression of short-circuit defects or to reduce parasitic capacitance.

Moreover, when the insulating resin portion is formed over the entire surface of the thin film transistor, When the resin material hardens and shrinks, the channel bends or contracts, and the distance between the channel electrodes changes. I am afraid that the characteristics of the thin film transistor change. On the other hand, in the present embodiment, the insulating resin portion 50 is provided only in a necessary portion, and since the bending or contraction of the passage can be suppressed, the characteristics of the thin film transistor can be maintained. Further, the distance from the end of the gate electrode 30 to the end portions of the insulating resin portions 51 and 52 is preferably from about 100 μm to about 500 μm as viewed in plan.

As shown in FIG. 1, the first insulating resin portion 51 has a convex shape that protrudes upward from the forming surface 41 of the gate insulating film 40.

In the present embodiment, the height h ₁ of the topmost portion 513 of the first insulating resin portion 51 (the distance from the upper surface of the insulating substrate 20 in the vertical direction in the first drawing to the topmost portion 513 in the first drawing) is the highest for the semiconductor layer 60. The height h _{2 of} the top portion 61 (the distance from the upper surface of the insulating substrate 20 in the vertical direction in the first drawing to the topmost portion 61 in the first drawing) is relatively high (h ₁ > h ₂ ). Therefore, the interval between the gate electrode 30 and the source electrode wiring 71 can be further increased, and the short-circuit defect between the gate electrode 30 and the source electrode wiring 71 can be further suppressed. Further, the topmost portion 513 of the first insulating resin portion 51 is the highest portion of the first insulating resin portion 51, and the topmost portion 61 of the semiconductor layer 60 is also the highest portion of the semiconductor layer 60.

Further, the first insulating resin portion 51 has two inclined surfaces 511 and 512.

The first inclined surface 511 constitutes the inner side surface of the first insulating resin portion 51, and is inclined as it goes away from the semiconductor layer 60. On the other hand, the second inclined surface 512 forms the outer surface of the first insulating resin portion 51 and is inclined as it goes away from the semiconductor layer 60.

In this embodiment, as shown in FIG. 1, the second inclined surface 512 The inclination angle α is relatively large (α>β) with respect to the inclination angle β of the first inclined surface 511, and the inclination of the second inclined surface 512 is faster than the inclination of the first inclined surface 511. Therefore, the size of the first insulating resin portion 51 can be reduced, and the thinning of the thin film transistor 10 can be enhanced. Further, the inclination angle α of the second inclined surface 512 is an angle formed by the second inclined surface 512 with respect to the upper surface of the insulating substrate 20 with respect to a substantially parallel plane. In addition, the inclination angle β of the first inclined surface 511 is an angle formed by the first inclined surface 511 on a plane substantially changed from the upper surface of the insulating substrate 20.

Further, in the present embodiment, as shown in Fig. 1, the second inclined surface 512 The flat surface 43 of the gate insulating film 40 is extended, and the outer end of the second inclined surface 512 is located on the flat surface 43 of the gate insulating film 40. Therefore, the interval between the gate electrode 30 and the source electrode wiring 71 can be further increased, and the short-circuit failure between the gate electrode 30 and the source electrode wiring 71 can be further enhanced.

Further, in the present embodiment, as shown in Fig. 1, the second inclined surface 512 The inclination angle α is relatively large (α>γ) with respect to the inclination angle γ of the gate insulating film 40, and the inclination of the second inclined surface 512 becomes more urgent than the inclination of the inclined surface 42 of the gate insulating film 40. . Therefore, the size of the first insulating resin portion 51 can be reduced, and the thinning of the thin film transistor 10 can be enhanced. Moreover, the inclined surface 42 of the gate insulating film 40 is inclined by an angle γ, and the angle formed by the inclined surface 42 is based on a plane substantially changed from the upper surface of the insulating substrate 20.

Similarly, the second insulating resin portion 52 also has insulation from the gate. The forming surface 41 of the film 40 has a convex shape that protrudes upward.

In the present embodiment, the topmost portion 523 of the second insulating resin portion 52 The height is relatively high for the height of the topmost portion 61 of the semiconductor layer 60. Therefore, the interval between the gate electrode 30 and the drain electrode wiring 81 can be further increased, and the short-circuit failure between the gate electrode 30 and the drain electrode wiring 81 can be further enhanced. Further, the topmost portion 523 of the second insulating resin portion 52 is the highest portion of the second insulating resin portion 52.

Further, the second insulating resin portion 52 has two inclined surfaces 521 and 522.

The first inclined surface 521 constitutes the inner side surface of the second insulating resin portion 52, and is inclined as the forming surface 41 away from the semiconductor layer 60 becomes higher. On the other hand, the second inclined surface 522 constitutes the outer surface of the second insulating resin portion 52 and is inclined as it goes away from the semiconductor layer 60.

Similarly to the first insulating resin portion 51, the inclination angle of the second inclined surface 522 of the second insulating resin portion 52 is relatively increased with respect to the inclination angle of the first inclined surface 521, and the inclination of the second inclined surface 522 is increased. 1 The inclination of the inclined surface 521 is more urgent. Therefore, the size of the second insulating resin portion 52 can be reduced, and the thinning of the thin film transistor 10 can be enhanced.

Further, in the present embodiment, as shown in Fig. 1, the second inclined surface 522 extends to the flat surface 43 of the gate insulating film 40, and the outer end portion of the second inclined surface 522 is located at the flat surface of the gate insulating film 40. On face 43. Therefore, the interval between the gate electrode 30 and the drain electrode wiring 81 can be further increased, and the short-circuit failure between the gate electrode 30 and the drain electrode wiring 81 can be further enhanced.

Further, similarly to the first insulating resin portion 51, the inclination angle of the second inclined surface 522 is relatively larger with respect to the inclination angle of the inclined surface 42 of the gate insulating film 40, and the inclination of the second inclined surface 522 is compared with the gate. Pole of insulating film 40 The inclination of the slope 42 becomes more urgent. Therefore, the size of the second insulating resin portion 52 can be reduced, and the thinning of the thin film transistor 10 can be enhanced.

Such an inclined surface 511 is provided in the insulating resin portions 51, 52, In 512, 521, and 522, the electrode wirings 71 and 81 to the insulating resin portions 51 and 52 are easily formed. Moreover, in order to suppress disconnection of the electrode wires 71 and 81, the thickness of the insulating resin portions 51 and 52 is preferably 5 μm or less.

Moreover, as shown in Fig. 3, the insulating resin portion 50B is viewed from the plane It is also possible to have a rectangular frame shape. In this case, as shown in the figure, the semiconductor layer 60 is formed in the opening 501 of the insulating resin portion 50B, and the semiconductor layer 60 is surrounded by the insulating resin portion 50B. Therefore, the wet expansion of the semiconductor layer 60 can be suppressed, and the channel size can be specified with high precision. Further, although not particularly illustrated, the inner side surface and the outer side surface of the insulating resin portion 50B are also formed by inclined surfaces similar to those of the first and second inclined surfaces, respectively.

Returning to Figures 1 and 2, the semiconductor layer 60 is disposed on the gate insulating film. 40 is formed on the face 41. This semiconductor layer 60 is formed, for example, by inkjet printing by printing TIPS and pentacene chloroform (Pentacene Chloroform) solution.

Moreover, the material constituting the semiconductor layer 60 is not particularly limited to the above. Polymer materials such as P3HT (poly-3-hexylthiophene) and F8T2 (poly(9,9-dioctyfluorene-co-bithiophene)) can also be used. Or a carbon compound such as a carbon nanotube or a fullerene having a semiconductor property. The method for producing the semiconductor layer 60 is not particularly limited to a printing method, and a sputtering method, a vacuum evaporation method, or the like is used. The semiconductor layer 60 may be formed by a chemical vapor deposition method or a spin coating method.

The source electrode 70 and the drain electrode 80 are disposed on the semiconductor layer 60 on. A predetermined interval is formed between the source electrode 70 and the drain electrode 80.

The source electrode wiring 71 is connected to the source electrode 70. This source electrode The wiring 71 extends from the source electrode 70 over the first insulating resin portion 51 to the outside of the thin film transistor 10. The source electrode 70 and the source electrode wiring 71 are integrally formed by, for example, printing a silver (Ag) ink by gravure printing. In addition, the material and the manufacturing method of the source electrode 70 and the source electrode wiring 71 are not particularly limited to the above, and may be formed by the materials and manufacturing methods exemplified in the gate electrode 50.

Further, the source electrode 70 and the source electrode wiring 71 may be individually form. The source electrode 70 and the source electrode wiring 71 may be made of the above materials, and the materials constituting the source electrode 70 and the source electrode wiring 71 may be the same or different from each other. Further, the source electrode 70 and the source electrode wiring 71 may be formed by the above-described manufacturing method, and the method of manufacturing the source electrode 70 and the method of manufacturing the source electrode wiring 71 may be the same or different from each other.

Similarly, the drain electrode wiring 81 is connected to the drain electrode 80. this The drain electrode wiring 81 extends beyond the second insulating resin portion 52 to the outside of the thin film transistor 10. The drain electrode 80 and the drain electrode wiring 81 are integrally formed by, for example, printing a silver (Ag) ink by gravure printing. In addition, the material and the manufacturing method of the gate electrode 80 and the drain electrode wiring 81 are not particularly limited to the above, and may be constituted by the materials and the manufacturing methods exemplified in the gate electrode 50.

The gate electrode 80 and the drain electrode wiring 81 may also be individually shaped to make. In this case, the drain electrode 80 and the drain electrode wiring 81 may be made of the above materials, and the materials constituting the drain electrode 80 and the drain electrode wiring 81 may be the same or different from each other. Further, both of the drain electrode 80 and the drain electrode wiring 81 can be formed by the above-described manufacturing method, and the method of manufacturing the drain electrode 80 and the manufacturing of the drain electrode wiring 81 can be employed. The methods can be the same or different from each other.

Moreover, the thin film transistor 10 shown in Fig. 1 has a so-called lower The structure of the electrode/staggered type is not particularly limited to the structure of the thin film transistor in the case of the lower electrode type. Specifically, the thin film transistor may have a lower electrode/staggered structure as shown in FIG. 4. In this case, as shown in the figure, first, the source electrode 70 and the drain electrode 80 are formed on the formation surface 41 of the gate insulating film 40, and secondly, the source electrode 70 and the gate electrode 80 are covered, and the above-described formation is performed. A semiconductor layer 60 is formed on the face 41.

The thin film transistor 10 described above is incorporated in the moment shown in FIG. The array circuit 100 is used. Figure 5 is a plan view showing a matrix circuit in an embodiment of the present invention. Moreover, such a matrix circuit 100 can be utilized for a liquid crystal display or a pressure sensor.

The matrix circuit 100 includes m×n (m, n are natural numbers) The thin film transistor 10, m × n thin film transistors 10 are arranged in a matrix of m rows and n columns along the Y direction and the X direction on one insulating substrate 20. Further, the Y direction in the present embodiment corresponds to an example of the first direction of the present invention, and the X direction in the present embodiment corresponds to an example of the second direction of the present invention.

In the present embodiment, the insulating resin portion 50 is individually disposed at m × n In the thin film transistor 10, the insulating resin portions 50 between the adjacent thin film transistors 10 are cut off from each other. Therefore, the insulating substrate 20 which is caused by the hardening shrinkage of the resin material is suppressed from being bent.

Moreover, the matrix circuit 100, as shown in the figure, includes n pieces 1 scan wiring 110, n second scanning wirings 120 and m third scanning wirings 130. The first scan wiring 110 or the second scan wiring 120 in this embodiment The third scanning wiring 130 in the present embodiment corresponds to an example of the second wiring of the present invention, which corresponds to an example of the first wiring of the present invention.

Each of the first scan lines 110 extends in the Y direction, and the thin film is electrocrystal The source electrode wiring 71 of the body 10 is connected to this first scanning wiring 110. The n first scanning lines 110 are substantially equally spaced in the X direction, and the source electrodes 70 of the m thin film transistors 10 arranged along the Y direction are connected to each other via one first scanning wiring 110. .

Similarly, each of the second scan lines 120 extends in the Y direction. The drain electrode wiring 81 of the thin film transistor 10 is connected to the second scan wiring 120. The n second scanning wires 120 are substantially equally spaced in the X direction, and the gate electrodes 70 of the m thin film transistors 10 arranged along the Y direction are connected to each other via one second scanning wiring 120. .

On the other hand, each of the third scan lines 130 extends in the X direction. The gate electrode wiring 31 of the thin film transistor 10 is connected to this third scanning wiring 130. The m pieces of the third scanning lines 130 are substantially equally spaced in the Y direction, and the gate electrodes 30 of the n thin film transistors 10 arranged along the X direction are connected to each other via one of the third scanning lines 130.

Further, in the present embodiment, the third insulating resin portion 53 is provided in the first 1 The intersection (repeated portion) of the scan wiring 110 and the third scan wiring 130. The third insulating resin portion 53 is interposed between the first scanning wiring 110 and the third scanning wiring 130.

The third insulating resin portion 53 is in contact with the thin film transistor 10 described above. The first and second insulating resin portions 51 and 52 are made of the same material, and are formed substantially simultaneously in the same steps as the first and second insulating resin portions 51 and 52.

Such an intersection is the same as the above-mentioned thin film transistor, and the third The end portion of the scanning line is likely to be thin, and the first scanning line and the third scanning line are short-circuited, and a large parasitic capacitance may be generated between the first scanning line and the third scanning line.

On the other hand, in the present embodiment, the third insulating resin portion 53 is used. Between the first scanning line 110 and the third scanning line short-circuit 130, the short-circuit defect between the first scanning line 110 and the third scanning line 130 is suppressed, and the first scanning line 110 and the third scanning line 130 can be reduced. Parasitic capacitance between.

Similarly, the second scan wiring 120 and the third scan wiring 130 The fourth insulating resin portion 54 is provided at the intersection (repeating portion), and the fourth insulating resin portion 54 is interposed between the second scanning wiring 120 and the third scanning wiring 130.

The fourth insulating resin portion 54 is also in contact with the above-described thin film transistor 10. The first and second insulating resin portions 51 and 52 are made of the same material, and are formed substantially simultaneously in the same steps as the first and second insulating resin portions 51 and 52.

In the present embodiment, according to such a fourth insulating resin portion 54, The short-circuit defect between the second scan line 120 and the third scan line 130 is reduced, and the parasitic capacitance between the second scan line 120 and the third scan line 130 can be reduced.

Moreover, the embodiments described above are for easy understanding of the present invention. The description is not intended to limit the invention. Therefore, the above embodiments disclose that each element includes all the design changes and the equivalents of the technical scope of the present invention.

10‧‧‧film transistor

20‧‧‧Insulating substrate

30‧‧‧gate electrode

40‧‧‧gate insulating film

41‧‧‧Formation

42‧‧‧Sloping surface

43‧‧‧flat surface

50‧‧‧Insert Resin Department

51‧‧‧1st Insulating Resin Department

511‧‧‧1st inclined surface

512‧‧‧2nd inclined surface

513‧‧‧ top

52‧‧‧2nd Insulating Resin Department

521, 522‧‧‧ sloped surface

523‧‧‧ top

60‧‧‧Semiconductor layer

61‧‧‧ top

70‧‧‧Source electrode

71‧‧‧Source electrode wiring

80‧‧‧汲electrode

81‧‧‧汲 electrode wiring

h ₁ ‧‧‧height

h ₂ ‧‧‧height

‧‧‧‧ tilt angle

‧‧‧‧ tilt angle

Γ‧‧‧ tilt angle

Claims (11)

A thin film transistor is a lower gate type thin film transistor including a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, and a drain electrode, and includes: an electrode wiring, respectively, from the source electrode and the above a drain electrode extending; and an insulating resin portion disposed between the electrode wiring and the gate insulating film; wherein the insulating resin portion is provided at least at an outer edge portion of the gate electrode A repeating portion with the above electrode wiring. The thin film transistor according to the first aspect of the invention, wherein the insulating resin portion protrudes convexly from a surface on which the gate insulating film is formed, and the forming surface is a surface on which at least the semiconductor layer is formed. The thin film transistor according to claim 2, wherein the topmost portion of the insulating resin portion is relatively high with respect to the topmost portion of the semiconductor layer. The thin film transistor according to the second aspect of the invention, wherein the insulating resin portion has a first inclined surface that becomes higher as the semiconductor layer is separated from the semiconductor layer, and a second inclined surface that is located above the first inclined surface. The outer side becomes lower as leaving the above semiconductor layer. The thin film transistor according to the fourth aspect of the invention, wherein the inclination angle of the second inclined surface is inclined with respect to the inclination angle of the first inclined surface, bigger. The thin film transistor according to claim 4, wherein the gate insulating film has an inclined surface located outside the forming surface; and an inclination angle of the second inclined surface with respect to the gate insulating film The inclination angle of the inclined surface is relatively large. The thin film transistor according to claim 4, wherein the gate insulating film has an inclined surface located outside the forming surface and a flat surface located further outside the inclined surface; and an end of the second inclined surface The portion is located on the flat surface of the gate insulating film. The thin film transistor according to the first aspect of the invention, wherein the electrode wiring includes: a source electrode line extending from the source electrode; and a drain electrode line extending from the drain electrode; and the insulating resin portion The first insulating resin portion is provided at a portion overlapping the outer edge portion of the gate electrode and the source electrode wiring, and the second insulating resin portion is provided at an outer edge portion of the gate electrode and the gate electrode Repeated parts of the wiring. The thin film transistor according to the first aspect of the invention, wherein the insulating resin portion has a rectangular frame shape as viewed in plan, and the semiconductor layer is surrounded by the insulating resin portion. A matrix circuit comprising m×n thin film transistors according to any one of claims 1 to 9; Here, m × n of the thin film transistors are arranged in m rows and n columns along the first and second directions; and the insulating resin portions are individually provided in m × n of the thin film transistors. The matrix circuit according to claim 10, wherein the matrix circuit further includes: n first connection wires electrically connected to the source of the m thin film transistors arranged along the first direction The electrode or the above-described drain electrode; and the m second connection wires are electrically connected to the gate electrode of the n thin film transistors arranged along the second direction; and the insulating resin portion is interposed between the first connection The wiring and the second connection wiring are provided between the first connection wiring and the second connection wiring.