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TW201330202A - 半導體堆疊結構及其製法 - Google Patents

半導體堆疊結構及其製法 Download PDF

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TW201330202A
TW201330202A TW102100390A TW102100390A TW201330202A TW 201330202 A TW201330202 A TW 201330202A TW 102100390 A TW102100390 A TW 102100390A TW 102100390 A TW102100390 A TW 102100390A TW 201330202 A TW201330202 A TW 201330202A
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cutting
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TWI473220B (zh
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Po-Shen Lin
Chuan-Jin Shiu
Bing-Siang Chen
Chen-Han Chiang
Chien-Hui Chen
Hsi-Chien Lin
Yen-Shih Ho
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Xintec Inc
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Abstract

一種半導體堆疊結構之製法，係將相堆疊之基板與晶圓進行切單製程，主要藉由在切割處上，先移除部分晶圓材質，以在該晶圓之晶片邊緣形成應力集中處，再進行切割，使應力被迫集中在該晶圓之晶片邊緣，而令該晶片之邊緣翹曲。因此，可避免該應力延伸至該晶片之內部。本發明復提供該半導體堆疊結構。

Description

半導體堆疊結構及其製法
本發明係關於一種半導體晶圓，更詳言之，本發明係為一種半導體堆疊結構及其製法。
當半導體平面封裝相關技術到達極限，可藉由積體化滿足微小化的需求，故有堆疊晶圓技術之發展。目前係朝將多個同質或異質之晶片堆疊發展，以達多功之目的。
如第1A至1B圖所示之習知半導體堆疊結構1之製法，係於一玻璃板10上形成一擋層100，以藉該擋層100堆疊一由複數晶片11’組成之晶圓11，且各該晶片11’之間係為切割線L，亦即，一晶圓11係可切割出複數個晶片11’。
其中，該晶圓11係具有有線路結構110，該線路結構110係包含至少一介電層110a、形成於該介電層110a上之線路(圖略)與電性連接墊110b,110c。
接著，沿該切割線L進行一次直接切割製程，以獲得複數個半導體堆疊結構1。
惟，習知切單製程中，係一次切割完成，使該晶片11’所受之應力會朝晶片11’之中間處延伸集中，因而導致晶 片11’之中間處容易破裂或損壞(如第1C圖所示之標號K)，造成晶片11’的線路或電性連接墊110b,110c受損，更甚者，將使該半導體堆疊結構1報廢。
因此，如何克服習知技術之應力向內延伸之問題，實為一重要課題。
為解決上述習知技術之應力集中問題，本發明遂提出一種半導體堆疊結構及其製法，係於基板上堆疊晶圓，再移除部分晶圓材質，以於該晶圓之切割線上形成切割槽，最後沿該切割槽切割該基板與晶圓，以使該晶片之邊緣形成翹曲部。
由上可知，本發明之半導體堆疊結構及其製法，藉由先移除部分晶圓材質再切割之方式，將應力集中於不具線路之晶片邊緣，使應力不會延伸至晶片之中間處，因而降低線路損壞之風險。故相較於習知技術之一次直接切割的方式，本發明半導體堆疊結構之製法可降低報廢之風險。
1、2‧‧‧半導體堆疊結構
10‧‧‧玻璃板
100,200,200’‧‧‧擋層
11,21‧‧‧晶圓
11’,21’‧‧‧晶片
110,210‧‧‧線路結構
110a,210a‧‧‧介電層
110b,110c,210b,210c‧‧‧電性連接墊
20,20’‧‧‧基板
21a‧‧‧第一表面
21b‧‧‧第二表面
211‧‧‧切割區
211a‧‧‧翹曲部
212‧‧‧穿孔
213‧‧‧絕緣層
214‧‧‧線路層
214a‧‧‧導電結構
215‧‧‧保護層
216‧‧‧焊錫凸塊
22‧‧‧切割槽
23‧‧‧透鏡
P‧‧‧應力集中處
L‧‧‧切割線
K‧‧‧破裂或損壞
第1A至1B圖係為習知半導體堆疊結構之製法之剖面示意圖；第1C圖係為第1B圖之A之放大圖；以及第2A至2G圖係為本發明半導體堆疊結構之製法之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明之半導體堆疊結構2之製法之剖面示意圖。
如第2A及2B圖所示，於一基板20上形成一擋層(dam layer)200，再將一晶圓21結合於該擋層200上。
於本實施例中，該基板20之材質係為玻璃或矽，而該晶圓21係具有微機電系統(Micro Electro Mechanical System,MEMS)或特殊功能積體電路(Application Specific Integrated Circuit,ASIC)，且該擋層200係可供作支撐之用且材質不限，例如氧化(oxide)材。
再者，該晶圓21係由複數晶片21’組成，且具有接置該基板20之第一表面21a與相對該第一表面21a之第二 表面21b，而該晶圓21之第一表面21a上具有線路結構210及切割區211。其中，該線路結構210具有至少一介電層210a、形成於該介電層210a上之線路(圖略)與電性連接墊210b,210c。
又，該晶圓21之線路結構210上可設置透鏡23。另外，該晶圓21中具有複數電子元件(圖未示)，以提供所需功能；因該電子元件之種類繁多，且非本發明之技術特徵，故不加以詳述。
如第2C圖所示，形成穿孔212於該第二表面21b上以令該電性連接墊210b外露於該穿孔212。
如第2D圖所示，於該穿孔212與第二表面21b上形成絕緣層213，再於該絕緣層213上形成線路層214，且於該穿孔212中形成電性連接該線路層214之導電結構214a。
接著，於該線路層214與第二表面21b上形成用於防焊之保護層215，且該保護層215外露該線路層214之部分表面，以結合焊錫凸塊216。
如第2E圖所示，蝕刻移除該晶圓21之部分材質，以形成對應該切割區211之切割槽22，令該切割區211外露於該切割槽22。其中，該切割槽22係位於各該晶片21’之間。
如第2F圖所示，進行切割製程，沿該切割槽22切割該晶圓21、基板20與擋層200，以於該切割區211上形成應力集中處P，而使該切割區211形成翹曲部211a。其中，該翹曲部211a係位於該晶片21’之邊緣。
當該半導體堆疊結構2進行切割製程時，藉由先蝕刻再切割之方式，以於蝕刻時故意外露該切割區211，故當切割時，應力將集中於該切割區211與該線路結構210之交界處而使該切割區211破裂，因而於該晶片21’之邊緣形成翹曲部211a。因此，相較於習知技術之一次直接切割，本發明之製法可避免應力延伸至該晶片21’中間，故可避免該線路結構210之線路與電性連接墊210b,210c受損，因而可避免該半導體堆疊結構2報廢。
再者，因一般晶片21’於邊緣處不設計線路，故該晶片21’之邊緣形成翹曲部211a，並不會造成線路受損，亦可避免該半導體堆疊結構2報廢。
本發明復提供一種半導體堆疊結構2，係包括：一基板20’、以及一具有相對之第一表面21a與第二表面21b之晶片21’。
所述之半導體堆疊結構2可應用於，例如各種微機電系統(Micro Electro Mechanical System,MEMS)，尤其是利用電性或電容變化來測量的影像感測器。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)或壓力感測器(process sensors)等半導體封裝件。
所述之基板20’上具有擋層200’。
所述之晶片21’之第一表面21a係結合於該擋層200’上，且該晶片21’之第一表面21a上具有線路結構 210，而該晶片21’之第一表面21a邊緣具有翹曲部211a。
綜上所述，本發明之半導體堆疊結構及其製法，主要藉由先蝕刻再切割之方式，以於切割製程中，該晶圓所受的應力集中至晶片之邊緣，以防止晶片之佈線處破裂，因而有效避免線路受損。
上述該些實施樣態僅例示性說明本發明之功效，而非用於限制本發明，任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述該些實施態樣進行修飾與改變。此外，在上述該些實施態樣中之元件的數量僅為例示性說明，亦非用於限制本發明。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體堆疊結構
20’‧‧‧基板
200’‧‧‧擋層
21’‧‧‧晶片
210‧‧‧線路結構
21a‧‧‧第一表面
21b‧‧‧第二表面
211a‧‧‧翹曲部

Claims (10)

  1. 一種半導體堆疊結構，係包括：基板；以及晶片，係具有相對之第一表面與第二表面，該晶片之第一表面係堆疊於該基板上，且該晶片之第一表面上具有線路結構，而該晶片之第一表面邊緣具有翹曲部。
  2. 如申請專利範圍第1項所述之半導體堆疊結構，其中，該晶片上之應力係集中於該翹曲部上。
  3. 如申請專利範圍第1項所述之半導體堆疊結構，其中，該基板與晶片之間具有擋層。
  4. 如申請專利範圍第1項所述之半導體堆疊結構，其中，該基板之材質係為玻璃或矽。
  5. 一種半導體堆疊結構之製法，係包括：於基板上堆疊晶圓，該晶圓具有接置該基板之第一表面與相對該第一表面之第二表面，該晶圓之第一表面上具有線路結構及切割區；移除該晶圓之部分材質，以形成對應該切割區之切割槽，令該切割區外露於該切割槽；以及進行切割，沿該切割槽切割該基板與晶圓，以於該切割區上形成應力集中處，而使該切割區形成翹曲部。
  6. 如申請專利範圍第5項所述之半導體堆疊結構之製法，其中，該基板與晶圓之間具有擋層。
  7. 如申請專利範圍第6項所述之半導體堆疊結構之製法，其中，進行切割時，一併切割該擋層。
  8. 如申請專利範圍第5項所述之半導體堆疊結構之製法，其中，該基板之材質係為玻璃或矽。
  9. 如申請專利範圍第5項所述之半導體堆疊結構之製法，其中，該晶圓係由複數晶片所組成。
  10. 如申請專利範圍第9項所述之半導體堆疊結構之製法，其中，該切割槽係位於各該晶片之間，以當進行切割後，該翹曲部位於該晶片之邊緣。
TW102100390A 2012-01-10 2013-01-07 半導體堆疊結構及其製法 TWI473220B (zh)

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