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TW201338167A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201338167A
TW201338167A TW101140936A TW101140936A TW201338167A TW 201338167 A TW201338167 A TW 201338167A TW 101140936 A TW101140936 A TW 101140936A TW 101140936 A TW101140936 A TW 101140936A TW 201338167 A TW201338167 A TW 201338167A
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region
insulating layer
conductivity type
semiconductor device
substrate
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TW101140936A
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TWI491042B (zh
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Po-Yu Chen
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Taiwan Semiconductor Mfg
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Abstract

側向溝槽金氧半電晶體包括一介電隔離溝槽形成於一絕緣層上覆矽基板上方。側向溝槽金氧半電晶體更包括一第一漂移區，形成於一汲極/源極區與一絕緣層之間；及一第二漂移區，形成於介電隔離溝槽與絕緣層之間。介電溝槽及絕緣層係助於使漂移區完全空乏。空乏區可改善側向溝槽金氧半電晶體的崩潰電壓及導通電阻。

Description

半導體裝置及其製造方法
本發明係有關一種半導體裝置及其形成方法，特別是一種具有介電隔離溝槽的側向金氧半電晶體。
由於各式電子元件(例如電晶體、二極體、電阻、電容等)積集度的提高，半導體工業已經歷急速的成長。大抵來說，積集度的提高是由於半導體製程節點的縮小(例如朝著次20奈米的節點縮小)而造成。隨著半導體裝置的尺寸縮小，需要新的技術以維持代與代之間電子組件的性能。舉例來說，對高功率應用來說，電晶體較佳具有低的閘極至汲極電容、低導通電阻及高崩潰電壓。
隨著半導體技術的演化，金氧半場效電晶體(MOSFET)已被普遍用於今日的積體電路中。金氧半場效電晶體為電壓控制的裝置。當在一金氧半場效電晶體的閘極施加一控制電壓且該控制電壓大於金氧半場效電晶體的臨界電壓時，在金氧半場效電晶體的汲極與源極之間將形成一導電通道。如此一來，在金氧半場效電晶體的汲極與源極之間將有一電流流動。另一方面，當控制電壓小於金氧半場效電晶體的臨界電壓，金氧半場效電晶體將被關閉。
金氧半場效電晶體可包括兩個主要的類別。一種類別是n通道金氧半場效電晶體，而另一種類別是p通道金氧半場效電晶體。根據結構上的差異，金氧半場效電晶體可進一步被細分為三種次類別，其分別為平面金氧半場效電 晶體(planar MOSFETs)、側向雙重擴散金氧半場效電晶體(lateral double diffused MOS(LDMOS)FETs)及垂直雙重擴散金氧半場效電晶體(vertical double diffused MOSFETs)。相較於其他金氧半場效電晶體，由於側向雙重擴散金氧半場效電晶體的不對稱結構使汲極與源極之間的通道較短，因此能夠提供較高的每單位面積電流。
為能進一步改善側向雙重擴散金氧半場效電晶體的性能，可在一側向金氧半場效電晶體之中加入一隔離溝槽以增加側向金氧半場效電晶體的崩潰電壓。尤其是使側向金氧半場效電晶體的閘極區、通道區、及漂移區沿著隔離溝槽的側壁形成。如此的側向溝槽金氧半場效電晶體結構會幫助降低側向溝槽金氧半場效電晶體的導通電阻及增加其崩潰電壓。
本發明之實施例係揭示一種半導體裝置，包括：一基板，具有一第一導電型且包括埋設於其中的一絕緣層；一主體區，具有一第二導電型且形成於基板中；一隔離區，形成於基板上；一第一主動區，具有第一導電型且形成於主體區中；一第二主動區，具有第一導電型且形成於基板中，其中第一主動區及第二主動區係形成於隔離區的相反側；一漂移區，包括：一第一漂移區，具有第一導電型及一第一摻雜密度，且形成於第二主動區與絕緣層之間；及一第二漂移區，具有第一導電型及一第二摻雜密度的，且形成於隔離區與絕緣層之間；一第一介電層，形成於基板 上方；及一閘極，形成於第一介電層上方。
本發明之另一實施例係揭示一種半導體裝置，包括：一絕緣層，埋設於一基板中且具有一第一導電型；一漂移區，具有第一導電型且形成於絕緣層上方；一隔離區，形成於漂移區上方；一汲極區，具有第一導電型且形成於漂移區上方；一主體區，具有一第二導電型且形成於基板中；一源極區，具有第一導電型且形成於主體區中，其中源極區及汲極區係形成於隔離區的相反側；及一閘極，形成於鄰近源極的一位置。
本發明之又一實施例係揭示一種半導體裝置的製造方法，包括：提供一基板，具有一第一導電型；將一絕緣層埋設於基板中；在絕緣層上方形成一隔離區；在基板中的絕緣層上方形成一主體區，其具有一第二導電型；植入具有第一導電型的離子以形成一第一漂移區，其中第一漂移區位於絕緣層與隔離區之間；植入具有第一導電型的離子以形成一第二漂移區；植入具有第一導電型的離子以形成一汲極區，其中第二漂移區位於汲極區與絕緣層之間；植入具有第一導電型的離子以在主體區中形成一源極區，其中源極區及汲極區位於隔離區的相反側；及在鄰近源極區的位置形成一閘極結構。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
將在以下詳細討論本揭露實施例的組成及使用。應能理解的是實施例提供許多發明概念已實施在多種特定情況。在此討論的特定實施例僅為說明用且不對本揭露之範疇有限定性。
將配合具有介電隔離溝槽的側向金氧半電晶體作為特定實施例以敘述本揭露。然而本揭露的實施例亦可被應用於各種金氧半電晶體。
第1圖係繪示出根據一實施例之一側向溝槽金氧半電晶體的簡化剖面示意圖。側向溝槽金氧半電晶體(或側向溝槽MOSFET)100包括具有第一導電型的一基板及埋設於基板中的絕緣層101。更特別的是，基板可被分成兩個部份。如第1圖所示，一基板上部102，形成於絕緣層101的上方；及一基板下部103，形成於絕緣層101下方。根據一實施例，絕緣層101係以二氧化矽形成。基板可為一輕摻雜n型基板，其藉由植入n型摻質(例如為磷)而形成，且濃度為約5×1016/立方公分(cm3)至約9×1016/立方公分(cm3)。第1圖所示的基板通常被稱為一絕緣層上覆矽基板。
一第一汲極/源極區112及一第二汲極/源極區114係形成於絕緣層101上方的基板上部102中。隔離區104及106係形成於兩個主動區之間。舉例來說，如第1圖所示，隔離區104係形成於第一汲極/源極區112及第二汲極/源極區114之間。根據一實施例，第一汲極/源極區112作為側向溝槽MOSFET 100的一汲極，且第二汲極/源極區114為側向溝槽MOSFET 100的一源極。
第一汲極/源極區112係形成於基板上部102中。根據 一實施例，第一汲極/源極區112係作為側向溝槽MOSFET 100的汲極。第一汲極/源極區112可以n型摻質形成。可藉由植入一n型摻質(例如為磷)以形成汲極區，且濃度為約1×1019/cm3至約5×1019/cm3。
第二汲極/源極區114係形成於一主體區122中。根據一實施例，第二汲極/源極區114可作為側向溝槽MOSFET 100的一源極。該源極區可藉由植入一n型摻質(例如為磷)而形成，且濃度為約1×1019/cm3至約5×1019/cm3。如第1圖所示，源極區係形成於鄰近隔離區104與汲極相反側(第一汲極/源極區112)的位置。
側向溝槽MOSFET 100更包括具有第二導電型的主體區122，其係形成於絕緣層101上方的基板上部102。如第1圖所示，主體區122係形成於第二汲極/源極區114下方。根據一實施例，當基板為n型，主體區122為一p型主體區。主體區122係藉由植入一p型摻質，例如硼、鎵、鋁、銦、上述任意組合、或其類似物而形成。根據一實施例，可植入一p型材料(例如硼)直到摻雜密度約為1017/cm3至3×1018/cm3。或者，可藉由一擴散製程形成主體區122。側向溝槽MOSFET 100的主體區122亦可被稱為一通道區。
側向溝槽MOSFET 100可包括一閘極142。如第1圖所示，閘極142被一介電層包圍。更特別的是，介電層隔開閘極142及第二汲極/源極區114。根據一實施例，閘極142可電性連接至一控制訊號。當控制訊號大於側向溝槽MOSFET 100的臨界電壓時，側向溝槽MOSFET 100導通。然而，當控制訊號小於側向溝槽MOSFET 100的臨界電壓 時，側向溝槽MOSFET 100則關閉。
側向溝槽MOSFET 100可包括一汲極區，其包括形成於第一汲極/源極區112與絕緣層101之間的一第一漂移區116，及形成於隔離區104與絕緣層101之間的一第二漂移區118。根據一實施例，第一漂移區為摻雜濃度約1017/cm3至約5×1017/cm3的一n型區。第二漂移區118為摻雜濃度為約1016/cm3至約3×1017/cm3的一n型區。
隔離區104的深度及隔離區104與絕緣層101之間的空隙係繪示於第1圖中。更特別的是，隔離區104的深度被定義為H1。隔離區104與絕緣層101之間的空隙被定義為H2。根據一實施例，H1約為1微米。H2為約0.05微米至約0.3微米。
任何所屬技術領域中具有通常知識者將能理解的是，第1圖僅繪示出一理想的輪廓。在後續製程後H1及H2的尺寸將改變。第1圖所示的H1及H2是用來說明各實施例的發明形式。本揭露並不限定於具有特定尺寸的H1及H2。
隔離區(例如隔離區104)係用於改善側向溝槽MOSFET 100的崩潰電壓。更特別的是，如第1圖所示，隔離區104的底表面鄰近於絕緣層101。絕緣層101及隔離區104皆以例如二氧化矽的介電材料形成。兩層二氧化矽層彼此靠近可產生一完全空乏的第二漂移區118。如此完全空乏的漂移區將助於降低在關閉狀態時側向溝槽MOSFET 100表面的電場。類似地，由於第一漂移區116位於兩個二氧化矽區104及106之間，第一漂移區116可為完全空乏。如此一來，完全空乏的第二漂移區116助於 降低側向溝槽MOSFET 100表面的電場。
完全空乏的漂移區(例如第二漂移區118)所產生的影響與表面電場降低(reduced surface field,RESURF)的效應類似。表面電場降低為用來改善高電壓金氧半電晶體的崩潰電壓的習知機制。因此，完全空乏的漂移區有助於改善側向溝槽MOSFET 100的崩潰電壓。再者，由於側向溝槽MOSFET 100的崩潰電壓改善了，可使用一高摻雜漂移區以進一步降低側向溝槽MOSFET 100的導通電阻。總而言之，完全空乏的漂移區118助於改善側向溝槽MOSFET 100的崩潰電壓及導通電阻。
具有介電隔離溝槽(例如隔離區104)之側向溝槽MOSFET的優點之一在於第1圖所示之溝槽結構助於改善側向溝槽MOSFET 100的崩潰電壓及導通電阻。亦即溝槽結構幫助維持側向溝槽MOSFET的崩潰電壓。再者，溝槽結構可降低側向溝槽MOSFET 100的導通電阻，使側向溝槽MOSFET 100的功率損失可降低。再者，第1圖所示的側向溝槽結構可有助於降低側向溝槽MOSFET 100的間距(pitch)。降低的間距可有助於降低通道長度及側向溝槽MOSFET 100的導通電阻。
第2-15圖係繪示出根據一實施例之製造一側向溝槽金氧半電晶體的中間步驟的剖面示意圖。第2圖係繪示出根據一實施例之在基板上形成一介電層後一半導體裝置的剖面示意圖。如第2圖所示，一介電層132係形成於一絕緣層101上方的一基板上部102之頂部。如上述配合第1圖的說明，基板可為一n型絕緣層上覆矽基板。
介電層132可以常用於積體電路製程中的各種介電材料形成。舉例來說，介電層132可由二氧化矽、氮化矽或一摻雜玻璃層(例如硼矽玻璃及其類似物)形成。或者，介電層可為一由氮化矽層、氮氧化矽層、聚醯胺(polyamide)層、一低介電常數絕緣體或其類似物形成。再者，也可使用上述介電材料之組合以形成介電層132。根據一實施例，介電層132係可藉由合適技術，例如濺鍍、氧化及/或化學氣相沉積而形成。
第3圖係繪示出根據一實施例之在對第2圖所示半導體裝置實施一蝕刻製程後的半導體裝置剖面示意圖。根據一實施例，使用沉積及微影技術在介電層132上形成一圖案化罩幕(未繪示)，例如一光阻罩幕及/或一硬式罩幕。此後，實施一蝕刻製程，例如一反應離子蝕刻或其他乾式蝕刻、一非等向性濕式蝕刻或任何其他合適的非等向性蝕刻或圖案化製程，以形成溝槽302及304。
第4圖係繪示出根據一實施例之在第3圖所示半導體裝置的溝槽302及溝槽304中形成一薄介電層後的剖面示意圖。薄介電層402及404可為由熱生長法分別形成於溝槽302及溝槽304的一氧化層。另外，薄介電層402及404可由其他合適技術而形成，例如濺鍍、氧化及/或化學氣相沉積。
第5A圖係繪示出根據一實施例在對第4圖所示的半導體裝置的溝槽302及304實施一非等向性蝕刻製程後的剖面示意圖。對溝槽302及304實施一非等向性蝕刻製程。可藉由控制蝕刻製程的強度及方向以移除薄介電層402及 404的底部。
第5B圖係繪示出根據一實施例在對第5A圖所示半導體裝置的溝槽302及304實施一額外的蝕刻製程後的剖面示意圖。對溝槽302及304實施一額外的蝕刻製程。如第5B圖所示，藉由控制額外的蝕刻製程的強度及方向，以移除溝槽302及304的介電側壁之底部。
第6圖係繪示出根據一實施例在第5B圖所示半導體裝置的溝槽302及304的底部分別形成底部介電層後的剖面示意圖。底部介電層602及604可為由熱氧化法分別形成於溝槽302及304的一底部介電層。應注意的是，可藉由例如化學氣相沉積的其他合適製程形成底部介電層602及604。
第7圖係繪示出根據一實施例在對第6圖所示半導體裝置的溝槽302及304分別實施一非等向性蝕刻製程後的剖面示意圖。對溝槽302及304實施一非等向性蝕刻製程以移除溝槽302及304側壁上的薄介電層。
第8圖係繪示出根據一實施例在以介電材料填入第7圖所示半導體裝置的溝槽後的剖面示意圖。根據一實施例，隔離區802及804可藉由先形成溝槽再以一介電材料填入溝槽而形成。為了研磨第8圖所示之半導體裝置的表面，可實施一平坦化製程(例如化學機械研磨或回蝕刻製程)以平坦化隔離區802及804的一上表面。
在溝槽(如第7圖所示)內填入一介電材料，藉以形成第8圖所繪示的隔離區域802及804。介電材料可包括例如熱氧化物、化學氣相沉積氧化矽或其類似物。介電材料 亦可包括一些材料之組合，例如氮化矽、氮氧化矽、高介電常數介電材料、低介電常數介電材料、化學氣相沉積多晶矽或其他介電材料。
第9圖係繪示出根據一實施例在對第8圖所示半導體裝置實施一非等向性蝕刻製程後的剖面示意圖。在半導體裝置的上表面上使用沉積及微影技術形成一圖案化罩幕(未顯示)，例如一光阻罩幕及/或硬式罩幕。實施一非等向性蝕刻製程以形成溝槽902及904。
第10圖係繪示出根據一實施例在第9圖所示半導體裝置的溝槽的側壁上形成一薄氧化層後的剖面示意圖。薄氧化層可藉由一熱氧化法形成於溝槽902及904中。上表面上的介電層可防止半導體裝置上表面上產生任何額外的氧化。
第11圖係繪示出根據一實施例在以一閘極電極材料填入第10圖所示半導體裝置的溝槽後的剖面示意圖。閘極電極層1102可以多晶矽形成。或者，閘極電極層1102可以其他常用導電材料形成，例如一金屬(例如Ta、Ti、Mo、W、Pt、Al、Hf、Ru)、一金屬矽化物(例如鈦矽化合物、鈷矽化合物、鎳矽化合物、鉭矽化合物)、一金屬氮化物(例如氮化鈦、鉭化鈦)、摻雜多晶矽、其他導電材料、上述之任意組合或其類似物。
第12圖係繪示出在對第11圖所示半導體裝置的上表面實施一化學物理研磨製程或一回蝕刻製程後的剖面示意圖。可實施一平坦化製程(例如一化學機械研磨或回蝕刻製程)以平坦化閘極電極層1102的上表面。如第12圖所示， 閘極電極層1102的一部份因此被移除。如第12圖所示，在化學機械研磨製程之後可形成兩個閘極，也就是第一閘極1202及一第二閘極1204。
第13圖係繪示出在對第12圖所示半導體裝置的上表面實施一非等向性蝕刻製程後的剖面示意圖。根據一實施例，對上表面實施一非等向性蝕刻製程。如此一來，介電層132(未繪示於第13圖然而繪示於第2圖中)被移除。
第14圖係繪示出在對第13圖所示半導體裝置的基板中形成主體區後的剖面示意圖。主體區122及124可形成於基板上部102中。根據一實施例，當基板上部102為一輕摻雜n型基板時，主體區122及124可藉由植入合適p型摻質(例如B、Ga、In或其類似物)而形成。或者，在基板103為一n型基板的一實施例中，主體區122及124可藉由植入合適n型摻質(例如P、As或其類似物)而形成。根據一實施例，主體區122及124的摻雜密度約從1017/cm3至約3×1018/cm3。
第15圖係繪示出在第14圖所示半導體裝置的基板上方形成汲極/源極區後的剖面示意圖。汲極/源極區112及114可形成於隔離區(例如隔離區802)的相反側。根據一實施例，汲極/源極區(例如汲極/源極區112)可藉由植入例如P、As或其類似物的合適n型摻質而形成。根據一實施例，汲極/源極(例如汲極/源極)的摻雜密度係從1019/cm3至約5×1019/cm3。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者， 在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
再者，本說明書所敘述的製程、機器、產品、物質組成、手段、方法、及步驟之特定實施例並不意圖限定本揭露的範疇。任何所屬技術領域中具有通常知識者已能從本揭露理解的是，可根據本揭露使用與在此敘述之相對應實施例實質執行相同功能或達到實質上相同的結果之現有的或以後發展的製程、機器、產品、物質組成、手段、方法、或步驟。因此，所附申請專利範圍意圖包括上述製程、機器、產品、物質組成、手段、方法、或步驟。
100‧‧‧側向溝槽金氧半電晶體
101‧‧‧絕緣層
102‧‧‧基板上部
103‧‧‧基板下部
104、106‧‧‧隔離區
112‧‧‧第一汲極/源極區
114‧‧‧第二汲極/源極區
116‧‧‧第一漂移區
118‧‧‧第二漂移區
122、124‧‧‧主體區
132‧‧‧介電層
142‧‧‧閘極
302、304、902、904‧‧‧溝槽
402、404‧‧‧薄介電層
602、604‧‧‧底部介電層
802、804‧‧‧隔離區
1102‧‧‧閘極電極層
1202‧‧‧第一閘極
1204‧‧‧第二閘極
H1‧‧‧深度
H2‧‧‧空隙
第1圖係繪示出根據一實施例之一側向溝槽金氧半電晶體的簡化剖面示意圖。
第2圖係繪示出根據一實施例之在基板上形成一介電層後一半導體裝置的剖面示意圖。
第3圖係繪示出根據一實施例之在對第2圖所示半導體裝置實施一蝕刻製程後的半導體裝置剖面示意圖。
第4圖係繪示出根據一實施例之在第3圖所示半導體裝置的溝槽302及溝槽304中形成一薄介電層後的剖面示意圖。
第5A圖係繪示出根據一實施例在對第4圖所示的半導體裝置的溝槽302及304實施一非等向性蝕刻製程後的剖面示意圖。
第5B圖係繪示出根據一實施例在對第5A圖所示半導體裝置的溝槽302及304實施一額外的蝕刻製程後的剖面示意圖。
第6圖係繪示出根據一實施例在第5B圖所示半導體裝置的溝槽302及304的底部分別形成底部介電層後的剖面示意圖。
第7圖係繪示出根據一實施例在對第6圖所示半導體裝置的溝槽302及304分別實施一非等向性蝕刻製程後的剖面示意圖。
第8圖係繪示出根據一實施例在以介電材料填入第7圖所示半導體裝置的溝槽後的剖面示意圖。
第9圖係繪示出根據一實施例在對第8圖所示半導體裝置實施一非等向性蝕刻製程後的剖面示意圖。
第10圖係繪示出根據一實施例在第9圖所示半導體裝置的溝槽的側壁上形成一薄氧化層後的剖面示意圖。
第11圖係繪示出根據一實施例在以一閘極電極材料填入第10圖所示半導體裝置的溝槽後的剖面示意圖。
第12圖係繪示出在對第11圖所示半導體裝置的上表面實施一化學物理研磨製程或一回蝕刻製程後的剖面示意圖。
第13圖係繪示出在對第12圖所示半導體裝置的上表面實施一非等向性蝕刻製程後的剖面示意圖。
第14圖係繪示出在對第13圖所示半導體裝置的基板中形成主體區後的剖面示意圖。
第15圖係繪示出在第14圖所示半導體裝置的基板上 方形成汲極/源極區後的剖面示意圖。
100‧‧‧側向溝槽金氧半電晶體
101‧‧‧絕緣層
102‧‧‧基板上部
103‧‧‧基板下部
104、106‧‧‧隔離區
112‧‧‧第一汲極/源極區
114‧‧‧第二汲極/源極區
116‧‧‧第一漂移區
118‧‧‧第二漂移區
122‧‧‧主體區
142‧‧‧閘極
H1‧‧‧深度
H2‧‧‧空隙

Claims (10)

  1. 一種半導體裝置，包括：一基板，具有一第一導電型且包括埋設於其中的一絕緣層；一主體區，具有一第二導電型且形成於該基板中；一隔離區，形成於該基板上；一第一主動區，具有該第一導電型且形成於該主體區中；一第二主動區，具有該第一導電型且形成於該基板中，其中該第一主動區及該第二主動區係形成於該隔離區的相反側；一漂移區，包括：一第一漂移區，具有該第一導電型及一第一摻雜密度，且形成於該第二主動區與該絕緣層之間；一第二漂移區，具有該第一導電型及一第二摻雜密度的，且形成於該隔離區與該絕緣層之間；一第一介電層，形成於該基板上方；以及一閘極，形成於該第一介電層上方。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一介電層係形成於該閘極與該第一主動區之間。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該隔離區與該絕緣層之間的一距離為0.05微米至0.3微米。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該主體區具有一為1017/cm3至3×1018/cm3的摻雜密度。
  5. 如申請專利範圍第1項所述之半導體裝置，其中： 該第一主動區及該第二主動區具有一為1019/cm3至5×1019/cm3的摻雜密度且；該第一漂移區的該第一摻雜密度為1017/cm3至約5×1017/cm3；以及該第二漂移區的該第二摻雜密度為1017/cm3至約5×1017/cm3。
  6. 一種半導體裝置，包括：一絕緣層，埋設於一基板中且具有一第一導電型；一漂移區，具有該第一導電型且形成於該絕緣層上方；一隔離區，形成於該漂移區上方；一汲極區，具有該第一導電型且形成於該漂移區上方；一主體區，具有一第二導電型且形成於該基板中；一源極區，具有該第一導電型且形成於該主體區中，其中該源極區及該汲極區係形成於該隔離區的相反側；以及一閘極，形成於鄰近該源極的一位置。
  7. 如申請專利範圍第6項所述之半導體裝置，其中該漂移區包括：一第一漂移區，形成於該汲極區與該絕緣層之間；以及一第二漂移區，形成於該隔離區與該絕緣層之間。
  8. 如申請專利範圍第6項所述之半導體裝置，更包括：一第一介電層，形成於該閘極與該源極區之間；以及一第二介電層，形成於該閘極與該基板之間。
  9. 一種半導體裝置的製造方法，包括： 提供一基板，具有一第一導電型；將一絕緣層埋設於該基板中；在該絕緣層上方形成一隔離區；在該基板中的該絕緣層上方形成一主體區，其具有一第二導電型；植入具有該第一導電型的離子以形成一第一漂移區，其中該第一漂移區位於該絕緣層與該隔離區之間；植入具有該第一導電型的離子以形成一第二漂移區；植入具有該第一導電型的離子以形成一汲極區，其中該第二漂移區位於該汲極區與該絕緣層之間；植入具有該第一導電型的離子以在該主體區中形成一源極區，其中該源極區及該汲極區位於該隔離區的相反側；以及在鄰近該源極區的位置形成一閘極結構。
  10. 如申請專利範圍第9項所述之半導體裝置的製造方法，更包括：在該基板中形成一二氧化矽絕緣層；在該二氧化矽絕緣層上方形成一二氧化矽隔離區；以及在該二氧化矽絕緣層與該二氧化矽隔離區之間形成一漂移區，其中該漂移區的一厚度從0.05微米到0.3微米。
TW101140936A 2012-03-09 2012-11-05 半導體裝置及其製造方法 TWI491042B (zh)

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