TW201133729A - Semiconductor chip assembly with post/base heat spreader and conductive trace - Google Patents

Abstract

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The heat spreader includes a post and a base. The post extends upwardly from the base into an opening in the adhesive, and the base extends laterally from the post. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace provides signal routing between a pad and a terminal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer package, and more particularly to a semiconductor wafer package comprising a semiconductor component, a wire, an adhesive layer, and a heat sink. Production method. [Prior Art] Semiconductor components such as packaged and unpackaged semiconductor wafers can provide applications with voltage, high frequency, and high performance; these applications require a very high power for performing special functions. The higher the semiconductor component, the more heat it generates. In addition, after the package density is increased and the size is reduced, the surface area available for heat dissipation is reduced, resulting in an increase in heat generation. Semiconductor components are prone to performance degradation and shortened service life at high temperatures, and may even fail immediately. High heat not only affects wafer performance, but may also cause thermal stress on the wafer and its surrounding components due to thermal expansion mismatch. Therefore, the wafer must be dissipated quickly and efficiently to ensure the efficiency and reliability of its operation. A high thermal conductivity path typically conducts and dissipates thermal energy to a larger area than the die pad where the wafer or wafer is located. Light-emitting diodes (LEDs) have recently become the alternative source of incandescent light sources, fluorescent light sources, and light sources. LEDs can provide energy efficiency and low cost LEDs for medical, military, signage, signal, aviation, marine, handle, portable devices, commercial and residential lighting applications. LEDs can be used for lamps, flashlights, headlights, and long time. illumination. For example, searchlights, traffic lights, and display devices provide a light source. The high-power chip of the LED towel also generates a large amount of heat energy while providing high-intensity output. However, under high temperature operation, LEDs may suffer from color shift, brightness reduction, shortened life, and immediate failure. In addition, the LED is scattered

There are limits in terms of heat' which in turn affects its light output and reliability. Therefore, LEDs highlight the market's need for high-power chips with good heat dissipation. 〇 led packages typically contain an LED chip, a pedestal, electrical contacts, and a hot junction. The pedestal is thermally coupled to the LED wafer and used to support the LED wafer. The electrical contacts are electrically connected to the anode and cathode of the LED chip. The thermal contacts are thermally bonded to the LED wafer via the pedestal, and the underlying carrier is sufficiently thermally dissipated to prevent overheating of the LED wafer. The industry is actively investing in high-power chip packages and thermal boards in a variety of design and manufacturing technologies to meet performance needs in this extremely cost-competitive environment. A plastic ball grid array (P B G A) package encloses a wafer and a laminate substrate in a plastic case and then adheres to a printed circuit board (PCB) with solder balls. The laminate substrate comprises a dielectric layer typically composed of glass fibers. The heat generated by the wafer can be transferred to the solder ball via the plastic and dielectric layers and then to the printed circuit board. However, due to the low thermal conductivity of the plastic and dielectric layers, the heat dissipation effect of PBGA is not good. A quad flat no-lead (qFN) package places the wafer on a copper die pad that is soldered to the printed circuit board. The thermal energy generated by the wafer can be transferred to the printed circuit board via the die. However, due to the limited routing capability of its leadframe interposer, QFN packages are not suitable for high input/output (1/〇) wafers or passive components. 5 201133729 Thermal pads provide electrical routing, thermal management and mechanical support for semiconductor components. The heat conducting plate usually comprises a substrate for signal routing, a heat sink or heat sink for providing heat removal, a solder pad electrically connectable to the semiconductor component, and a terminal electrically connectable to the next layer. The substrate can be a laminate having a single or multi-layer routing circuitry and/or a multilayer dielectric layer. The heat sink can be a metal base, a metal block or a buried metal layer. The heat conducting plate engages the next layer of the body. For example, the next layer of the body can be a lamp holder with a printed circuit board and a heat sink. In this example, a led package system is mounted on the heat conducting plate, and the heat conducting plate is mounted on the heat dissipating device, and the heat conducting plate/heat dissipating device sub-group and the printed circuit board are further disposed in the lamp holder. In addition, the heat conducting plate is electrically coupled to the printed circuit board via wires. The substrate directs the electrical signal from the printed circuit board to the LED package, and the heat sink scatters and transfers the thermal energy of the led package to the heat sink. Therefore, the heat shield can provide an important thermal path for the LED wafer. U.S. Patent No. 6,5,7,1,2, issued toJ.S.A. No. 6, the disclosure of which is incorporated herein by reference. A heat dissipating block having a square or rectangular shape similar to the central opening is adhered to the central opening side wall to be bonded to the substrate. The upper and lower conductive layers are respectively adhered to the top and bottom of the substrate, and are electrically connected to each other through the plating vias penetrating the substrate. A wafer is disposed on the heat slug and bonded to the upper conductive layer, the package material is patterned on the wafer, and the lower conductive layer is provided with solder balls. At the time of manufacture, the substrate was originally a Bstage 201133729 resin film placed on the lower conductive layer. The heat dissipating block is inserted in the central opening so as to be located on the lower conductive layer and spaced apart from the substrate by a gap. The upper conductive layer is disposed on the substrate. After the upper and lower conductive layers are heated and pressed against each other, the resin is melted and flows into the gap to be solidified. The upper and lower conductive layers are patterned, thereby forming circuit wiring on the substrate and exposing the resin flash to the heat sink. Then remove the resin flash to expose the heat sink. Finally, the wafer is placed on the heat slug and bonded and packaged. Therefore, the thermal energy generated by the wafer can be transferred to the printed circuit board via the heat slug. However, in mass production, the manual placement of the heat sink in the central opening is labor intensive and costly. Moreover, since the mounting tolerance of the lateral direction is small, the heat dissipating block is not easily positioned in the central opening, which causes a gap between the substrate and the heat radiating block and uneven wiring. As a result, the substrate is only partially adhered to the heat sink block, and sufficient support force is not obtained from the heat sink block and is easily delaminated. In addition, the chemical etching solution for removing part of the conductive layer to expose the resin flash will also remove some of the heat-dissipating block which is not covered by the resin flash, so that the heat-dissipating block is not flat and difficult to combine, and finally the yield of the group is lowered, Insufficient reliability and high cost. US Patent No. 6,528,882 to Ding et al. discloses a high heat dissipation ball grid array package having a substrate comprising a metal core layer and a wafer disposed on a top surface of the metal core layer. The bottom surface of the metal core layer. The blind hole penetrates the insulating layer through the metal core layer, and the hole is filled with a heat-dissipating solder ball. Further, a solder ball corresponding to the heat-dissipating solder ball is disposed on the substrate. The thermal energy generated by the wafer can flow through the metal core to the heat sink balls and then to the printed circuit board. However, the 201133729 edge layer sandwiched between the metal core layer and the printed circuit board limits the heat flow to the printed circuit board. U.S. Patent No. 6,670,219 issued to, the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all A substrate having a central opening is disposed on the ground plate through an adhesive layer having a central opening. A chip is mounted on the heat sink in a recess formed by the central opening of the ground plate, and the substrate is provided with a solder ball. However, since the solder ball is on the substrate, the heat sink cannot contact the printed circuit board, and the heat dissipation effect of the heat sink is limited to heat convection instead of heat conduction, thereby greatly reducing the heat dissipation effect. U.S. Pat. A substrate having a window-shaped opening is disposed on the wide substrate, and an adhesive layer adheres the pillar portion and the wide substrate to the substrate. A wafer system is disposed on the pillar portion and wire bonded to the substrate, a package material is molded on the wafer, and a solder ball is disposed on the substrate. The post extends through the window opening and supports the substrate by a wide substrate, and the solder ball is located between the wide substrate and the periphery of the substrate. The thermal energy generated by the wafer can be transferred to the wide substrate via the post and then to the printed circuit board. . However, since a space for accommodating the solder balls must be left on the wide substrate, the wide substrate extends only below the substrate at a position corresponding to the center window and the innermost tin ball. As a result, the substrate is unbalanced during the manufacturing process, and is easily shaken and bent, which in turn leads to difficulty in mounting the wafer, bonding the wire, and molding the package material. In addition, the wide substrate may be bent by the molding of the encapsulating material, and once the solder ball collapses, the 201133729 may make the package unweldable to the next layer. Therefore, the yield of the package is low, the reliability is insufficient, and the cost is too high.

In the U.S. Patent Application Publication No. 2/7/267,642 to Erchak et al., the X-ray device assembly comprises a substrate, a protrusion and an insulating layer having a through hole. A sealing system with an electrical connection of eight through holes and a transparent upper cover is disposed on the insulating layer. - The LED day and day film is placed on the protruding portion and connected to the substrate by wire bonding. The protruding portion is adjacent to the substrate and extends through the insulating layer and the through hole on the package body, and is inserted into the package body to be disposed on the substrate, and the insulating layer is provided with an electrical contact. A package system is disposed on the electrical contacts and spaced apart from the insulating layer. The thermal energy generated by the wafer can be transferred to the substrate via the projections to the heat sink. However, these electrical contacts are not easily disposed on the insulating layer, and are difficult to electrically connect with the lower-layer assembly, and cannot provide multilayer routing. ^The conventional package and the heat conducting plate have major drawbacks. For example, an electrically insulating material such as an epoxy resin that has low thermal conductivity limits the heat dissipation effect. However, an electrically insulating material having a high conductivity such as a ceramic or a carbonized stone-filled epoxy resin has adhesion. Low cost and high cost of mass production. The electric, or rim material can be delaminated by heat during the manufacturing process or at the beginning of the operation. If the substrate is a single-layer circuit system, the routing energy board is a rigid circuit system, and the excessively thick dielectric layer will reduce the bulk = base. In addition, the technology has insufficient heat sink performance, is too bulky, or is not easily thermally connected to the bottom. One layer group and other issues. The manufacturing process of the prior art is also not suitable for low-cost mass production operations. In view of the current situation and related limitations of the current high-power semiconductor package and heat-conducting plate, the f sector needs __(4) cost-effectiveness, performance guilty, suitable for mass production, multi-function, flexible adjustment of signal routing and A semiconductor wafer package with excellent heat dissipation. [CRITERIA] The cross-references of the relevant applications: The application for this application is (10) September 11th, 9th, and the request for the US special account No. 12/557, 540 is extended (4), and the 12th, 557, (10) The US special account request is part of the continuation of the US patent application No. 12/406'51G filed on March 18, 2nd. The first: The main 2/406,510 US patent application claims 2 years, 7 months, 7 days, 申7〇, 589唬 US provisional patent application, May 7th, 2nd, May 7th US Provisional Patent No. 61/G71,588_Request, No. 61/〇71, filed on April 11, 2008, US Provisional Patent Application No. 72 and Application No. on March 25, 2008 61, the priority of the state's US provisional patent application, the contents of the above cases are incorporated herein by reference. M US Patent No. 12/557'54G, and the other application is filed on February 9, 2009. Priority to U.S. Provisional Patent Application Serial No. 61/15, the disclosure of which is incorporated herein by reference. This application is also a continuation of the U.S. Patent Application No. 7,541, filed on Sep. 2, 2009, and the U.S. Patent Application Serial No. 12/557,541, the UMOWO application filed on March a. Part of the continuation of the US patent φ request. The US Patent No. 12/406, 51G claims that the US Patent Provision No. 61/071,589 of Shen Qing, No. 61/071,589, is filed in the US Patent No. 12/406, 51G. Proposal for US Provisional Patent No. 61/G71, 588, No. 61/071, No. 748, filed on March 11th, US Patent Application No. 61/071, No. 72 Priority of the U.S. Provisional Patent Application, the contents of each of which are incorporated by reference in its entirety in the U.S. Patent Application Serial No. 12/557,541, the entire disclosure of which is incorporated herein by reference. The priority of the U.S. Provisional Patent Application is hereby incorporated by reference. The present invention provides a semiconductor wafer package comprising at least one half of a conductor, a heat sink, a wire and an adhesive layer. The semiconductor component is sexually coupled to the wire and thermally coupled to the heat sink. The heat sink includes at least: a stud and a base. The stud extends upward from the base and into the viscous opening, the pedestal extending laterally from the stud. The adhesive layer extends between the stud and the wire and between the base and the wire. The wire provides signal routing between a pad and a terminal. According to one aspect of the invention, a semiconductor wafer package includes at least one of a conductor member, an adhesive layer, a heat sink and a wire. The adhesive layer has a small opening to ▲. The heat sink includes at least a stud and a base, the post is adjacent to the base and extends upwardly in the upward direction of the base, and the base is in a downward direction opposite to the upward direction Extending from the column side and /CF perpendicular to the lateral direction of the upward and downward directions, extending laterally from the stud. The wire includes at least one pad and one terminal. The semiconductor component is located above the pillar and overlaps the pillar. The semiconductor component is electrically connected to the pad to be electrically connected to the terminal ′ and thermally coupled to the stud to be thermally coupled to the pedestal. 11 3- 201133729 The adhesive layer is disposed on the base, extends above the base, and extends into the gap σ between the stud and the material. The adhesive layer extends laterally from the stud to the terminal or over the terminal and between the pedestal and the pad. The solder pad is disposed on the adhesive layer and extends above the base. The stud extends into the opening, and the pedestal extends over the semiconductor component, the adhesive layer and the pad. The heat sink can include a cover body located above the top of the stud, abutting the top of the stud, while covering the top of the stud from above, and from the top side of the stud in the side directions Extend out. For example, the cover may be rectangular or square, and the top of the stud may be circular. In this case, the cover may be sized and shaped to match the thermal contact surface of the semiconductor component. The size and shape of the top of the stud are not designed according to the thermal contact surface of the semiconductor component. The cover may also contact and cover the adhesive layer a portion adjacent to the co-column and coplanar with the stud. The cover may also be coplanar with the material and/or the terminal above the adhesive layer. In addition, the stud can thermally join the base and the cover. The heat sink may be composed of the pillar and the base, or the pillar, the base and the cover. The heat sink can also be composed of steel, (four) steel / Lu alloy. Regardless of the composition, the heat sink can provide heat dissipation to diffuse the thermal energy of the semiconductor component to the next layer. The semiconductor component can be disposed on the heat sink. For example, the semiconductor device can be disposed on the heat sink and the wire, and is electrically connected to the bump and the solder pad through the solder-first solder, and is electrically connected to the solder through a second solder 12 201133729 To the heat sink. Alternatively, the semiconductor component may be disposed on the heat sink instead of the wire, and overlap the bump and the wire, electrically connected to the pad through a wire, and thermally coupled to the heat sink through a die bonding material. . The semiconductor component can be a packaged or unpackaged semiconductor wafer. For example, the semiconductor component may be an LED sealing body comprising an LED chip, which is disposed on the heat sink and the wire, and is overlapped with the pillar and the pad, and is electrically connected to the solder via a first solder. The pad is thermally coupled to the heat sink via a second solder. Alternatively, the semiconductor device may be a semiconductor wafer disposed on the heat sink instead of the wire, overlapping the pillar and not the wire, electrically connected to the pad via a wire, and through a die bond The material is thermally bonded to the heat sink. The adhesive layer contacts the stud in the notch and contacts the pedestal, the pad and the terminal outside the notch. The adhesive layer may also cover the wire from below and cover and surround the protrusion in the lateral direction while covering the base from a portion of the protrusion outside the protrusion. The adhesive layer may also be coated in the same manner on the sidewall of the stud and the base is located on a top surface of the stud. The adhesive layer can still be coplanar with the top of one of the studs. The adhesive layer may also fill a space between the base and the wire, and the adhesive layer is confined in a space between the heat sink and the wire. The adhesive layer can extend laterally from the stud to the terminal or across the terminal. For example, the adhesive layer and the terminal can extend to the peripheral edge of the assembly. In this example, the adhesive layer extends laterally from the stud to the terminal. Alternatively, the adhesive layer may extend to a peripheral edge of the set, and the terminal is spaced from the peripheral edge of the set by the 13 201133729; in this case the stud extends laterally and over the terminal . The terminal layer may be overlapped with the terminal or overlapped by the material, for example, above the bonding pad and the adhesive layer, in the adhesive layer, and coplanar with the "cover; in this case, the adhesive layer is The terminal is heavy and goes to the group to be in the material (4) (4) of the terminal for horizontal signal routing. - the terminal may extend below the (four) layer and be coplanar with the pedestal by the (four) layer overlap/time; in this case, the adhesive layer is overlapped with the terminal ' and the set is at the 蝉Provide vertical signal routing between the terminal and the terminal. The stud can be integrally formed with the base. For example, the stud and the pedestal may be a single-metal body or comprise a single metal ruthenium in its interface, wherein the single metal body may be copper. The stud can also extend through the opening. The stud can also be coplanar with the adhesive layer above the bottom surface of the solder fillet. The stud may also be a flat-topped conical cylinder having a diameter that decreases upwardly from the base toward its flat top adjacent the cover. The pedestal can cover the semiconductor component, the stud, the cover, the adhesive layer and the wire from below, and simultaneously support the adhesive layer and the wire and extend to the peripheral edge of the set. The wire can be spaced from the stud and the base. The wire may also be a single-layer continuous trace disposed on and in contact with the adhesive layer while overlapping the adhesive layer and extending over the wire. The wire may also include the pad 'the terminal and the A routing line, wherein a conductive path between the pad and the terminal includes the routing line. In either case, the wire can provide signal routing between the 14 201133729 pad and the terminal. , the solder pad can be used as an electrical contact of the semiconductor component, the terminal can be used as an electrical contact of the next layer, and the pad and the terminal can be between the semiconductor 7G component and the next layer assembly Provide signal routing. ▲ The group can be a -stage or second stage single crystal or polycrystalline device. E.g . The squad can be a first-stage package containing a single-wafer or multi-grass wafer. Or the 'group can be - a second-level module comprising a single-LED package or a plurality of LED packages, wherein each of the LED packages can comprise a single wafer or a plurality of led wafers." The present invention provides a fabrication The method of the semiconductor wafer assembly includes: providing a stud and a pedestal; and providing an adhesive layer on the pedestal; the step of inserting the stud into an opening of the adhesive layer; and providing a conductive layer to the adhesive On the layer, the step comprises: aligning the stud with one of the through holes of the conductive layer; causing the adhesive layer to flow upward into the through hole; a gap between the stud and the conductive layer; curing the adhesive layer; providing a wire The wire includes at least one pad, a terminal and a selected portion of the conductive layer; a semiconductor component is disposed on a heat sink, wherein the heat sink comprises at least the pillar and the base; and the semiconductor component is electrically connected to The wire; and thermally bonding the semiconductor component to the heat sink. According to one aspect of the invention, a method of fabricating a semiconductor wafer package includes: (1) providing a stud, a pedestal, an adhesive layer, and a conductive layer, wherein (a) the stud is adjacent to the pedestal Extending in an upward direction above the pedestal, extending into one of the openings of the adhesive layer, and aligning one of the conductive layers with a through hole' (b) the pedestal is extended in a downward direction opposite to the upward direction 15 201133729 extends below the stud and extends laterally from the stud in a direction perpendicular to the upward and downward directions. ((c) the adhesive layer is disposed on the base and extends to the base Above the seat, between the base and the conductive layer, and uncured, in addition, '(d) the conductive layer is disposed on the adhesive layer and extends above the adhesive layer; (2) the adhesive layer Flowing upward into the through hole, a gap between the stud and the conductive layer; curing the adhesive layer; (providing a wire comprising at least one pad, a terminal and a selected portion of the conductive layer; (5) Configuring a semiconductor component to include at least the stud a heat sink of the pedestal, wherein the semiconductor component is overlapped with the stud; (6) electrically connecting the semiconductor component to the pad, thereby electrically connecting the semiconductor component to the terminal; and (7) thermally connecting The semiconductor device is connected to the semiconductor device to the pedestal. The method for fabricating a semiconductor wafer assembly 7 according to another aspect of the present invention comprises: (1) providing a stud and a pedestal 'where the stud is adjacent and Forming the body on the base and extending in an upward direction above the base 'and the base is extending in a downward direction opposite the upward direction from below the 1st post' and perpendicularly from the stud In the upward and downward directions; the surface direction extends laterally; (7) providing an adhesive layer, wherein the opening is extended through the adhesive layer; (3) providing a conductive layer 'where the through hole extends through the electrical layer; (4) providing the adhesive layer on the pedestal, the step comprising: inserting the column into the opening, wherein the adhesive layer extends over the pedestal and the post extends into the opening; (5) the conductive layer is disposed At the point of the layer, 2 steps will be included The protruding post is aligned with the through hole, wherein the conductive layer is: above the stretched adhesive layer, the adhesive layer is between the base and the conductive layer and is not solidified; (6) heating and melting Adhesive layer; (7) causing the pedestal and the conductive layer to abut each other', thereby moving the stud upward in the through hole, and applying pressure to the molten adhesive layer between the pedestal and the conductive layer, the pressure Forcing the molten adhesive layer to flow upward into the through hole and a gap between the protruding post and the conductive layer; (8) heating and curing the molten adhesive layer, thereby mechanically adhering the protruding post and the base to the conductive layer (9) providing a wire comprising at least one pad, a terminal and a routing line, wherein the pad, the terminal and the routing line comprise a selected portion of the conductive layer, and a pad is located between the pad and the pad The conductive path between the terminals includes the routing line, and a semiconductor component is disposed on a heat sink, the heat sink includes at least the pillar and the base, wherein the semiconductor component is overlapped with the pillar; Electrically connecting the semiconductor component to the pad, Electrically connecting the semiconductor element i, and the end (12) thermally coupled to the semiconductor Wu the boss member, whereby the semiconductor element is thermally coupled to the base. Providing the stud and the base may include: providing a metal plate; forming a patterned patterned resist layer on the metal plate to selectively expose the metal plate to engrave the metal plate to form the pattern Etching a pattern defined by the resist layer, thereby forming a recess on the metal plate that extends into but not through the metal plate; and then removes the patterned etch stop layer, wherein the stud includes the metal plate - an unexamined portion - the unexamined portion protrudes above the pedestal and is laterally surrounded by the recess, the pedestal also including an unetched portion of the metal plate, the unetched portion being located The stud is below the groove. Providing the adhesive layer may include: providing an uncured epoxy resin, and flowing the adhesive layer may include: refining and curing the uncured epoxy resin; and pressing 17 S-201133729 to press the susceptor between the pedestal and the conductive layer Curing epoxy resin. Curing the adhesive layer can comprise: curing the molten uncured epoxy resin. Providing the heat sink may include: providing a cover on the stud after curing the adhesive layer and before disposing the semiconductor component, the cover being located above the top of one of the studs, adjacent to the top of the stud, and simultaneously The top of the stud is covered from above and extends laterally from the top of the stud in the lateral directions. Providing the pad, the terminal and the routing line can include removing a selected portion of the conductive layer after curing the adhesive layer. Providing the solder pad, the terminal and the routing line may further include: after curing the adhesive layer, grinding the pillar, the adhesive layer and the conductive layer, so that the pillar, the S-adhesive layer and the conductive layer are A top side surface facing the upward direction is laterally flush with each other; and then a selected portion of the conductive layer is removed such that the pad, the terminal and the routing line comprise selected portions of the conductive layer. The grinding may include: grinding the adhesive layer without grinding the stud; and then grinding the stud, the adhesive layer, and the conductive layer. The removing may include: performing a wet chemical scavenging of the conductive layer with a patterned etch stop layer defining the pad, the terminal, and the routing line. Providing the solder pad, the terminal and the routing line may further include: depositing a conductive metal on the bump, the adhesive layer and the conductive layer to form a second conductive layer after the polishing is completed; and then removing the conductive layer The selected portion is such that the pad, the terminal and the routing line comprise selected portions of the conductive layers. Depositing the conductive metal to form the second conductive layer may include: disposing a first coating layer on the stud, the adhesive layer and the conductive layer 1833733729 in an electroless plating manner, and then coating a second frost layer The layer is provided on the first coating layer by electroplating. The removing may include a shattering layer of the shovel. The conductive layer is wet chemically etched using the pad, the terminal, and the patterned etch stop layer of the line. The cover is provided to include a soil a - a crucible 3. The selected portion of the second electrically conductive layer is removed. Providing the cover body may further include: first + 兀 刖 刖 刖 研磨, then using the patterned etching etch layer of the cover to remove the selected portion of the first conductive layer, so that the cover includes the first The second part of the two conductive layers. In this way, the terminal, the 4 routing wires and the cover body can be transparently ground and simultaneously formed by the same patterned etching resist layer in the same wet chemical yak dry etching step. The adhesive layer is allowed to flow 0# 匕3. The gap is filled with the adhesive layer. Flowing the adhesive layer may also include: pressing the adhesive layer through the notch to reach the stud and the conductive layer, and a portion of the top surface of the stud adjacent to the top surface of the conductive layer . The cured layer can be mechanically bonded to the conductive layer. qn t t 匕3. The providing the conductive layer may include: separately arranging the conductive layer on the adhesive layer, or 'adhering the conductive layer to a carrier, and then placing the conductive layer and the carrier on the adhesive layer, so that The carrier is overlaid on the conductive layer, and the conductive layer contacts the adhesive layer and is interposed between the adhesive layer and the carrier. Then, after the adhesive layer is cured, the carrier is removed first and then the wire is provided. Providing the semiconductor device may include disposing the semiconductor device on the cover. The disposing the semiconductor device may further include: placing the semiconductor device 19 201133729 over the stud, the cover and the opening, and overlapping the semiconductor element with the stud, the cover and the opening. The disposing the semiconductor device may include: providing a -th solder and a second solder, wherein the first solder is located between a led package including an LED chip and the solder pad, and the second solder is located in the LED package and the Between the covers. Electrically connecting the semiconductor component can include: providing the H-th thermal connection between the LED package and the solder fillet. The semiconductor component can include: providing the second solder between the LED package and the cover. Providing the semiconductor device can include providing a -solid crystal material between a semiconductor wafer and the cover. Electrically bonding the semiconductor component can include providing a wire between the wafer and the pad. Thermally bonding the semiconductor component can include providing the die bond material between the wafer and the cover. The adhesive layer may contact the protruding post, the base, the cover body, the soldering ring, the terminal and the routing line 'covering the wire from below, covering the surrounding side and surrounding the protruding column' from above The pedestal is located at a portion of the outer portion of the stud and extends to a peripheral edge formed by the separation of the other components of the same batch after the assembly is completed. After the assembly is manufactured and separated from other groups of the same batch, the pedestal can cover the semiconductor element, the stud, the cover, the adhesive layer and the wire from below, while supporting the adhesive layer and The wire extends to the peripheral edge of the set. The invention has several advantages. The heat sink provides excellent heat dissipation and allows thermal energy to flow through the adhesive layer. Therefore, the adhesive layer can be a low-cost dielectric with low heat conductivity and is not easily removed. The stud is integrally formed with the base 20 201133729 for improved reliability. The cover body can be tailored to the semiconductor component to enhance the effect of thermal bonding. The adhesive layer can be interposed between the base and the wire to provide a strong mechanical bond between the heat sink and the wire. The wire can have a simple circuit pattern and provide a horizontal single-layer de-routed pedestal at a low cost to provide a mechanical support for the wire to prevent bending deformation. This group can be manufactured by a low temperature process, which not only reduces stress but also improves reliability. The assembly can also be fabricated using high control procedures that can be easily implemented by circuit boards, lead frames, and tape and roll substrate manufacturers. The above and other features and advantages of the present invention will be further described hereinafter by way of various embodiments. [Embodiment] Figs. 1A to 1D are cross-sectional views showing a method of fabricating a stud and a pedestal, and a plan view and a bottom view. Continuing to show an embodiment of the present invention, the first and second figures are the mth, and the first and second views are a cross-sectional view of the metal plate 10, and the metal plate ι includes the opposite major surfaces 12 and 14. The illustrated metal plate 1 is a copper plate having a thickness of 5 μm and has the advantages of thermal conductivity, good bonding, and low cost. The metal sheet 10 can be made of a variety of metals such as steel, stellite, ferrous alloy, iron, nickel, silver, gold, mixtures thereof, and alloys thereof. Fig. 1B is a plan view showing that a patterned etch stop layer 16 and a etch stop layer 8 are formed on the metal plate. The illustrated pattern resistive layer 16 and the fully-covered surname resist layer 18 are deposited on the metal photoresist layer'. The fabrication method is to use the hot-rolling roller to simultaneously dust the photoresist layer on the surface 12 & 14. Wet spin coating and curtain coating 21 gas. 201133729 = also = the use of photoresist formation technology. A reticle (not shown) is placed in the light according to the conventional technique, so that the light selectively passes through the reticle, so that the affected portion becomes insoluble, and then the unreceiving portion is removed by the developer: the dissolved photoresist portion The photoresist layer is patterned, that is, the patterned resist layer 16 is formed. Thus, the photoresist layer (i.e., the patterned resist layer 16) has a pattern of selectively exposed surface 12, while the photoresist layer (i.e., the fully covered resist layer 18) is unpatterned and covers the surface 14. Fig. 1C is a cross-sectional view showing that the metal plate 1 is formed with a recess 20 into which the metal plate 10 is dug. The recess 20 is formed in a manner that the metal plate 10 is formed such that the metal plate 10 forms a pattern defined by the patterned etched layer 16. The name of the surname is engraved on the front side of the wet chemical money engraving. For example, 'the structure is reversed so that the patterned etch stop layer 16 faces downward and the full-scale etched layer 18 faces upward, and then the bottom nozzle of the α-layer 16 facing upwards and facing the pattern (Fig. The chemical etching solution is sprayed onto the metal plate 10 and the patterned etch stop layer 16. At the same time, a top nozzle (not shown) facing the fully-covered surname resist layer 18 is not activated, so By gravity, the by-products of the money can be removed. Alternatively, the backing protection may be provided by a fully-covered surname resist layer 18, or the structure may be immersed in a chemical engraving to form the recess 20. The chemical etchant is highly targeted to copper and can be engraved into the metal plate 10 up to 200 microns. Therefore, the groove 2〇 extends from the surface ^ but does not penetrate the metal plate 1〇, is 3 μm from the surface 14 and has a depth of 200 μm. The chemical etchant also causes lateral etch in the metal plate 10 below the patterned etch stop layer. A suitable chemical etching solution may be a solution containing an alkali ammonia or a diluted mixture of nitric acid and hydrochloric acid. In other words, the etchant can be acidic or basic. . Sufficient to form the groove 2 过度 excessive exposure to the ideal etching time of the chemical surname 20 without causing the metal plate to be determined by trial and error

The figure in which the photoresist layers have been removed by solvent treatment and removed in a plan view and a top view. For example, the solvent used may be a strong alkaline potassium hydroxide solution having a pH of 14. The etched metal plate ίο thus includes a stud 22 and a pedestal 24. The studs 22 are portions of the metal plate 1 that are protected by the patterned etch stop layer 16 and are not etched. The studs 22 are adjacent to the base 24 and are integrally formed with the base 24 and project above the base 24 and are laterally surrounded by the recesses 2''. The stud 22 is 200 microns high (equal to the depth of the groove 2〇), the top surface (the circular portion of the surface 12 (Fig. 1A) has a diameter of 1 μm, and the bottom (the circle adjacent to the pedestal 24) The shape of the shape is 11 μm. Thus the stud 22 is in the form of a flat-topped conical cylinder (like a frustum) with a tapered diameter of the side wall that tapers from the base 24 toward its flat circular top. The tapered sidewalls are formed by lateral etching of the chemical etchant into the patterned etch stop layer 16. The top surface is concentric with the circumference of the bottom (as shown in Figure 1E). The susceptor 24 is an unetched portion of the metal plate 1 below the stud 22, and extends laterally from the stud 22 to a plane (such as the left and right side directions) to a thickness of 300 microns (ie, 500- 200). The posts 22 and pedestal 24 can be treated to enhance bonding to epoxy and solder. For example, the studs 22 and the susceptor 24 may be chemically oxidized or microetched to create a rougher surface. 23 201133729 The stud 22 and the pedestal 24 are a single metal (copper) body formed by a reduction method in the drawings. Alternatively, the contact metal stamping metal plate 1Q may be formed by a contact having a groove or a hole to define the portion of the stud 22, so that the stud 22 and the pedestal Μ are formed into a single metal body by press forming. Alternatively, the studs 22 may be formed by an additive method by depositing the studs 22 on the susceptor 24 by techniques such as electroplating, chemical vapor deposition (cvd), and physical vapor deposition (PVD). For example, the solder bumps 22 can be electroformed on the copper pedestal 24; in this case, the posts 22 and the pedestal 24 are joined by a metallurgical interface, adjacent to each other but not formed. Alternatively, the studs 22 may be formed by a semi-addition method, for example, the upper portion of the studs 22 may be deposited above the lower portion of the studs 22. In addition, the stud 22 and the base 24 can also be formed by a semi-additive method. For example, the upper portion of the stud 22 and the pedestal 24 can be deposited above the etched portion of the stud 22 and the base. The studs 22 can also be sintered to the pedestal 24. 2A and 2B are cross-sectional views showing a method of making an adhesive layer in an embodiment of the present invention.帛2 (: and 2D are respectively a top view and a bottom view drawn according to Fig. 2b. Fig. 2A is a cross-sectional view of the adhesive layer 26, wherein the adhesive layer % is a B-stage uncured epoxy film. It is an uncured and unpatterned sheet having a thickness of 125 microns. The adhesive layer 26 can be a variety of dielectric films or films made of various organic or inorganic electrical insulators. For example, the adhesive layer 26 can initially be a film. The resin-type thermosetting epoxy resin is partially cured to a medium stage after being immersed in a reinforcing material. The epoxy resin may be FR-4, but may also be used, for example, a polyfunctional and bismaleimide triazine. (BT) Resin and other epoxy resins. In the specific application of 24 201133729, cyanate esters, polyfluorenes, succinimide, and polytetraethylene (pTFE) are also known as clothing oxygen. The material can be electronic grade glass, also: strong material, such as the strength of the broken glass, low-inducing rate glass, Shi Kejiawei (kevlar aramicn monthly test philosopher, brother Vera fiber. The reinforcing material can also be fabric, Non-woven or ",, directional microfiber. Can be such as Shi Xi (grinding powder The melt is added to the film to 楛弁邋,) the temple filler...*,... the impact resistance and the thermal expansion match...using a commercially available pre-impregnated body' such as Oakley, Wisconsin, USA

Gore & Assoclates speedb〇ard c film is an example. The 2C and 2D views are respectively a cross-sectional view, a plan view, and a bottom view of the adhesive layer 26 having the opening 28. The opening 28 is a central opening 61 of a penetration adhesive layer. The open α 28 system was formed by mechanically drilling through the film and had a diameter of 115 Gm. The opening 28 can also be made by other techniques, stamping, and the like. 3D to 3D are cross-sectional views showing a method of fabricating a conductive layer in the embodiment of the present invention, and FIGS. 3 and 3F are respectively a plan view and a bottom view according to the first drawing. 3A is a cross-sectional view of the conductive layer 30. The conductive layer 3 is an electrical conductor. For example, the conductive layer 30 is a copper plate having no pattern and having a thickness of 125 μm. Fig. 3B is a cross-sectional view showing patterned etching resist layers 32 and 34 formed on the top and bottom surfaces of the conductive layer 3, respectively. The patterned etch stop layers 32 and 34 are similar to the photoresist layer of the patterned etch stop layer 16, wherein the photoresist layer (ie, the patterned etch resist layer 32) is provided with a selectively exposed conductive layer. The top surface pattern is 30, and the photoresist layer (ie, the patterned etch stop layer 34) is also provided with the same pattern 'to selectively expose the bottom surface of the conductive layer 30.

S 25 201133729 Figure 3C shows a conductive layer 30 having vias 36 formed in such a manner that the conductive layer 30 is etched in accordance with the pattern defined by the patterned etch stop layers 32 and 34. The illustrated etching method is a two-sided wet chemical etching. For example, a top nozzle (not shown) facing the patterned etch stop layer 32 can be used to spray the chemical etchant down onto the conductive layer 3 and the patterned etch stop layer U while using a pattern-oriented pattern. A bottom nozzle (not shown) of the etch stop layer 34 sprays the chemical etchant up onto the conductive layer 3 and the patterned etch stop layer 34. Alternatively, the structure may be immersed in a chemical etching solution. The chemical etching solution is highly targeted to steel and can etch the conductive layer 3〇. Therefore, the through holes 36 extend through the conductive layer 3A. The applicable chemical surrogate may be a solution containing ammonia or a diluted mixture of nitric acid and hydrochloric acid. In other words, the chemical etchant can be acidic or basic. The ideal etching time sufficient to form the vias 36 without causing the conductive layer 3A to be excessively exposed to the chemical etchant can be determined by trial and error. The 3D, 3E, and 3F are respectively a cross-sectional view, a top view, and a bottom view of the conductive layer 3 having the via holes 36 after the patterned (four) resist layers 32 and 34 are removed. The photoresist layer (i.e., patterned etch stop layers 32 and 34) may be stripped in the same manner as the photoresist layer (patterned etch stop layers 16 and 18). The through hole 36 is a central window extending through the conductive layer 3, and has a diameter of 1,150 μm. The through hole 36 can also be formed by other techniques such as mechanical drilling, punching, and stamping. Preferably, the opening 28 (Fig. 2B) has the same diameter as the through hole 36. 4A through 4L are cross-sectional views illustrating a method of fabricating a thermally conductive plate in accordance with one embodiment of the present invention, the thermally conductive plate including studs 22, a susceptor 24, an adhesive layer 26, and a conductive layer 30. The 4th & 4th views are the top view of the ceremony map 26 201133729 and the bottom view. 4A is a cross-sectional view showing the adhesive layer 26 disposed on the susceptor 24. Adhesive layer 26 is lowered onto susceptor 24 such that stud 22 is inserted upwardly through opening 28 and adhesive layer 26 contacts and is positioned at pedestal 24. Preferably, the stud 22 is aligned with the opening 28 after insertion and penetration through the opening 28 and is located centrally within the opening μ without contacting the adhesive layer 26. In the structure shown in Fig. 4, the conductive layer 3 is provided on the adhesive layer %. The conductive layer 30 is lowered onto the adhesive layer 26 such that the studs 22 are inserted upward into the through holes 36, and the conductive layer 30 contacts and is positioned at the adhesive layer %. Preferably, the stud 22 is aligned with the through hole after being inserted (but not penetrating) through the through hole 36 and located at a central position within the through hole 36 without contacting the conductive layer 3A. Therefore, the notch 38 is located in the through hole 36 and between the stud 22 and the conductive layer 3A. The notch 38 laterally surrounds the stud 22 while being laterally surrounded by the conductive layer 3〇. Further, the opening 28 and the through hole 36 are aligned with each other and have the same diameter. At this time, the conductive layer 30 is disposed on and in contact with the adhesive layer 26 and extends over the adhesive layer 26. The stud 22 extends through the opening 28 and into the through opening 36. The stud 22 is 50 microns lower than the top surface of the conductive layer 30 and is exposed in an upward direction by the through hole 36. Adhesive layer 26 contacts pedestal 24 and conductive layer 30 and is interposed therebetween. At this stage, the adhesive layer 26 is still a film of B-stage uncured epoxy resin, and the air in the notch 38 is 〇. FIG. 4C shows that the adhesive layer 26 is heated and pressurized and flows into the notch 38. In this figure, the method of forcing the adhesive layer 26 to flow into the indentation 38 applies downward pressure to the conductive layer 30 and/or applies upward pressure to the susceptor 24, i.e., a 27 S. 201133729 block 24 is opposite the conductive layer 30. Pressing is used to apply pressure to the adhesive layer; at this time, the adhesive layer 26 is also heated. The heated adhesive layer 26 can be formed under pressure (d). Therefore, the adhesive layer % between the susceptor 24 and the conductive layer 3 欠 is pressed, changes its original shape and flows upward into the notch 38. The susceptor 24 and the conductive layer 30 are continuously pressed toward each other until the adhesive layer % fills the notch %. In addition, after the gap between the susceptor 24 and the conductive layer 3 is reduced, the adhesive layer 26 still fills the reduced gap. For example, the susceptor 24 and the conductive layer 30 can be disposed between a press machine and a lower pressing table (not shown). In addition, an upper baffle plate and an upper buffer paper (not shown) may be interposed between the conductive layer 3 and the upper pressing table, and the lower and lower cushioning sheets (not shown) may be placed on the base. Between seat 24 and the next. The laminated body thus constructed is, in order from top to bottom, an upper pressing table, an upper baffle plate, an upper baffle paper, a conductive layer 30, an adhesive layer 26, a susceptor 24, a lower cushioning paper, a lower baffle plate, and a lower pressing table. The stack can be positioned on the lower press table by means of tool pins (not shown) extending upwardly through the alignment holes of the base 24 (not shown). The upper and lower press tables are then heated and pushed into each other, whereby the adhesive layer 26 is heated and pressed. The baffle can disperse the heat of the press table to uniformly apply heat to the base 24 and the conductive layer 30 or even the adhesive layer. The cushioning paper disperses the pressure of the pressing table so that the pressure is uniformly applied to the susceptor 24 and the conductive layer 3 or even the adhesive layer 26. Initially, the conductive layer 3 is in contact with and is pressed against the adhesive layer %. As the platen continues to operate and continues to heat, the adhesive layer 26 between the susceptor 24 and the conductive layer 3 is squeezed and begins to melt, thereby flowing upward into the notch % through the conductive layer 30. For example, the uncured epoxy resin is melted into the gap 38 after being melted by heat, but the reinforcing material and the filler remain between the susceptor 24 and the conductive layer 28 201133729 3〇. The adhesive layer 26 rises faster in the through hole 36 than the stud 22, and the full gap 38. The adhesive layer 26 also rises slightly above the notch 38 and overflows to the top surface of the stud 22 and the top surface of the conductive layer < This can happen if the film thickness is slightly larger than actually needed. Thus, the adhesive layer 26 is formed on the top surface of the stud 22 to cover the thin layer. The platen stops after touching the stud 22 but continues to heat the adhesive layer 26. a direction in which the adhesive layer 26 flows upward in the absence of d 38 as shown by the upward bold arrow in the figure. The upward movement of the stud 22 and the susceptor 24 with respect to the conductive layer 3Q is as indicated by the upward fine arrow, and the conductive layer 30 The downward movement relative to the stud 22 and the base 24 is as indicated by the downwardly fine arrow. The adhesive layer 26 in Figure 4D has cured. For example, after the platen stops moving, the post 22 and the base cymbal are continuously clamped and heated, # this converts the B-stage epoxy resin to C-stage curing or hardening. Epoxy tree month. Due to & epoxy resins are cured in a similar manner to conventional lamination. After the epoxy resin is cured, the platen is separated to remove the structure from the press. The cured adhesive layer 26 provides a strong mechanical bond between the stud 22 and the conductive layer 30 and between the pedestal 24 and the conductive layer 30. The adhesive layer can be subjected to normal operating pressure without deformation and damage. In case of excessive pressure, it is only temporarily distorted. Furthermore, the adhesive layer 26 can absorb thermal expansion mismatch between the stud 22 and the conductive layer 30 and between the pedestal 24 and the conductive layer 3A. At this stage, the studs 22 are substantially coplanar with the conductive layer 30, and the adhesive layer 26 and the conductive layer 30 extend to a top surface facing the upward direction. example

29 S 201133729 If the adhesive layer 26 between the pedestal 24 and the conductive layer 30 is 75 microns thick, it is reduced by 50 microns from its initial thickness of 125 microns; that is, the stud 22 is raised by 50 microns in the through hole 36, and the conductive layer 30 Then it is lowered by 50 micrometers with respect to the stud 22 . The height of the studs 22 of 200 microns is substantially equivalent to the combination of the conductive layer 30 (125 microns) and the underlying adhesive layer 26 (75 microns). In addition, the stud 22 is still located at the center of the opening 28 and the through hole 36 and is spaced apart from the conductive layer 3, and the adhesive layer 26 fills the space between the pedestal 24 and the conductive layer 3 and fills the gap 38. For example, the notch 38 (and the adhesive layer 26 between the stud 22 and the conductive layer 3) is 75 microns ((115 〇 -1 〇〇〇)/2) wide at the top surface of the stud 22 . The adhesive layer % extends across the conductive layer 3 in the notch 38. In other words, the adhesive layer 26 in the notch 38 extends in the upward direction and in a downward direction and spans the thickness of the conductive layer 3G of the outer sidewall of the notch. The adhesive layer 26 also includes a thin top portion ' above the notch % which contacts the top surface of the stud 22 and the top surface of the conductive layer 3 () and extends a micron over the stud 22 . In the projection shown in Fig. 4E, the top of the stud 22, the adhesive layer %, and the conductive sound 30 are removed. The top of the θ stud 22, the adhesive layer 26, and the conductive layer % is finely ground: except for, for example, the top of the structure is treated with a slave diamond wheel and distilled water. = Grinding the grinding wheel only grinds the layer 26. Continuous grinding, the occupation layer % layer does not necessarily have to be at the same time), and thus begins to grind the convex :: after the grinding: the studs ~ ... the conductive layer 3. = = Move and thin. The grinding is continued until the desired thickness is removed. The distilled water rinses the structure to remove dirt. Thereafter, the top of the adhesive layer 26 was ground to 25 μm by steaming, and the top of the conductive layer 22 was ground to 15 μm. The thickness reduction has a significant effect on the pillars 22 and the adhesive layer 2 "the conductive layer 3". At this point, the pillars 22, the adhesive layer 26 and the conductive layer 3 are co-located above the susceptor 24 toward the upward direction. The structure shown in FIG. 4F has a conductive layer 4 〇 deposited on the stud 22, the adhesive layer 26 and the conductive layer 30. The conductive layer 40 contacts the stud 22 and the adhesive layer 26 And the conductive layer 30, and covering the three from above. For example, the structure can be immersed in an activator solution so that the adhesive layer 26 can react with the electroless copper to generate a catalyst, and then a second copper layer is coated with an electroless ore. The method is disposed on the stud 22, the adhesive layer 26 and the conductive layer 30, and then a second copper layer is electroplated on the first copper layer. The first steel layer is about 2 microns thick and the second copper layer is thick. Approximately 13 microns, so the total thickness of the conductive layer 40 is about 15 microns. As a result, the thickness of the conductive layer is increased to about 125 microns (110 + 15). The conductive layer 40 is used as a cover layer and conductive One of the layers 3 加厚 a thickened layer. For convenience of explanation, the stud 22 and the conductive layer 40 and the conductive layers 30 and 40 are The layer is displayed. Since the steel is a homogeneous coating, the boundary between the pillars 22 and the conductive layer 40 and the boundary between the conductive layers 30 and 40 (both shown by dashed lines) may be difficult to detect or even undetectable. However, the adhesive layer 26 and the conductive layer The boundaries between the 40 lines are clearly visible. The upper and lower surfaces of the structure shown in Fig. 4G are respectively provided with a patterned etching resist layer 42 and a comprehensively covered etching resist layer 44. The patterned etching resist layer 42 is shown and The fully covered etch stop layer 44 is similar to the photoresist layer (ie,

S 31 201133729 Patterned etch stop layers 16 and 18) photoresist layer. The photoresist layer (i.e., the patterned etch stop layer 42) is provided with a pattern that selectively exposes the conductive layer 4'', and the photoresist layer (i.e., the etch stop layer 44 that is entirely covered) is unpatterned and covers the pedestal. In the structure shown in Fig. 4, the conductive layers 3 and 4 have been etched away from their selected portions to form a pattern defined by the patterned etch stop layer 42. The etching is similar to the front wet chemical etching applied to the metal plate. The chemical etching solution etches through the conductive layers 3 and 4 to expose the adhesive layer %, thereby converting the originally unpatterned conductive layers 30 and 4 to the pattern layer, and the susceptor 24 is not patterned. In Fig. 41, the patterned etch stop layer 42 on the structure and the fully covered #etch resist layer 44 have been removed. The photoresist layer (ie, the patterned etched layer 42 and the overlying resist layer 44) may be removed by removing the photoresist layer (ie, the patterned germanium) resist layer 16 and the fully covered (four) resist layer 18. The way is the same. After the etching, the conductive layers 30 and 40 include the bonding pad 46, the routing line 48 and the terminal 50, and the remaining conductive layer 4〇 includes the cover body, the routing wire and the terminal 50-based conductive layer 30 and 4〇 The patterned (4) resistive layer 42 (as shown in Fig. 4G) is protected from the part (4), and the cover 52 is protected by the patterned resistive layer 42 (Fig. 4G). Engraved part. As a result, the conductive layers 30 and 40 become patterned layers comprising solder bumps, routing lines 48 and terminals 50 but no cover 52. In addition, the routing line μ is a copper wire that contacts and extends over the adhesive layer 26 while abutting and electrically bonding the pad 46 to the terminal 50. The pad 46, routing line 48, and terminal % together form a wire 54. Routing 32 201133729 Line 48 is the conductive path between the pad 46 and the terminal 5〇. Wire 54 provides a horizontal (lateral) route from weld 46 $ sand 2 to a thousand. The wire 54 is not limited to the structure. For example, the conductive path may further include passive components such as δ and resistors and capacitors placed on other pads. The hot seat 56 includes a stud 22, a base 24, and a cover 52. The stud 22 is integrally formed with the base 24. The cover 52 is located above the top of the stud 22 adjacent the top of the stud 22 while covering the top of the stud 22 from above and extending laterally from the top of the post 22. After the cover 52 is provided, the stud 22 is seated in a central region within the circumference of the cover 52. The cover 52 also contacts the portion of the adhesive layer 26 from above which is attached to the adhesive layer 26, and the portion of the adhesive layer is coplanar with the projections 22, adjacent to the projections 22, while laterally surrounding the projections 22. The post 2 'seat 56 is essentially an inverted heat sink block that includes a post (convex) wing.卩 (the portion of the pedestal 24 extending laterally from the column portion) and a guide pad (cover 52). The structure of Fig. 4J is provided with a solder resist green paint 58 on the adhesive layer % 'conductive layer 4' and the cover %. The solder resist green paint 58 is an electrically insulating layer which can be patterned to expose the material 46, the terminal 5 turns and the cover 52, and covers the outer portion of the adhesive L6 and the routing line 48 from above. The solder resist green paint 58 has a thickness of 25 microns above the pad 46 and the terminal turns, and the solder resist green paint extends 150 microns (125 + 25) above the adhesive layer %. The solder resist green paint 58 is initially a light-developing liquid helium that is applied to the structure. Then, a pattern is formed on the solder resist green paint 58. The method is to selectively pass the light through the mask (not shown) to make the portion of the light-receiving portion of the green paint lacquered to be 33 201133729 insoluble, and then use the __ developing solution portion. Soluble. The lacquer 58 is finally hard baked. The above steps are the base 24 of the structure shown in Fig. 52, the solder bump 46, and the terminal 50 and the cover 52 have covered contacts 60. The broken contact 60 is a multi-layer metal plating which contacts and covers the seat 24 from below and contacts the solder tab 46, the terminal 5q and the cover u from above to cover the exposed portion thereof. For example, the nickel layer is gas-freely coated on the susceptor 24, the solder bumps 46, the terminals 50 and the cover 52, and then a gold layer is placed on the brocade in a manner free of electricity. The layer thickness is about 3 microns and the surface gold layer is about 0.5 microns thick, so the thickness of the covered joint (6) is 3 · 5 microns. The surface treatment with the covered contacts 60 as the susceptor 24, the pads 46, the terminals 5, and the cover 52 has several advantages. The inner recording layer provides the main mechanical and electrical connection and/or thermal connection ' while the surface gold layer provides the wettable surface for solder reflow. The covered contact 60 also protects the pedestal 24, the solder 塾 46, and the sub-layer. 50 and the cover 52 are not rotted #. The covered joints 6〇 can contain various metals Z in accordance with the needs of externally connected media. For example, a silver layer coated on a nickel layer can be soldered or wired. 3 For convenience of explanation, the susceptor 24 provided with the covered contacts 60, the solder bumps, the terminals 50 and the cover 52 are all displayed in a single-layer manner. The boundary between the covered contact 6 〇 and the susceptor 24, the pad 46, the terminal 50 and the cover 52 (not shown) is a copper/recording interface. The fabrication of the heat conducting plate 62 (Fig. 4L) is thus completed. 34 201133729 The 4L, 4M and 4N drawings are respectively a cross-sectional view, a top view and a bottom view of the heat conducting plate 62, in which the edge of the heat conducting plate 62 has been separated along the cutting line from the support frame and/or the adjacent heat conducting plate produced in the same batch. The heat conducting plate 62 includes an adhesive layer 26, a wire 54, a heat sink %, and a solder resist green paint 58. Wire 54 includes pad 46, routing line 48, and terminal 50. The heat sink 56 includes a stud 22, a base 24, and a cover 52. The post 22 extends through the opening 28 (Fig. 4B) and remains centrally within the opening 28 and is coplanar with an adjacent portion of the adhesive layer 26 above the bottom surface of the pad 40. The stud 22 maintains a flat-topped tapered cylindrical shape with tapered side walls that decrease in diameter from the base 24 toward the flattened dome adjacent the cover 52. The base 24 covers the stud 22, the adhesive layer 26, the cover 52, the wire 54 and the solder resist green paint 58 from below and extends to the peripheral edge of the heat conducting plate 62. The cover 52 is located above the stud 22 and is adjacent to and thermally coupled. The cover 52 simultaneously covers the top of the stud 22 from above and extends laterally from the top of the stud 22 . The cover 52 also contacts and covers a portion of the adhesive layer 26 from above, the portion of the adhesive layer 26 abutting the stud 22, coplanar with the stud 22, and laterally surrounding the post 22. The cover 52 is also coplanar with the pads 46 and the terminals 50 above the adhesive layer 26. The adhesive layer 26 is disposed on the base 24 and extends above it. The adhesive layer 26 extends between the studs 22 and the pads 46 in the notches 38; it contacts between the pedestals 24 and the wires 54 outside the notches 38, and fills the space between the pedestals 24 and the wires 54. . The adhesive layer 26 extends laterally from the stud 22 and over the zither 50' and is overlapped by the terminal 5'. Further, the adhesive layer 26 covers the base 24 from above with a portion outside the periphery of the stud 22 and covers the 35 201133729 wire 54 from below while contacting, covering and surrounding the stud 22 in the lateral direction. Adhesive layer 26 is confined within the space between conductor 54 and heat sink 56 and fills most of this space. At this time, the adhesive layer 26 has solidified. Lead 54 (and pad 46, routing line 48 and terminal 50) are disposed on adhesive layer 26, contact and overlap the adhesive layer %, and extend over the adhesive layer %. Both the base 24 and the cover 52 of the stud 22 are spaced from the wire 54. Therefore, the wires 54 are mechanically coupled to the heat sink 56 and electrically isolated from each other. After the same batch of thermally conductive plates 62 have been cut, the base 24, the adhesive layer 26 and the solder resist green paint 58 extend to the cut vertical edges. The pad 46 is a semiconductor element such as an LED package or a semiconductor chip! ^ The customized electrical interface, the semiconductor component will be set in the subsequent process; the cover 52. Terminal 5 is a tailor-made electrical interface for the next layer of components (e.g., solderable wires from a printed circuit board). The cover 52 is a thermal interface tailored specifically for the semiconductor component. The pedestal 24 is a hot interface tailored to the next set of components (such as the heat sink of a sub-device). In addition, the cover body 52 is thermally coupled to the susceptor % via the studs 22 . The pad 46 and the terminal 5G are laterally offset from each other and are exposed on the top surface of the heat conducting plate 62, thereby providing a horizontal input/output routing between the semiconductor component and the lower-layer assembly. The top surface of the θ 6 terminal 50 and the lid body 52 are coplanar above the adhesive layer 26. For ease of illustration, the conductor 54 is shown in cross-section as a continuous circuit trace. However, when the wire 54 is turned on (4), the horizontal signal of the γ#γ direction is provided. 36 201133729 = The pad 46 and the terminal 5 形成 form a lateral misalignment in the χ #γ direction, and the routing line 48 constitutes a path in the 乂 and 丫 directions. The heat sink 56 diffuses the thermal energy generated by the semiconductor component subsequently disposed on the cover 52 to the submount of the heat sink 56. The heat energy generated by the semiconductor component flows into the body 22 from the cover 52 and enters the base 24 via the boss 22. Thermal energy is dissipated from the susceptor 24 in the downward direction, for example, to a lower heat sink. The pillars 22 and the routing wires 48 of the heat conducting plate 62 are not exposed. The pillars 22 are covered by the cover 52, and the routing line 48 is covered by the solder resist green paint. The top surface of the adhesive layer 26 is simultaneously covered by the cover 52 and Anti-weld green paint brothers cover. For convenience of explanation, the fourth figure shows the stud 22, the adhesive layer %, and the routing line 48 with a dotted line. Thermally conductive plate 62 also includes other conductors 54, which are substantially comprised of pads 46, routing wires 48 and terminals 5A. For ease of explanation, only a single wire turns are illustrated and illustrated herein. In wire 54, pad 46 and terminal 50 are generally of the same shape and size, while routing line 48 is typically of a different routing configuration. For example, a portion of the conductors 54 are spaced apart from each other and electrically isolated, and a portion of the conductors 54 are staggered or directed to the same pad 46, routing line 48 or terminal 50 and electrically coupled to one another. Similarly, a portion of the pad 46 can be used to receive an independent signal, while a portion of the pad 46 shares a sfL number, power supply or ground. The heat conducting plate 62 can be applied to an LED package having blue, green and red LED chips, wherein each LED chip comprises an anode and a cathode, and each LED package comprises a corresponding anode terminal and cathode terminal. In this example, 37 201133729 _ 62 may include six pads 46 and four terminal % to direct each anode from the individual material 46 - separate % and direct each cathode from a separate pad 46 A common ground terminal 5〇. The fabric can be removed at various stages of manufacture - a simple cleaning step to remove oxides and residues from the exposed metal. For example, a short oxygen plasma cleaning step can be applied to the structure. Alternatively, the structure of the present invention may be subjected to a short wet chemical cleaning step. Similarly, the structure can be rinsed with distilled water to remove dirt. This cleaning step cleans the surface as needed without causing significant damage or damage to the structure. The advantage of this case is that there is no need to separate or separate the confluence points or associated circuitry from the wires 54 after they are formed. The confluence point can be separated during the wet chemical etching step of forming the pad 46, the routing line 48, the terminal 5, and the cover 52. The heat conducting plate 62 may include alignment holes (not shown) formed by drilling or cutting through the base 24, the adhesive layer 26 and the solder resist green paint 58. In this way, when the heat conducting plate 62 needs to be disposed on a lower carrier in a subsequent process, the tool pin can be inserted into the alignment hole to position the heat conducting plate 62. The cover 52 can be omitted from the heat conducting plate 62. To achieve this purpose, the patterned surname resist layer 42 (as shown in FIG. 4H) can be adjusted to expose the conductive traces 4 above the entire via 36 to the pads 46, the routing lines 48 and the terminals 50. In chemical silver engraving. Another method of omitting the cover 52 is to provide no conductive layer 4 (Fig. 4J). The heat conducting plate 62 can accommodate a plurality of semiconductor elements instead of only a single half of the conductor elements. To achieve this goal, the patterned etch stop layer 16 (as shown in FIG. 1C) can be modified to define more bumps 22, the adhesive layer 26 can be adjusted to include more openings 28 38 201133729, and the conductive layer 30 can be adjusted to include more passes. Hole 36 (Fig. 4B), the patterned etch stop layer 42 (Fig. 4H) is adjusted to define more pad private, routing core, terminal M) and cover 52, and adjust the solder resist green paint 58 to include More openings. Elements other than terminal 50 can change the lateral position to provide an array of four semiconductor components. In addition, the cross-sectional shape and height (ie, side shape) of some but not all components may be adjusted. For example, pad 46, terminal 5〇 and cover 52 can maintain the same side shape, while routing line 48 has a different routing configuration. 5A, 5B, and 5C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package in accordance with an embodiment of the present invention, the semiconductor wafer package including a heat conductive plate and an LED package having a back contact. The semiconductor wafer package 1 includes a heat conductive plate 62, an LED package i 〇 2, and first and second solders 104 and 1 〇6. The LED package 1〇2 includes an LED wafer 108, a pedestal 11 〇, a wire 112, an electrical contact 114, a thermal contact 116, and a transparent encapsulation material 118. One of the LED chips 1 〇 8 (not shown) is electrically connected to one of the pedestals 11 导电 via a wire 112 (not shown) to electrically connect the LED chip 108 to the electrical contact U4. The LED chip 108 is disposed on the susceptor 110 through a die bonding material (not shown), and the LED chip 108 is thermally bonded and mechanically adhered to the pedestal 11 〇, thereby thermally bonding the LED chip 108 to the thermal connection. Point 116. The susceptor 11 is a ceramic block having low conductivity and high thermal conductivity, and the contacts 114 and 116 are covered on the back of the pedestal 11 and protrude downward from the back of the pedestal 110.

The LED package 1〇2 is disposed on the wire 54 and the heat sink 56, electrically connected to the wire 54 and thermally coupled to the heat sink 56. In detail, the LED 201133729 package 102 is disposed on the pad 46 and the cover 52 , overlaps the stud 22 ′ and is electrically connected to the wire 54 via the first solder 104 , and is thermally coupled to the second solder 106 via the second solder 106 . Heat sink 56. For example, the first solder 1〇4 contacts and is located between the bonding pad 46 and the electrical contact 114, and electrically and mechanically bonds the bonding pad 46 and the electrical contact 114, thereby electrically connecting the LED chip 1〇8. Connected to terminal 50. Similarly, the second solder 106 contacts and is located between the cover 52 and the thermal contact 116 while thermally bonding and mechanically bonding the cover 52 and the thermal contact 116 ' thereby thermally bonding the LED wafer 108 to the pedestal 24 . The pad 46 is provided with a gold-plated metal bond to facilitate solid bonding with the first solder 1 〇 4, and the shape and size of the pad 46 are matched with the electrical contacts 114, thereby improving the self-conducting wire 54 to the LED package. The signal transmission of the body 1〇2. Similarly, the cover body 52 is provided with a nickel/gold coated metal pad for stable bonding with the second solder 1〇6, and the shape and size of the cover 52 are matched with the thermal contact 116, thereby improving the self-package body. The heat transfer from 102 to the heat sink 56. As for the shape and size of the stud 22, it is not and does not need to be designed with the hot joint 丨丨6. The transparent encapsulating material 118 is a solid electrically insulating protective plastic covering body, which can provide environmental protection such as moisture resistance and anti-particles for the wafer 108 and the wire 112. The wafer 1 (8) and the wire 112 are embedded in the transparent packaging material. 118 in. To fabricate the semiconductor wafer package 100, a solder can be deposited on the pad and the cover 52, and the contacts 114 and 116 are placed on the solder on the pad % and the body 52, respectively, and then the solder is returned. Welding is performed to form the first first solders 104 and 106. For example, the solder paste is selectively printed on the pad 40 201133729 46 and the cover 52 by screen printing, and then the LED package 1 is stepped and repeated by using the grab head and the automated pattern recognition system. 〇2 is placed above the heat conducting plate. * The picking head of the wide welding machine places the contacts 114 and 116 on the solder paste above the soldering pad and the cover 52, respectively. Then heat the solder paste 'to make it at a relatively low temperature (such as 190. 〇 reflow) and then remove the heat source, #wait the solder paste to cool and solidify to form the hardened first and second solder just hired. Place tin on the pad 46 and the cover 52, and then place the contacts ι 4 and μ on the solder balls above the solder 46 and the cover 52, and then heat the solder balls to reflow to form the next First, the second solder 1〇4 and 1〇6. The solder may initially be deposited on the heat conducting plate 62 or the LED package 1〇2 via coating or printing or placement techniques, between the heat conducting plate 62 and the LED package 102. And solder reflow. Solder can also be placed on the terminal % for use in the next group. In addition, solder can be replaced with a conductive adhesive (such as silver-filled epoxy) or other bonding medium, and soldered. The connection medium on the pad 46 and the terminal and the cover 52 need not be the same. The semiconductor semiconductor package 1 is a second-order single crystal module. The sixth embodiment, the sixth embodiment, the sixth embodiment, the sixth embodiment, the sixth embodiment, the sixth embodiment, the sixth embodiment, the sixth embodiment, the sixth embodiment a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package, wherein the semiconductor wafer The assembly includes a heat conducting plate and an LED package having side pins. In this embodiment, the LED package has side pins and no back contacts. For simplicity, the group 100 is related. The description applies to this embodiment, and the description of (4) is not repeated. Similarly, the S piece of the embodiment is similar to the component of the group _, and the corresponding reference number is used, but the code is encoded. The base number is changed from 100 to 2. For example, led chip

41 S 201133729 208 corresponds to LED chip 108, while pedestal 210 corresponds to pedestal 11 〇 , and so on.

The semiconductor wafer package 200 includes a heat conductive plate 62, an LED sealing body 202, and first and first solders 204 and 206. The LED package 202 includes an LED wafer 208, a pedestal 210, a wire 212, a pin 214, and a transparent encapsulant 218. The LED chip 208 is electrically coupled to the pin 214 via the wire 212. The back side of the susceptor 210 includes a thermal contact surface 216. Further, the pedestal 21 is narrower than the pedestal 110 and has the same lateral dimensions and shape as the thermal contact surface 216. The LED chip 208 is disposed on the susceptor 21 via a die bond material (circular not shown) to thermally bond the LED die 208 and mechanically adhere to the pedestal 21 〇, thereby thermally bonding the LED chip 208 to the thermal contact. Surface 216. Pin 214 extends laterally from pedestal 210 with thermal contact surface 216 facing downward. The LED package 202 is disposed on the wire 54 and the heat sink, electrically connected to the wire 54, and thermally coupled to the heat sink 56. In detail, the LED package 202 is disposed on the pad 46 and the cover 52 , overlaps the stud 22 , is electrically connected to the wire 54 via the first solder 204 , and is thermally coupled to the heat through the second solder 206 . Block 56. For example, the first solder 2 〇 4 contacts and is located between the solder bumps 46 and the leads 214 , and electrically and mechanically bonds the solder pads 46 and the leads 214 , thereby electrically connecting the LED chips 208 to the terminals 50 . . Similarly, the second solder 206 contacts and is positioned between the cover 52 and the thermal contact surface 216 while thermally bonding and mechanically bonding the cover 52 to the thermal contact surface 216' thereby thermally bonding the LED wafer 208 to the pedestal 24. If the semiconductor wafer package 200 is to be fabricated, a solder may be placed on the solder bumps 46 and the cover 52, and then the pins 214 and the thermal contact surfaces 216 are placed on the solder pads 42 201133729 above the pads 46 and the cover 52, respectively. The solder is then reflowed to form the first and second solders 2〇4 and 2〇6. The semiconductor wafer package 200 is a second-level single crystal module. 7A, 7B, and 7C are respectively a semiconductor wafer according to an embodiment of the present invention: and a J-view, a top view, and a bottom view of the body, wherein the semiconductor wafer package includes a heat conductive plate and a semiconductor wafer β. In an embodiment, the semiconductor component is a wafer rather than a package ' and the wafer is disposed on the heat sink instead of the wire. Further, the wafer is overlapped with the studs instead of the wires, and the wafer is electrically connected to the solder fillet via a wire and thermally bonded to the cover by a die bonding material. The semiconductor wafer package 300 includes a heat conductive plate 62, a wafer 3, a wire bond, a die bonding material 306, and a package material 3〇8. The wafer 3〇2 includes a top surface, a bottom Φ 312, and a wire bonding pad 314. The top surface 31 is an active surface and includes a wire bond pad 314, while the bottom surface 312 is a thermal contact surface. The chip 302 is disposed on the heat sink 56, electrically connected to the wire Μ, and thermally coupled to the heat sink 56. In detail, the wafer transfer system is disposed on the lid body 52, is located in the periphery of the lid body 52, and overlaps the stud 22 but does not overlap the lead wire 54. In addition, the 'wafer 3〇2 is electrically connected to the wire 54 via a wire, and is thermally coupled via the die bonding material 3〇6 and mechanically adhered to the heat sink 56. For example, the wire is connected to the wire and is electrically connected to the pad. And bonding the wire pad 314, thereby electrically connecting the wafer 3〇2 to the terminal 5〇. Similarly, the die bonding material 306 is in contact with and located between the cover body μ and the bottom surface 312 (ie, the thermal contact surface) while thermally bonding and mechanically bonding the cover 52 to the bottom surface 312, thereby thermally bonding the S-43 201133729 wafer 302 to Base 24. The pad 46 is provided with a nickel/silver coated metal pad to securely engage the wire 3〇4, thereby improving the signal transmission from the wire 54 to the chip 302. In addition, the shape and size of the cover 52 is adapted to the bottom surface 312, thereby improving heat transfer from the wafer 3〇2 to the heat sink. The shape and size of the studs 22 are not designed and do not need to be matched to the bottom surface 312. The encapsulating material 308 is a solid electrically insulating protective plastic covering that provides environmental protection for the wafer 302 and the wire 304 against moisture and particulates. The wafer 302 and the wire 304 are embedded in the packaging material 3〇8. In addition, if the wafer 302 is an optical wafer such as an LED, the encapsulating material 3〇8 may be transparent. The encapsulating material 308 is transparent in FIG. 7B for convenience. If the semiconductor wafer assembly 300 is to be fabricated, the wafer 302 may be placed on the cover 52 by means of a die bonding material 3? 6, and then the pad 46 and the bonding pad 314 may be wire bonded to form a package material 308. For example, the die bond material 306 is originally a silver-containing epoxy resin paste having high thermal conductivity and is selectively printed on the cover 52 by screen printing. The wafer 302 is then placed on the epoxy silver paste in a step-and-repeat manner using a gripping head and an automated pattern recognition system. The epoxy silver paste is then heated and hardened at a relatively low temperature (e.g., 190 ° C) to complete the solid crystal. The wire 304 is a gold wire which is then connected to the bonding pad 46 and the wire bonding pad 314 by thermal ultrasonic waves. Finally, the encapsulation material 308 is transferred onto the structure. The wafer 302 can be electrically connected to the bonding pad 46 through a plurality of bonding media, thermally bonded or mechanically adhered to the heat sink 56 by a plurality of thermal adhesives, and packaged in a package material of 201133729. The semiconductor wafer package 300 is a first-level single crystal package. 8A, 8B and 8C are respectively a light source sub-body in an embodiment of the invention. The top view, the top view and the bottom view, wherein the subgroup of the light source comprises a semiconductor wafer package and a heat sink. The light source sub-assembly 400 includes a semiconductor wafer package 1 and a heat sink 402. The heat sink 402 includes a thermal contact surface 404, fins 406, and a fan 408. The semiconductor wafer package 1 is disposed on the heat sink and mechanically coupled to the heat sink 402, for example, by screws (not shown). Therefore, the susceptor 24 is fastened to and thermally coupled to the thermal contact table, thereby thermally connecting the heat sink 56 to the heat sink 4〇2. The heat sink % can diffuse the heat energy generated by l U 1 曰曰08, and transfer the heat energy of the diffusion to the heat sink 4〇2' heat sink 402, then use the Korean film 4〇6 and the fan 4〇8 to dissipate 2 heat energy to Peripheral environment. - The light source sub-assembly 400 is designed as a lamp holder that can be replaced with a standard incandescent light bulb. The lamp holder comprises a sub-assembly 4〇〇, a glass cover, a threaded base, a control board, a line and a casing. The sub-group 4〇〇, the control board and the line are coated on the material (4). The material extends from the laminate and is soldered to the terminals. The glass cover and the threaded base respectively protrude at both ends of the outer casing. The glass cover exposes the LED chip 1 8 to the outer end. The threaded base can be screwed into the light source socket, and the control board is electrically connected to the terminal 50 through the line. The outer casing is a two-piece plastic case divided into two parts. The glass cover is adhered and protrudes above the upper half of the outer casing, and the threaded base is adhered to and protrudes from the lower portion of the outer casing. The light source sub-assembly 400 45 201133729 and the control plate are disposed in the lower half of the outer casing and extend into the upper half of the outer casing. In operation, the threaded base transfers AC power from the light source socket to the control panel, which converts the alternating current to a rectified direct current. On the one hand, the line transmits the rectified direct current to the terminal 5, and the other terminal 50 is grounded on the other side. Therefore, the LED chip 1 8 can be illuminated by the glass cover. & The powerful local thermal energy generated by the LED chip 1G8 flows into the heat sink 56 and is diffused by the heat sink 56 to the heat sink 4〇2. The fins 406 in the heat sink 402 transfer heat energy to the air, and the hot air is blown through the long holes in the casing by the fan 4 to radially radiate into the peripheral environment. The semiconductor wafer package and the heat conducting plate described above are merely illustrative examples, and the present invention can be implemented by other various embodiments. Furthermore, the above embodiments may be relied upon. also. The ten and the guilty exams are used in combination with each other or in combination with other embodiments. For example, the semiconductor component can be an -LED package and wire bonded to the wire; the semiconductor component can also be a - semiconductor wafer and overlap the wire. The thermally conductive plate may comprise a plurality of studs, and the studs are arranged in an array for use with a plurality of semiconductor components. Further, the guide plate may include more wires for mating additional semiconductor components. Similarly,

The semiconductor component can be an LED package having a multi-grazing IF negative LED chip, and the thermally conductive sheet contains more wires (4) and additional LED chips. The semiconductor component can use the heat sink alone or share the heat sink with other semiconductor components. For example, a single semiconductor component may be disposed on the heat sink, or a plurality of semiconductors may be mounted on the heat sink. For example, four small arrays of thin wafers can be attached to the studs, 46 201133729, and the thermally conductive plates can include additional wires to accommodate the electrical connections of the wafers. This practice is far more economical than placing a tiny stud on each wafer. The semiconductor wafer can be optical or non-optical. For example, the wafer can be an LED' - a solar cell, a microprocessor, a controller or a radio frequency power amplifier. Similarly, the semiconductor package is a led package or a thin package a. Thus, the semiconductor component can be an encapsulated or unpackaged optical or non-optical wafer. In addition, the semiconductor element can be mechanically bonded, electrically connected, and thermally bonded to the thermally conductive plate by a variety of bonding media, including by soldering and using conductive and/or thermally conductive adhesives. The heat sink can quickly, efficiently and evenly dissipate the heat generated by the semiconductor component to the next layer without passing heat through the adhesive layer, the wire or other portion of the heat conducting plate. As a result, an adhesive layer having a lower thermal conductivity can be used, thereby greatly reducing the cost. The heat sink can include an integrally formed stud and a base, and a cover body that is metallurgically coupled and thermally coupled to the stud, thereby improving reliability and reducing cost. The cover may be coplanar with the pad to form electrical, thermal and mechanical bonds with the semiconductor component. In addition, the cover can be tailored to the semiconductor component, and the pedestal can be tailored to the next layer of components to thereby enhance thermal bonding from the semiconductor component to the next layer. For example, the stud may be circular in a lateral plane, the cover may be square or rectangular in a lateral plane, and the side shape of the cover is the same as the side shape of the thermal junction of the semiconductor element or similar. The heat sink can be electrically connected to the semiconductor component and the wire or electrically isolated. For example, the second conductive layer on the polished surface can include a routing line extending between the wire and the cover through the adhesive I' to electrically connect the semiconductor component to the Heat sink. Thereafter, the heat sink can be electrically grounded to electrically ground the semiconductor component. The heat sink can be copper, aluminum, steel/nickel/aluminum alloy or other thermally conductive metal structure. - The stud can be deposited on the base or integrally formed with the base. The studs can be associated with the base-body filaments and thus become a single-metal body (e.g., copper or inscription). The stud can also be integrally formed with the base such that the interface between the two comprises a single metal body (for example, copper)', and other portions include other metals (for example, the upper portion of the stud is solder, the lower portion of the stud and the base) The copper pillar may also be integrally formed with the base such that the interface between the two comprises a plurality of single metal bodies (for example, a nickel buffer layer is disposed on an aluminum core peripheral portion, and a copper buffer layer is disposed on the nickel buffer layer). The protrusion may include a flat top surface, and the top surface is coplanar with the adhesive layer. For example, the protrusion may be coplanar with the adhesive layer, or the protrusion may be cured after the adhesive layer is cured Receiving an etch, thereby forming a recess in the adhesive layer above the stud. We can also selectively etch the stud to form a recess in the stud that extends below its top surface. The semiconductor component can be disposed on the stud and located in the recess, and the wire can extend from the semiconductor component in the cavity to the pad outside the cavity. In this case, the The semiconductor component can be an LED wafer, and The recess focuses the LED light toward the upward direction. 48 201133729 The pedestal provides mechanical support for the wire. For example, the pedestal stops the conductive layer from deforming during the metal grinding process and prevents the wafer from being deformed. During the process of setting, wire bonding and molding the material, the base can also be covered by the base. The base can also cover the group from below. In addition, the backing of the base includes the sisters protruding in the downward direction. The sheet, for example, can be cut by a rig to cut the bottom surface of the pedestal to form a lateral groove, and the lateral grooves are the rotators. In this case, the thickness of the pedestal can be & The depth of the grooves may be 500 micrometers, that is, the height of the rotors may be micrometers. The spacers may increase the surface area of the base, if the Korean films are exposed to the air instead of being disposed. In the heat sink, the thermal conductivity of the susceptor via convection can be improved. The cover can be formed by various deposition techniques before, during or after the solder bump and/or the terminal is formed. Formation, including electroplating, electroless ore coating, evaporation and splashing Forming a single layer or a multi-layer structure. The cover body may be made of the same metal material as the protrusion or the same metal material as the top of the protrusion adjacent to the cover body. In either case, the cover body is The top of the stud extends laterally in a lateral direction. The adhesive layer provides a strong mechanical connection between the heat sink and the wire. For example, the adhesive layer can extend laterally from the stud and over the The wire reaches the peripheral edge of the group, the adhesive layer can fill the space between the base and the wire, the adhesive layer can be located in the space between the heat sink and the wire, and the adhesive layer can be uniform The non-porous structure of the bonding wire of the distribution. The adhesive layer can also absorb the mismatch between the heat sink and the wire due to thermal expansion. In addition, the adhesive layer can be a low-cost dielectric, 49 201133729 and does not need to be high Thermal conductivity. Furthermore, the adhesive layer is not easily delaminated. We can adjust the thickness of the adhesive layer so that the adhesive layer is two, and almost all the adhesives are located in the knot after curing and/or grinding. For example, the ideal thickness of W can be determined by trial and error. Similarly, we can also adjust the thickness of the conductive layer to achieve this effect. The conductive layer can be separately disposed on the adhesive layer. For example, the conductive layer may be first cut into the through hole, and then the conductive layer (excluding other layer) is disposed on the adhesive layer, so that the conductive layer contacts the adhesive layer and is exposed toward the upward direction. At the same time, the stud extends into the through hole and is exposed through the through hole in the upward direction. In this case, the conductive layer may have a thickness of 100 to 200 micrometers, for example, 125 micrometers, and the thickness is thick enough on the one hand, so that it does not cause bending and shaking during transportation, and can withstand high driving current on the one hand, and is thin enough, so that it is not required Excessive moments can form a pattern. The conductive layer may also be disposed on the adhesive layer simultaneously with a carrier. For example, the conductive layer may be adhered to a carrier such as a double-oriented polyethylene terephthalate film (Mylar) by using a film, and then the via hole is formed only on the conductive layer instead of the carrier, and then The conductive layer and the carrier are disposed on the adhesive layer, the carrier covers the conductive layer, and is exposed toward the upward direction and the film is contacted and interposed between the carrier and the conductive layer, as for the conductive layer Then contacting and interposed between the film and the adhesive layer, at the same time 'the pillar is aligned with the through hole and covered by the carrier from above. After the adhesive layer is cured, the film can be decomposed by ultraviolet light to strip the carrier from the conductive layer to expose the conductive layer in the upward direction, and then the conductive layer can be ground and patterned to form The wire. In this case, 50 201133729 the conductive layer may have a thickness of 10 to 50 micrometers, for example 3 micrometers, which is thick enough to provide reliable signal transmission and thin on the one hand to reduce weight and cost; As for the thickness of the carrier, it can be 3 〇〇 to 5 〇〇 micrometers, and the thickness is thick enough on the one hand, so that it does not bend and shake when transported, and is sturdy on the other hand, which helps to reduce weight and cost. The carrier is only a temporary fixture ‘not permanently part of the heat conducting plate. ° Xuanzhi and the terminal can be used in a variety of package forms depending on the needs of the semiconductor component and the next layer. The pad and the top surface of the cover may be coplanar, so that the welding between the body element and the heat conducting plate can be strengthened by controlling the tin (4) and (4). The solder pad, the terminal and the routing line can be formed by various deposition techniques, including plating, no f mine coating, evaporation, splashing, etc., when the conductive layer or the wire is not yet or already disposed on the adhesive layer. The technology forms a single layer or a multilayer structure. For example, the pattern of the conductive layer may be formed prior to a carrier, and the conductive layer may be disposed on the adhesive layer. Alternatively, the conductive layer may be patterned by using the adhesive layer, and the step of surface-treating the conductive layer to the pillar and the substrate may be performed before the solder bump and the terminal are formed or After that. For example, the capping layer can be deposited on the first conductive layer. The pad, the terminal and the routing line are then defined by a patterned etch stop layer to impart a pattern to the county layer. The wire can contain additional tantalum, terminal and routing wires, and passive components, and can be of the (four) type. The feed line can be - (four) layer, - power layer 51 £ 201133729 or a ground plane ' depending on the purpose of its corresponding semiconductor component pad. The wire may also comprise various conductive metals such as copper, gold, ruthenium, silver, palladium, tin, mixtures thereof, and alloys thereof. The ideal composition depends on both the nature of the external media and the design and reliability considerations. In addition, those skilled in the art should be able to understand that 'the copper used in the semiconductor wafer package can be pure copper' but is usually a copper-based alloy such as copper-wrong (99.9% copper), copper-silver- Fill- town (99.7% copper) and copper-tin-iron-phosphorus (μ.?% copper) to improve mechanical properties such as tensile strength and ductility. In general, it is preferable to provide the cover, the anti-knowledge green paint, the coated contact, and the second conductive layer on the surface after the polishing, but it may be omitted in some embodiments. For example, if the opening and the through hole are formed by punching instead of drilling, and thus the shape and size of the top of the stud are matched with the thermal contact surface of the semiconductor element, the cover and the cover may be omitted. The second conductive layer reduces cost. The heat conducting plate may include a heat conducting hole that is spaced from the stud and extends outside the opening through the adhesive layer while abutting and thermally joining the base and the cover body The heat dissipation effect of the cover to the base and the promotion of thermal energy diffusion in the base. The heat shield can be operated in a single or multiple heat shield depending on the manufacturing design. For example, a single heat conducting plate can be fabricated separately. Alternatively, a plurality of thermally conductive plates can be fabricated from a single metal sheet, a single adhesive layer, a single conductive layer, and a single tamper-proof green paint simultaneously and then separated. Similarly, for each of the heat-conducting plates in the same batch, we can also use a single metal plate, a single adhesive layer, a single conductive layer and a single solder-proof green paint to simultaneously manufacture multiple sets of separate 52 201133729 for the heat dissipation of a single semiconductor component. Seat and wire. For example, a plurality of grooves may be formed on a metal plate to form the base and the plurality of protrusions; and then an uncured adhesive layer having openings corresponding to the protrusions is disposed on the base, Extending each of the studs through a corresponding opening: then, a conductive layer having a through hole corresponding to the stud is disposed on the adhesive layer, so that each (four) corresponds to and enters the corresponding through hole. Then, the susceptor and the conductive layer are pressed against each other by the pressing table, forcing the adhesive layer to enter a gap between the protruding pillars and the conductive layer in the through holes; then curing the adhesive layer, and then grinding the convexities a pillar, the adhesive layer and the conductive layer to form a top surface; then, a second conductive layer is coated on the pillars, the adhesive layer and the conductive layer; and then the conductive layers are etched to form a plurality of groups respectively The pad, the terminal and the routing line of the stud should be equal, and the second conductive layer is etched to form a plurality of caps respectively corresponding to the studs; then the solder resist green paint is placed on the structure to make the solder resist Green paint produces a pattern to expose the pads, etc. And the cover body; and then the base, the pads, the terminals and the cover are surface-treated by the covered contacts, and then cut or split at appropriate positions on the peripheral edge of the 4 heat-conducting plates The susceptor, the adhesive layer and the solder resist green lacquer separate individual heat conducting plates from each other. The operational format of the semiconductor wafer package can be a single assembly or multiple assemblies' depending on the manufacturing design. For example, a single set can be manufactured separately. Alternatively, each of the heat conducting plates may be separated one by one after the plurality of groups can be manufactured at the same time. Similarly, a plurality of semiconductor elements can be electrically connected, thermally coupled, and mechanically coupled to each of the heat conducting plates in mass production. 53 S. 201133729 For example, 'a plurality of solder paste portions may be deposited on a plurality of solder pads and a cover respectively' and then a plurality of LED packages are respectively placed on the solder paste portions and then the solder paste portions are heated simultaneously It is re-welded, hardened and formed into a plurality of solder joints, after which the heat conducting plates are separated. In another example, a plurality of die-bonding materials are separately deposited on the plurality of caps' and then the multi-grain wafers are separately placed on the die-bonding materials, and then the die-bonding materials are simultaneously heated to harden them. A plurality of solid crystals are formed, and then the wafers are wire bonded to the corresponding pads, and then corresponding packaging materials are formed on the wafers and the wires, and finally the heat conducting plates are separated one by one. We can separate the heat conducting plates from each other in a single step or in multiple steps. For example, a plurality of heat conducting plates can be batched into a flat plate, and then a plurality of semiconductor elements can be placed on the flat plate, and then the plurality of semiconductor wafer assemblies formed by the flat plates can be separated one by one. Alternatively, a plurality of heat conducting plates can be batched into a flat plate, and then the plurality of heat conducting plates formed by the flat plate are slit into a plurality of heat conducting strips, and then a plurality of semiconductor elements are respectively disposed on the heat conducting strips. Finally, the plurality of semiconductor wafer assemblies formed by the heat conducting strips are separated into individual parts. In addition, mechanical cutting, laser cutting, bifurcation or other suitable techniques can be utilized when splitting the heat conducting plates. The term "adjacent" as used herein means that the elements are integrally formed (forming a single entity) or in contact with one another (with or without separation from one another). For example, the stud is adjacent to the pedestal, which is independent of the addition or reduction method when forming the stud. 「 The term "overlapping" means located above and extending within the periphery of a lower element. "Overlap" includes extending within, outside of, or within the perimeter of the perimeter 54 201133729. For example, the semiconductor element is heavy and is in the stud, because the semiconductor element and the stud are penetrated through the imaginary yoke 5, regardless of whether there is another imaginary vertical line between the semiconductor element and the stud. Throughout the element ^ as the cover) 'and whether or not there is another imaginary vertical line only through the semiconductor read without penetrating the stud (ie, outside the periphery of the stud). Similarly, the adhesive layer overlaps the pedestal and is overlapped by the solder fillet and the pedestal is overlapped by the stud. Due to the fact that the pillars are overlapped with the pedestal and are located in the periphery thereof. In addition, "overlap" is synonymous with "above" and "overlapping" is synonymous with "below". The term "contact" means direct contact. For example, the wire contacts the adhesive layer but does not contact the stud or the pedestal. The term "overlapping" means completely covering from above, from below and/or from the side. For example, the pedestal covers the stud from below, and (iv) the stud does not cover the pedestal from above. The layer includes a layer with or without a pattern. For example, when the conductive layer is disposed on the adhesive layer that has not been cured, the conductive layer may be a blank unpatterned flat panel. 'When the semiconductor component is disposed on the heat sink, the conductive layer may be cured. A circuit pattern having spaced wires on the adhesive layer. In addition, a "layer" may comprise a plurality of superposed layers. The term "pad" as used in connection with the conductor means a connection area for connecting and/or engaging an external connection medium (such as solder or wire), and the external connection medium electrically connects the wire to the Semiconductor component. The term "terminal" when used in conjunction with the conductor means a connection area that contacts and/or engages an externally bonded medium (such as solder or wire), and

S 55 201133729 The connecting medium can electrically connect the wire to your external device (such as a printed circuit board or a wire connected to it) connected to the next layer. The term "cover" when used in conjunction with the heat sink refers to a contact area for connecting and/or bonding an external connection medium (such as solder or a thermally conductive adhesive), and the external connection medium can heat the heat sink. Connected to the semiconductor component. The words "opening" and "through hole" refer to the through hole. For example, when the stud is inserted into the opening of the adhesive layer, the stud is exposed to the adhesive layer in an upward direction. Similarly, when the stud is inserted into the through hole of the conductive layer, the stud is exposed to the conductive layer in an upward direction. The term "insertion" means the relative movement between components. For example, "inserting the stud into the through hole" includes: the stud is fixed and moved by the conductive layer to the base, the conductive layer is fixed and moved by the stud to the conductive layer; Both the stud and the conductive layer abut each other. For another example, "inserting (or extending into) the through hole" includes: the through hole penetrates (passes through) the through hole, and the protrusion is inserted but not penetrated. Wear out) the through hole. The phrase "together with each other" also refers to the relative movement between components. For example, "the piano base and the conductive layer abut each other" includes: the base is fixed and moved by the conductive layer to the base; the conductive layer is fixed and moved by the base to the conductive layer; The pedestal and the conductive layer are close to each other. The term "aligned" means the relative position between components. For example, when the poison occupying layer is disposed on the pedestal, the conductive layer is disposed on the adhesive layer, the stud has been inserted and aligned with the opening, and the through hole has been aligned with the opening, 56 201133729 Whether the stud is inserted into the through hole or under the through hole and kept away from the through hole, the stud is aligned with the through hole. Placed in the "5" including contact and non-contact between the single or multiple support members. For example, the 兮 lane ^^ - μ J such as the conductor member is disposed on the heat sink, regardless of the semiconductor 7-piece system The F 4* a® is continuously extended to contact the heat sink or system, and is spaced apart from the heat sink by a solid crystal material. Similarly, the 7C conductor 7C is disposed on the heat sink, regardless of whether the semiconductor component is only one heavy, and is placed on the heat sink or on the heat sink. #层层... The term "in the middle of the gap" means the adhesive layer located in the gap. For example, "the adhesive layer extends across the conductive layer in the gap" means that the adhesive layer within the gap extends across the conductive layer. Similarly, "the adhesive layer is in contact between the gap and between the tab and the conductive layer" means that the adhesive layer in the gap contacts and refers to the inside wall of the notch. The stud is between the conductive layers of the outer sidewall of the notch. ^ Above" - semantically extends upwards and includes contiguous and non-contiguous elements and overlapping and non-overlapping elements. For example, the studs extend above the pedestal while adjoining, overlapping the pedestal and projecting therefrom. Similarly, the wire extends over the base even if the wire does not abut the base. The lower one is a downward extension and contains adjacent and non-contiguous elements as well as overlapping and non-overlapping elements. For example, if the pedestal extends below the stud and abuts the stud, it is overlapped by the protuberance of the larvae and protrudes from the stud. Similarly, the stud extends below the wire even if the stud is not adjacent to or overlapped by the wire. 57 201133729 The vertical direction of the two upwards and the downward direction is not dependent on the orientation of the semiconductor wafer package (or the heat conduction plate), and those skilled in the art can easily understand the direction in which they actually refer. For example, the stud column extends vertically above the pedestal in an upward direction, and the adhesive layer extends vertically below the pad in a downward direction, and whether the set is inverted and/or is disposed at - heat dissipation Not relevant on the device. Similarly, the pedestal extends laterally from the stud along the lateral plane regardless of whether the set is inverted, rotated or tilted. Thus, the upward and downward directions are opposite each other and perpendicular to the side direction, and further, the laterally aligned elements are coplanar with each other in a lateral plane perpendicular to the upward and downward directions. The semiconductor wafer package of the present invention has a number of advantages. The group can be leveled and very suitable for mass production. This group is especially suitable for high-power semiconductor components that are easy to generate south heat and require excellent heat dissipation to operate efficiently and reliably. 'Example #LED package, large semiconductor wafer, and multiple small semiconductor components used simultaneously (for example, in an array) Row-shaped multi-grazing small semiconductor wafer). The process of this case has a rain applicability and is unique and progressive.

The combination of various mature mines; fish gentleman -fe / I take 氕I electrical connection, thermal connection and mechanical connection technology. In addition, the manufacturing process of this case can be implemented without expensive tools. As a result, this manufacturing process significantly increases the yield, yield, performance and cost effectiveness of traditional packaging technologies. Furthermore, Taicha + 4 is a group suitable for environmental protection requirements for steel wafers and helmets. The present invention is not intended to be inconsistent with the invention. The embodiments described herein are exemplified by the teachings of the elements or the. Similarly, in order to clarify the drawings, the repeated or non-essential elements and reference numerals in the drawings may be omitted. Those skilled in the art will be able to readily appreciate various changes and modifications in the embodiments described herein. For example, the foregoing materials, dimensions, shapes, sizes, step contents, and order of steps are merely examples. The above-mentioned persons can make such changes, adjustments and equalizations without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1D are cross-sectional views illustrating a method for fabricating a stud and a pedestal in an embodiment of the present invention; and FIGS. 1E and 1F are top and bottom views of the first DD; 2A and 2B are cross-sectional views illustrating a method of fabricating an adhesive layer in accordance with an embodiment of the present invention; 2C and 2D views are a plan view and a bottom view of FIG. 2B; and FIGS. 3A to 3D are cross-sectional views illustrating the present invention. A method for fabricating a conductive layer in an embodiment; a top view and a bottom view of the 3D view; and a cross-sectional view of the fourth embodiment of the present invention, illustrating a method for fabricating a heat conductive plate according to an embodiment of the present invention; 4M and 4N are respectively a top view of the L4L mesh and a bottom view of the semiconductor chip group 5A, 5B, and 5C ® respectively, which are a cross-sectional view, a top view, and a bottom view of a wafer package in an embodiment of the present invention, the semiconductor crystal including the A heat conducting plate and an LED package having a back contact; 59 S: 201133729 曰 6A, 6B & 6C are respectively a cross-sectional view, a top view and a bottom view of a semiconductor device according to an embodiment of the present invention, Semiconductor wafer package 3, the heat conducting plate and a package having a side pin; 7A, 7B & 7C are respectively a cross-sectional view of a semiconductor wafer package in a top view and a bottom view of the semiconductor wafer package, The heat conducting plate and a semiconductor wafer; and FIGS. 8A, 8B, and 8C are respectively a different view, a top view, and a bottom view of a light source sub-group according to an embodiment of the present invention, the light source sub-group including the 5A to 5C The semiconductor chip assembly and a heat sink. 60 201133729 [Description of main component symbols] ίο.........metal plates 12, 14 · Surfaces 16, 32 · Patterned etching resist layers 34, 42 · Patterned etching resist layer 18 , 44 · · comprehensively covered etching resist layer 20 ... ... groove 22 ... ... ... ... ... ... ... ... ... ... ... ... ... 26 ... ...adhesive layer 28...the opening 30,40 ·the conductive layer 36...the through hole 38...the gap 46 .........pad 48.........route line 50.........terminal 52......cover 54... ... wire 56.........heatsink 58.........anti-weld green paint 60.........covered contact 62... ... heat conducting plate 100, 200 · semiconductor wafer package 300. • semiconductor wafer set 102, 202 · LED package 104 - • • first solder 106 - second solder 204 · · · " first Solder 206- "Second Solder 108, 208-LED Wafer 110, 210. · Dock 112, 212 •• Wire 114 · • Electrical Contact 116 • Hot Junction 118, 218 • Transparent Packaging Material 214. Pin 216, 404 .. Thermal contact surface 302 _ • 曰曰 306 • Solid day material 308 • Package material 310 • Top surface 312 • Bottom surface 314 • Wire bond pad 400 • Light source sub-assembly 402 • Heat sink 406 • Fin 61 201133729 Fan 408 62

Claims (1)

201133729 VII. Patent application scope: 1 _ A semiconductor wafer assembly comprising at least: a semiconductor component; an adhesive layer having at least one opening; a heat sink having at least one post and a base, wherein the bump a column system abuts the base and extends above the base in an upward direction, and the base extends below the protrusion 'in a downward direction opposite to the upward direction' and is perpendicular to the upward and downward directions a lateral direction of the direction extending laterally from the stud; and a wire comprising at least one pad and a terminal; wherein the semiconductor component is located above the stud and overlaps the stud, the semiconductor component is electrically connected To the solder pad, electrically connected to the terminal, and the semiconductor component is thermally coupled to the stud to be thermally coupled to the pedestal; ^ wherein the adhesive layer is disposed on the pedestal and extends to the base Above the seat, extending into a gap between the stud and the pad, and extending laterally from the stud to the terminal or over the terminal, and the adhesive layer is interposed between the base and the solder The solder pad is disposed on the adhesive layer and extends over the base; and wherein the protrusion extends into the opening, the base extends to the semiconductor component, the adhesive layer, and the bonding pad Below. 2. The semiconductor wafer package of claim 3, wherein the semiconductor component is an LED package comprising an LED chip. The semiconductor chip package according to the second aspect of the patent application, wherein the LED package (4) is electrically connected to the soldering pad by a first solder, and is thermally coupled to the heat sink by a second solder. seat. 4. The semiconductor wafer package according to the above-mentioned patent scope, wherein the semiconductor component is a semiconductor wafer. 5. The semiconductor wafer package of claim 4, wherein the wafer is electrically connected to the pad by a wire and thermally bonded to the heat sink by a solid material. 6. The semiconductor wafer package of claim 3, wherein the adhesive layer contacts the stud within the notch and contacts the pedestal, the pad and the terminal outside the notch. The semiconductor wafer package according to the above application, wherein the adhesive layer covers and surrounds the convex column in the lateral direction. 8. The semiconductor wafer package of claim 1, wherein the adhesive layer is isomorphically coated on a sidewall of the stud and the pedestal is located on a top surface of the stud. 9. The semiconductor wafer package of claim 1, wherein the adhesive layer fills a space between the pedestal and the wire. The semiconductor wafer package according to claim 1, wherein the adhesive layer extends laterally from the stud, passes over the terminal, and is overlapped by the terminal. 11. The semiconductor wafer package of claim 1, wherein the adhesive layer extends to a peripheral edge of the set. 12. The semiconductor wafer package of claim 1, wherein 64 201133729 the stud is integrally formed with the base. The μ-bump is a flat-topped tapered column whose diameter decreases upward from the pedestal to the flat top of one of the studs. The semiconductor wafer package according to the scope of the invention, wherein the pedestal covers the semiconductor element, the stud, the adhesive layer and the wire ′ from below and extends to the outer edge of the group. The semiconductor wafer package of claim 3, wherein the wire is spaced from the stud and the pedestal, the pad being in contact with the terminal and overlapping the adhesive layer. The semiconductor wafer package according to the invention of claim 2, wherein the heat sink comprises at least a cover, the cover is located above a top of one of the protrusions, abutting the top of the protrusion, and The top of the stud is covered above and extends. And the semiconductor wafer assembly according to claim 17 of the invention, wherein the β-cap and the pad and the terminal are above the adhesive layer A planar wafer body, wherein the thermal contact is in accordance with the semiconductor wafer assembly of claim 17, wherein the cover is rectangular or square, and the top of the stud is circular. 20. The semiconductor wafer set according to claim 17, wherein the size and shape of the cover are designed to match the surface of the semiconductor component 65 201133729, and the size and shape of the top of the stud is not compatible with the semiconductor The thermal contact surface of the component is designed. 21. A semiconductor wafer package comprising: at least: a semiconductor component; an adhesive layer having at least one opening; a heat sink having at least a stud and a pedestal, wherein the stud is adjacent to the pedestal Forming integrally with the base, and the stud extends above the base in an upward direction, the base extending below the stud in a downward direction opposite to the upward direction, and perpendicular to the upward direction And a side direction extending downward from the protruding column; and a wire comprising at least one pad, a terminal and a routing line, wherein a conductive path between the pad and the terminal comprises the routing line; The semiconductor component is disposed on the heat sink, overlaps the bump, and is electrically connected to the solder pad to be electrically connected to the terminal, and the semiconductor component is thermally coupled to the bump to thermally connect The susceptor is disposed on the susceptor i, extends over the pedestal, extends into a gap between the stud and the squeegee, and the adhesive layer is outside the π Between The adhesive layer between the base and the wire surrounds the protrusion in the lateral direction and extends to the peripheral edge of the group; wherein the wire 5 is placed on the adhesive layer and extends above the base And the pad, the terminal is in contact with the routing line and overlying the adhesive layer; and 66 201133729 wherein the stud extends into the opening, the pedestal extending over the semiconductor component, the adhesive layer and the wire, and The stud is covered from below, the adhesive layer and the wire 'extend to the peripheral edge of the set. The semiconductor wafer package according to claim 21, wherein the semiconductor component is an LED package including an LED chip, and the first solder is disposed on the bonding pad, and a second is utilized. Solder is disposed on the heat sink. The semiconductor device is electrically connected to the pad by the first solder, and is thermally coupled to the heat sink by the second solder. The semiconductor wafer package according to claim 21, wherein the adhesive layer contacts the stud in the notch, and contacts the pedestal, the pad, the terminal and the outside of the notch a routing line, the adhesive layer covering and surrounding the protruding column, covering the wire from below, and covering the base from a part of the protruding column from above, while filling the space between the base and the wire A space. 24. The semiconductor wafer package according to claim 21, wherein the stud is a flat-topped tapered column having a diameter that decreases upward from the pedestal to a flat top of the stud. The top of the column is circular, and a cover system is disposed on the top of the stud, above the top of the stud, adjoining the top of the stud and covering the top of the stud from above. (^ at the same time extending from the top side of the stud in the lateral direction, the sigma body is rectangular or square. 25. According to the semiconductor wafer assembly according to Item 21 of the application (4), wherein the convex The pillar and the adhesive layer are coplanar above the bottom of the wire, and the pad and the terminal are coplanar above the adhesive layer.