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TW201118995A - Metal layer structure for flip-chip semiconductor package - Google Patents

Metal layer structure for flip-chip semiconductor package Download PDF

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Publication number
TW201118995A
TW201118995A TW098139108A TW98139108A TW201118995A TW 201118995 A TW201118995 A TW 201118995A TW 098139108 A TW098139108 A TW 098139108A TW 98139108 A TW98139108 A TW 98139108A TW 201118995 A TW201118995 A TW 201118995A
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TW
Taiwan
Prior art keywords
metal layer
metal
under
layer
layer structure
Prior art date
Application number
TW098139108A
Other languages
Chinese (zh)
Inventor
feng-cheng Dai
Ji-Yang You
zheng-gong Du
Original Assignee
Nat Univ Tsing Hua
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Application filed by Nat Univ Tsing Hua filed Critical Nat Univ Tsing Hua
Priority to TW098139108A priority Critical patent/TW201118995A/en
Publication of TW201118995A publication Critical patent/TW201118995A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to a metal layer structure for flip-chip semiconductor package, including an under-ball metal layer formed on a metal pad, which is to assist the metal pad to form a high quality tin-based solder. The under-ball metal layer, in order to select Nickel-zinc-Phosphate coating, by means of the mixed solutions of Nickel sulfate (NiSO4), Zinc sulfate (ZnSO4), Sodium hypophosphite (NaH2PO2), Sodium citrate dihydrate (Na3C6H5O7-2H2O) and Ammonium chloride (NH4Cl), is created by oxidation-reduction reactions. Accordingly, it is appropriate to replace the conventional double layer structure of Au/Ni-P plating to reduce process complexity and costs. Also, the metal layer structure of the present invention, toughness can be achieved, difficult to peel, and has good corrosion resistance.

Description

201118995 六、發明說明： 【發明所屬之技術領域】 [0001] 本案係有關覆晶封骏的結構，尤指覆晶封裝中的球下 金屬層的結構。 [0002] C先前技術] 電子封裝技術中，第一層級的封裝是將晶片（chip)連 結到承載板上’其具有三種封裝型態，分別為打線技術 (wire bonding)、貼帶自動接合技術（tape automat_ ❹ ic bonding，TAB)、覆晶接合技術（flip chip, F/ C)。 [0003] 由於打線技術製程所需的時吋較長，於是成為打線接 合技術的最大瓶頸，且打線接合或捲帶式自動接合技術 (TAB) ’其封裝後的電子元件體積較大’與現今追求輕薄 短小電子產品的目標相左，因此便發展出覆晶接合技術 (F/C) 〇 [0004] 〇 關於覆晶技術（F/C)的發展，著眼於需要使用高腳數 (I/O)特性、散熱性較佳或較為輕薄短小的封裝技術，且 由於覆晶接合技術比習知打線結合技術大幅縮短接線長 度’其有助於電子訊號傳遞速度與提升，因此逐漸形成 高密度封裝主流》 [0005] 請參閲「圖1」所示，為習知電子元件結構示意圖， 其於一晶片1配置有複數個金屬整2，該金屬塾2 —般為銘 墊或銅墊，並於一基板3上設置有複數個接點4，並以複 數個錫基銲球5設置於該金屬墊2與該接點4之間，對該晶 098139108 片1與该基板3間形成連結，由該晶片1依序藉該金屬塾2 表單編號A0101 第3頁/共12買 0982067134-0 201118995 [0006] 該錫基鈐球5、該接點4產生電性連結到該基板3，另外 為避免濕氣與機械應力的破壞，可設置—底膠層6於該 晶片1與該基板3之間。 如上所述結構的製裡，其為先在該金屬塾2上形成該 錫基銲球5，再倒轉讓該錫基銲球5與該接點4連結，因此 該金屬墊2上形成該鎮基鲜球5的品質好壞，直接影響了 封裝的良率。 [0007] 凊再參閱「圖2」所示，為了於該金屬墊2形成該錫基 銲球5，該晶片1上的該金屬墊2上會先鍍上多層金屬薄膜 ，一般稱之為球下金屬層7(under_bump metal 1iza- tion ·’ UBM)，球下金屬層7通常包含三層金屬，其為黏 附層 8(Adhesi〇n layer)、潤濕層 9(WeUing Uyer) 與保護層HKProtective Layer)，其中黏附層201118995 VI. Description of the Invention: [Technical Field to Be Invented by the Invention] [0001] The present invention relates to a structure of a flip chip seal, and more particularly to a structure of a sub-spherical metal layer in a flip chip package. [0002] Prior to the prior art] In the electronic packaging technology, the first level of packaging is to connect a chip to a carrier board. It has three package types, namely wire bonding and tape bonding. (tape automat_ ❹ ic bonding, TAB), flip chip (F/C). [0003] Due to the long time required for the wire bonding process, it has become the biggest bottleneck of the wire bonding technology, and the wire bonding or tape automated bonding technology (TAB) 'the packaged electronic components are larger' and nowadays The goal of pursuing thin and light electronic products is different, so the development of flip chip bonding technology (F/C) 〇[0004] 〇About the development of flip chip technology (F/C), focusing on the need to use high number of pins (I/O) ) The package technology with better characteristics, better heat dissipation or lighter and shorter, and because the flip chip bonding technology greatly shortens the wiring length than the conventional wire bonding technology, which contributes to the speed and improvement of electronic signal transmission, and thus gradually forms a mainstream of high-density packaging. [0005] Please refer to FIG. 1 for a schematic diagram of a conventional electronic component. The wafer 1 is provided with a plurality of metal strips 2, which are generally indicia or copper pads. A plurality of contacts 4 are disposed on a substrate 3, and a plurality of tin-based solder balls 5 are disposed between the metal pads 2 and the contacts 4 to form a connection between the wafers 098139108 and the substrate 3. The wafer 1 borrows the gold in sequence塾 2 Form No. A0101 Page 3 / Total 12 Buy 0982067134-0 201118995 [0006] The tin-based ball 5, the contact 4 is electrically connected to the substrate 3, and in order to avoid damage of moisture and mechanical stress, A primer layer 6 can be disposed between the wafer 1 and the substrate 3. In the structure of the above structure, the tin-based solder ball 5 is formed on the metal crucible 2, and the tin-based solder ball 5 is transferred to the joint 4, so that the metal pad 2 is formed on the metal pad 2 The quality of the base fresh ball 5 directly affects the yield of the package. [0007] Referring to FIG. 2 again, in order to form the tin-based solder ball 5 on the metal pad 2, the metal pad 2 on the wafer 1 is first plated with a plurality of metal films, generally referred to as balls. The under-metal layer 7 (under-bump metal 1 ' UBM), the under-ball metal layer 7 usually comprises three layers of metal, which are an adhesion layer 8 , a wetting layer 9 (WeUing Uyer) and a protective layer HKProtective Layer), where the adhesion layer

^Adhesion layer)，如鈦（Ti)、鉻(Cr)、鈦鎢（TiW) 、鋅（Zn)等金屬擇- ’主要目的在於提供金屬塾⑽潤濕、 層9有較強之黏著性，因此黏附層8可以依據材料的特性 選擇是否需要。而潤濕層9，如鑷(Ni)、_(Ni-p)、^Adhesion layer), such as titanium (Ti), chromium (Cr), titanium tungsten (TiW), zinc (Zn) and other metal selection - 'the main purpose is to provide metal tantalum (10) wetting, layer 9 has strong adhesion, Therefore, the adhesive layer 8 can be selected depending on the characteristics of the material. And the wetting layer 9, such as niobium (Ni), _ (Ni-p),

銅（㈤等，此類金屬與該錫基鲜球5的鲜锡之潤濕程度較 高，在迴焊⑽flQW)時鐸錫可完全滯留附立其上而成球 狀，保護層 10(Protective Layei*)， 的金屬’此類金屬較鈍性（passive) 層7氧化。 則如金等電阻低 ’可避免球下金屬 [0008] 098139108 ^知的球下金屬層7,為使用鍍金製程來形成該保護 層10，然鍍金製程所使用的材料與今 竹興。又備卬貴，且鍍金薄 膜不容易完美附著與增厚，因«碎且，㈣ 表單編號A0101 ® i右，·· 一 第4頁/共12頁 0982067134-0 201118995 金製程已成為覆晶封裝製程中，降低成本的最大瓶頸。 【發明内容】 [0009] [0010] ❹ [0011] [0012] 〇 [0013] 本發明之主要目的在於揭露一種製造容易、低成本、 具韌性、且不易剝離並具良好的抗腐蝕性的球下金屬層 〇 為了達到上述目的，本發明為一種用於覆晶封裝的金 屬層結構，其包含一球下金屬層，其中該球下金屬層設 於一金屬墊上，且該球下金屬層為鎳鋅磷鍍層，以幫助 該金屬墊上形成品質良好的一錫基銲球。 據此，本發明的球下金屬層為由鎳鋅磷鍍層形成，其 只需單一層結構，因此相較習知技術使用的金/鎳-磷（Au /Ni-P)鍍層的雙層結構而言，其製造程序簡單、成本低 廉，且不易碎且不容易剝離。 【實施方式】 茲有關本發明的詳細内容及技術說明，現以實施例來 作進一步說明，但應暸解的是，該等實施例僅為例示說 明之用，而不應被解釋為本發明實施之限制。 請參閱「圖3」所示，本發明為一種用於覆晶封裝的 金屬層結構，形成於一金屬墊20上，該金屬墊20為設置 在一晶片30上，並具有一鈍態保護層80保護該晶片30， 並讓該金屬墊20顯露出來，且該金屬墊20可以為鋁墊或 是銅塾等常作為金屬接點的金屬。本發明包令—球下金 屬層50，其中該球下金屬層50設於該金屬墊20上，且該 球下金屬層50為鎳鋅磷鍍層。 098139108 表單編號A0101 第5頁/共12頁 0982067134-0 201118995 [0014] [0015] [0016] 又該球下金屬層50可以為藉硫酸鎳（NiS〇4)、硫酸鋅 (ZnS〇4)、亞磷酸二氫鈉（NaH2P〇2)、檸檬酸鈉-二結晶 水與氣化銨（NH/Cl)的混合水溶液， dbb/ L 4 經氧化還原反應而形成該鎳鋅磷鍍層。且上述混合水溶 液中，其適當的比例為，該硫酸鎳（NiSO,)、硫酸鋅 4 (ZnS〇4)、亞磷酸二氫納（NaH2P〇2)、擰檬酸鈉-二結晶 水2H90)與氣化銨（NH/1)的混合水溶液的 Ο Ό D ( L 4 每公升克數（g/L)為40、3、11 ' 60與80。 請參閱「圖4」所示，為本發明的另一實施例，本發 明的金屬層結構亦可包含黏附層40與球下金屬層50，其 中於本實施例中，該黏附層40設於該金屬墊20上，該球 下金屬層50設於該黏附層40上，並藉該黏附層40與該金 屬墊20結合，且該球下金屬層50為鎳辞磷鍍層，據而可 藉由黏附層40的黏力增加該球下金屬層50與該金屬墊20 結合的穩定性。 請參閱「圖5」所示，本發明藉由上述混合水溶液經 氧化還原反應形成該球下金屬層50，該球下金屬層50為 鎳鋅磷鍍層，且為1鎳-8鋅-8磷的組成，其可幫助於該金 屬墊20上形成品質良好的一錫基銲球70，其再與常用之 無錯銲錫合金，即SAC305 (Sn-3. 0 wt. %Ag-0. 5 wt. %Cu)接合之後，其顯微鏡像圖如「圖5」所示，其晶 片30上所形成的錫基銲球70具良好的品質，其供覆晶封 裝使用，可以滿足使用者的需求。 如上所述，本發明揭露一種用於覆晶封裝的金屬層結 構，其免除習知金/錄-磷·鏟層的使用，因此可免除使用 098139108 表單編號A0101 第6頁/共12頁 0982067134-0 [0017] 201118995 鍍金設備與金材料，故可大大的降低製造成本，又其鎳 鋅磷鍍層相較金鍍層而言，其不易碎且不容易剝離，亦 具良好的抗腐蝕性，且本發明僅需一道鍍膜程序，其製 程簡單，更可進一步降低製造成本，同時提高產量滿足 所需。 [0018] 惟上述僅為本發明之較佳實施例而已，並非用來限定 本發明實施之範圍。即凡依本發明申請專利範圍所做的 均等變化與修飾，皆為本發明專利範圍所涵蓋。 〇 【圖式簡單說明】 [0019] 圖1，為習知電子元件結構示意圖。 [0020] 圖2，為習知球下金屬層斷面結構圖。 [0021] 圖3，為本發明斷面結構圖。 [0022] 圖4，為本發明另一實施例的斷面結構圖。 [0023] 圖5，為本發明球下金屬層與錫基銲球的顯微鏡像圖。Copper ((5), etc., such metal has a higher degree of wetting with the tin of the tin-based fresh ball 5, and in the reflow (10) flQW), the tin-tin can be completely retained and attached to the spherical shape, and the protective layer 10 (Protective) Layei*), the metal of this type is oxidized by a passive layer 7 of this type. Then, if the resistance such as gold is low, the metal under the ball can be avoided [0008] 098139108 ^ The under-metal layer 7 of the ball is formed by using a gold plating process to form the protective layer 10, and the material used in the gold plating process is today. It is also expensive, and the gold-plated film is not easy to adhere and thicken perfectly, because «breaking, (4) Form No. A0101 ® i Right, · · · Page 4 / Total 12 pages 0992067134-0 201118995 Gold process has become flip chip package The biggest bottleneck in reducing costs in the process. [0010] [0012] [0013] The main object of the present invention is to disclose a ball that is easy to manufacture, low in cost, tough, and not easily peeled off and has good corrosion resistance. In order to achieve the above object, the present invention is a metal layer structure for flip chip packaging, comprising a sub-spherical metal layer, wherein the under-metal layer is disposed on a metal pad, and the under-metal layer is A nickel-zinc-phosphorus coating is applied to help form a good tin-based solder ball on the metal pad. Accordingly, the under-spherical metal layer of the present invention is formed of a nickel-zinc-phosphorus plating layer, which requires only a single layer structure, and thus has a two-layer structure of a gold/nickel-phosphorus (Au/Ni-P) plating layer which is used in comparison with the prior art. In terms of its simplicity, its manufacturing process is low, it is not fragile and it is not easy to peel off. The detailed description of the present invention and the technical description thereof will be further described by way of examples, but it should be understood that these embodiments are for illustrative purposes only and should not be construed as The limit. Referring to FIG. 3, the present invention is a metal layer structure for a flip chip package formed on a metal pad 20 disposed on a wafer 30 and having a passive protective layer. 80 protects the wafer 30 and exposes the metal pad 20, and the metal pad 20 may be an aluminum pad or a metal such as a copper wire which is often used as a metal contact. The present invention includes a sub-spherical metal layer 50, wherein the under-ball metal layer 50 is disposed on the metal pad 20, and the under-ball metal layer 50 is a nickel-zinc-phosphorus plating layer. 098139108 Form No. A0101 Page 5 of 12 0982067134-0 201118995 [0015] [0016] Further, the under-ball metal layer 50 may be nickel sulfate (NiS〇4), zinc sulfate (ZnS〇4), A mixed aqueous solution of sodium dihydrogen phosphate (NaH2P〇2), sodium citrate-dicrystallized water and ammonium sulfate (NH/Cl), and dbb/L 4 is subjected to a redox reaction to form the nickel-zinc-phosphorus plating layer. And in the above mixed aqueous solution, the appropriate ratio is the nickel sulfate (NiSO,), zinc sulfate 4 (ZnS〇4), sodium dihydrogen phosphate (NaH2P〇2), sodium citrate-dicrystal water 2H90) Ο Ό D (L 4 per liter of gram (g/L) is 40, 3, 11 '60 and 80 in a mixed aqueous solution of ammonium hydride (NH/1). Please refer to Figure 4 for In another embodiment of the invention, the metal layer structure of the present invention may further include an adhesion layer 40 and a sub-spherical metal layer 50. In this embodiment, the adhesion layer 40 is disposed on the metal pad 20, and the under-metal layer 50 is disposed on the adhesive layer 40, and is bonded to the metal pad 20 by the adhesive layer 40, and the under-metal layer 50 is a nickel-phosphorus plating layer, and the adhesive layer 40 can be increased by the adhesion of the adhesive layer 40. The stability of the metal layer 50 in combination with the metal pad 20. Referring to FIG. 5, the present invention forms the under-ball metal layer 50 by the redox reaction of the mixed aqueous solution, and the under-metal layer 50 is nickel-zinc. Phosphorus plating layer, and is composed of 1 nickel-8 zinc-8 phosphorus, which can help to form a good tin-based solder ball 70 on the metal pad 20, which is commonly used After the solder joint of the wrong solder alloy, SAC305 (Sn-3. 0 wt. %Ag-0. 5 wt. %Cu), the microscope image is as shown in FIG. 5, and the tin-based solder formed on the wafer 30 is formed. The ball 70 has good quality and is used for flip chip packaging to meet the needs of users. As described above, the present invention discloses a metal layer structure for flip chip packaging, which is free of conventional gold/record-phosphorus shovel. The use of layers can therefore be dispensed with using 098139108 Form No. A0101 Page 6 / Total 12 Page 0982067134-0 [0017] 201118995 Gold-plated equipment and gold material, which can greatly reduce the manufacturing cost, and its nickel-zinc-phosphorus coating is compared with gold plating In fact, it is not brittle and is not easy to peel off, and has good corrosion resistance, and the invention only needs one coating process, and the manufacturing process is simple, and the manufacturing cost can be further reduced, and the output can be improved to meet the requirements. [0018] The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. All changes and modifications made by the scope of the present invention are covered by the scope of the present invention. Simple description 1 is a schematic structural view of a conventional electronic component. [0020] FIG. 2 is a cross-sectional structural view of a conventional under-metal layer. [0021] FIG. 3 is a cross-sectional structural view of the present invention. [0022] FIG. A cross-sectional structural view of another embodiment of the present invention. [0023] FIG. 5 is a microscopic image of a lower metal layer and a tin-based solder ball of the present invention.

【主要元件符號說明】 [0024] 習知 [0025] 1 ·晶片 [0026] 2 :金屬墊 [0027] 3 :基板 [0028] 4 :接點 [0029] 5 :錫基鲜球 [0030] 6 :底膠層 098139108 表單編號A0101 第7頁/共12頁 0982067134-0 201118995 [0031] 7 :球下金屬層[Explanation of main component symbols] [0024] Conventional [0025] 1 wafer [0026] 2: metal pad [0027] 3: substrate [0028] 4: contact [0029] 5: tin-based fresh ball [0030] 6 : underlayer 098139108 Form No. A0101 Page 7 / Total 12 Page 0992067134-0 201118995 [0031] 7 : Under the metal layer

[0032] 8 ： 黏附層 [0033] 9 ： 潤濕層 [0034] 10 :保護層 [0035] 本發明 [0036] 20 :金屬墊 [0037] 30 •晶片 [0038] 40 :黏附層 [0039] 50 :球下金屬層 [0040] 70 :錫基焊球 [0041] 80 :鈍態保護層 098139108 表單編號A0101 第8頁/共12頁8 : Adhesive layer [0033] 9 : Wetting layer [0034] 10 : Protective layer [0035] The present invention [0036] 20: Metal pad [0037] 30 • Wafer [0038] 40: Adhesive layer [0039] 50: under-ball metal layer [0040] 70: tin-based solder ball [0041] 80: passive protective layer 098139108 Form No. A0101 Page 8 of 12

0982067134-00982067134-0

Claims (1)

201118995 七、申請專利範圍： . 1 . 一種用於覆晶封裝的金屬層結構，形成於一金屬墊上，該 金屬墊為設置在一晶片上，並具有一鈍態保護層保護該晶 片，並讓該金屬塾顯露出來，其包含： 一球下金屬層，該球下金屬層設於該金屬塾上，且該球下 金屬層為鎳鋅磷鍍層。 2 .如申請專利範圍第1項所述之用於覆晶封裝的金屬層結構 ，其中該球下金屬層為藉硫酸鎳（NiS04)、硫酸鋅 (ZnS04)、亞磷酸二氫鈉（NaH2P02)、檸檬酸鈉-二結晶 〇 水（Na3C6H507-2H20)與氯化銨（NH4C1)的混合水溶液， 經氧化還原反應而形成鎳鋅磷鍍層。 3 .如申請專利範圍第2項所述之用於覆晶封裝的金屬層結構 ，其中該硫酸鎳（NiS04)、硫酸鋅（ZnS04)、亞磷酸二氫 鈉（NaH2P02)、檸檬酸鈉-二結晶水（Na3C6H507-2H20) 與氣化銨（NH4C1)的混合水溶液的每公升克數（g/L)為40 ' 3、11、60與80 ° ^ 4 .如申請專利範圍第1項所述之用於覆晶封裝的金屬層結構 ，其中更包含一黏附層，該黏附層設於該金屬墊上，且該 球下金屬層設於該黏附層上，並藉該黏附層與該金屬墊結 合0 5 .如申請專利範圍第1項所述之用於覆晶封裝的金屬層結構 ，其中該金屬墊為選自鋁墊與銅墊的任一種。 6 .如申請專利範圍第1項所述之用於覆晶封裝的金屬層結構 ，其中該球下金屬層的鎳鋅磷鍍層為1鎳-8鋅-8磷。 098139108 表單編號A0101 第9頁/共12頁 0982067134-0201118995 VII. Patent application scope: 1. A metal layer structure for flip chip packaging, formed on a metal pad, which is disposed on a wafer and has a passive protective layer to protect the wafer and allows The metal ruthenium is exposed, comprising: a ball under metal layer, the under-metal layer is disposed on the metal ruthenium, and the under-ball metal layer is a nickel-zinc-phosphorus plated layer. 2. The metal layer structure for flip chip packaging according to claim 1, wherein the under-metal layer is nickel sulfate (NiS04), zinc sulfate (ZnS04), sodium dihydrogen phosphate (NaH2P02). A mixed aqueous solution of sodium citrate-dicrystal water (Na3C6H507-2H20) and ammonium chloride (NH4C1) is subjected to a redox reaction to form a nickel-zinc-phosphorus plating layer. 3. The metal layer structure for flip chip packaging according to claim 2, wherein the nickel sulfate (NiS04), zinc sulfate (ZnS04), sodium dihydrogen phosphate (NaH2P02), sodium citrate-two The number of grams per liter (g/L) of the mixed aqueous solution of crystal water (Na3C6H507-2H20) and vaporized ammonium (NH4C1) is 40 '3, 11, 60 and 80 ° ^ 4 as described in claim 1 The metal layer structure for the flip chip package further includes an adhesion layer disposed on the metal pad, and the under-metal layer is disposed on the adhesion layer, and the adhesion layer is combined with the metal pad The metal layer structure for flip chip packaging according to claim 1, wherein the metal pad is any one selected from the group consisting of an aluminum pad and a copper pad. 6. The metal layer structure for flip chip packaging according to claim 1, wherein the nickel-zinc-phosphorus plating layer of the under-metal layer is 1 nickel-8 zinc-8 phosphorus. 098139108 Form No. A0101 Page 9 of 12 0982067134-0
TW098139108A 2009-11-18 2009-11-18 Metal layer structure for flip-chip semiconductor package TW201118995A (en)

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