201039451 六、發明說明： 【發明所蜃之技術領域】 本發明是有關於一種太陽能電池面板結構，且特別是 有關於一種具未貫穿凹穴的太陽能電池面板結構。 【先前技術】 目前傳統的太陽能電池通常具有下列程序：（1 )拉晶 程序’其主要的原料為二氧化矽，利用晶種在拉晶爐中成 〇 長出一單晶石夕碇(Ing〇t) ; (2)修角程序，一般微電子產業 所用的晶圓（wafer)，是直接把單晶石夕碗進行切片，但對於 太陽能電池而言，通常必須把許多晶片串聯成一方形陣 列，為了使方形陣列排列的更緊密，大部分都先將單晶矽 碇修角成四方形；（3)切片程序，用切片機（slider)將單 晶矽碇切成厚度約0.5毫米的晶圓；（4 )蝕刻及拋光程序， 蝕刻的目的是去除切片製程中所造成的應力層（strained layer) ’而拋光的目的是要降低微粒(partide)附著在晶圓上 Ο 的了月b陡’（5 ).》月洗程序’用去離子水(DI water)把晶圓表 面的雜質污染物去除；（6)擴散程序（見第1圖所示），一 般太陽電池均採用p型的基板，利用高溫熱擴散的處理， 使P型的基板上形成一層薄薄的η型半導體。在進行擴散 程序刖’會將表面製成粗糙化的組織(Texturing)結構；（7) 牙J用電浆辅助化學》儿積（Plasma Enhanced Chemical Vapor Deposition，PECVD)加入抗反射層，以減少光的反射量； (8)網印程序，將製作完成的晶圓，塗佈上銀（Ag)膠 . 及鋁(A1)膠’以一網印機依據一網板（silk)將一種預設圖 4 201039451 形印刷在晶圓的兩面；（9)共同燒結程序，將印 及紹膠之晶®，共同通過高溫燒賴，使得鄉及^ 分別與晶圓之聽、面產生共晶結構結構，而與晶圓因此呈 有-定之歐姆接觸（ohmic contact) ;(10)邊緣隔離程序: 利用雷射技術或電漿蝕刻技術將晶圓邊緣進行絕緣處理。 如此，便可於晶圓之表面接出導電電極，如此即可6二 個簡單的太陽電池面板。 70风 然而，由於太陽電池面板對於藍光響應效果的好壞， 直接影響太陽電池面板之使用效率，加上太陽電池面板之 向光面可接收入射光的短波長之深度相當有限，使得加強 太陽電池面板之使用效率上，仍具有許多改善的空間，如 此’便成為業界亟欲改良的課題。 【發明内容】 有鑑於此，本發明之一目的在提供一種太陽能電池面 板結構，藉此增加面板接收入射光之面積、縮短載子移動 Q 至摻雜層的距離以及增加可收集到之載子，進而提高太陽 電池面板之使用效率’尤其是針對入射光之短波長對於藍 光響應的效果。 本發明之另一目的在提供一種具有多個未貫穿凹穴 的太陽能電池面板結構，藉以維持面板結構之強度，降低 面板產生斷裂的機率。 根據本發明之上述目的，提出一種太陽能電池面板結 構，包括一半導體晶圓基板、一摻雜層、一抗反射層及 201039451 一第一電極層。半導體晶圓基板具有相互對應之向光面 ' 及背光面，其中至少向光面及背光面其中之一具有多個 未貫穿的凹穴，此些凹穴之深度不及半導體晶圓基板厚 度之一半。掺雜層至少布滿向光面之表面。抗反射層位 於摻雜層之表面。第一電極層掺雜層相互產生共晶接 構。第二電極層與第一電極層呈相反極性，且第二電極 層位於背光面之一侧。 以下提供多個實施例，以進一步闡明本案之技術特徵。 本發明之一第一實施例中，此些凹穴位於半導體晶圓 Ο 基板之向光面上。摻雜層布滿向光面表面及此些凹穴的 内壁表面。第一電極層伸入其中一凹穴中，並與其内壁 表面之摻雜層產生一共晶結構，第一電極層之另端顯露 於抗反射層之表面。第二電極層是位於半導體晶圓基板 之背光面表面，並與半導體晶圓基板產生一共晶結構。 本發明之一第二實施例中，此些凹穴位於半導體晶 圓基板之背光面上。第二電極層位於半導體晶圓基板之 背光面及凹穴内壁表面，並與半導體晶圓基板產生一共 ^ 晶結構。第一電極層之一端於抗反射層中與摻雜層產生 一共晶結構，另端並顯露於抗反射層之表面。 本發明之一第三實施例中，此些凹穴位於半導體晶 圓基板之向光面上，且摻雜層位於半導體晶圓基板之向 光面表面及此些凹穴的内壁表面。第一電極層伸入其中 一凹穴中，並與其内壁表面之摻雜層產生一共晶結構， . 第一電極層之另端顯露於抗反射層之表面。此外，太陽 能電池面板結構更具有多個未貫穿之另一凹穴，此些另 6 201039451 一凹穴位於半導體晶圓基板之背光面，其深度不及半導 體晶圓基板厚度之一半。第二電極層位於背光面之表面 及另一凹穴内部之内壁表面，並與半導體晶圓基板產生 一共晶結構。 本發明之一第四實施例中，此些凹穴位於半導體晶圓 基板之向光面上，且丰導體晶圓基板上更具有至少一接 通半導體晶圓基板之向光面及背光面的貫穿孔。而掺雜 層位於半導體晶圓基板之表面、凹穴内部之内壁表面及 _ 貫穿孔的内壁表面。上述之第一電極層位於半導體晶圓201039451 VI. Description of the Invention: [Technical Field] The present invention relates to a solar cell panel structure, and more particularly to a solar cell panel structure having a through-hole. [Prior Art] At present, the conventional solar cell usually has the following procedures: (1) The crystal pulling process 'the main raw material is cerium oxide, and a single crystal stone 〇 〇 (Ing) is grown in the crystal pulling furnace by using the seed crystal. 〇t) ; (2) The cornering procedure, the wafer used in the general microelectronics industry, is to directly slice the single crystal stone bowl, but for solar cells, it is usually necessary to connect many wafers in series to form a square array. In order to make the square arrays more closely arranged, most of them are first trimmed into squares; (3) slicing procedure, using a slicer to cut single crystal crucible into crystals having a thickness of about 0.5 mm. Circle; (4) etching and polishing procedures, the purpose of etching is to remove the strained layer caused by the slicing process' and the purpose of polishing is to reduce the adhesion of the partide to the wafer. '(5).》月洗程序' uses DI water to remove impurity contaminants on the wafer surface; (6) diffusion procedure (see Figure 1), general solar cells are p-type Substrate, using high temperature thermal diffusion treatment, A thin n-type semiconductor is formed on the P-type substrate. In the diffusion process, the surface is made into a roughened texturing structure; (7) Plasma Enhanced Chemical Vapor Deposition (PECVD) is added to the antireflection layer to reduce light. The amount of reflection; (8) screen printing process, the finished wafer will be coated with silver (Ag) glue. And aluminum (A1) glue will be a preset according to a screen printing machine. Figure 4 201039451 is printed on both sides of the wafer; (9) co-sintering process, printing and smelting of the crystals of the slag, together through the high temperature burn, so that the township and ^ respectively and the wafer hearing, surface eutectic structure Therefore, there is a ohmic contact with the wafer; (10) Edge isolation procedure: The edge of the wafer is insulated by laser technology or plasma etching technology. In this way, the conductive electrodes can be connected to the surface of the wafer, so that six simple solar cell panels can be used. 70 wind However, due to the good response of the solar panel to the blue light, it directly affects the efficiency of the solar panel, and the depth of the short wavelength of the solar panel that can receive the incident light is quite limited, so that the solar cell is strengthened. The use efficiency of the panel still has a lot of room for improvement, which has become an issue that the industry is eager to improve. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a solar cell panel structure, thereby increasing the area in which the panel receives incident light, shortening the distance of the carrier from moving Q to the doped layer, and increasing the collectable carrier. In turn, the efficiency of use of the solar cell panel is improved, especially for the short-wavelength of incident light for the blue light response. Another object of the present invention is to provide a solar cell panel structure having a plurality of non-penetrating recesses for maintaining the strength of the panel structure and reducing the probability of panel breakage. In accordance with the above objects of the present invention, a solar cell panel structure is provided comprising a semiconductor wafer substrate, a doped layer, an anti-reflective layer, and a 201039451 first electrode layer. The semiconductor wafer substrate has mutually corresponding illuminating surfaces and a backlight surface, wherein at least one of the light surface and the backlight surface has a plurality of non-penetrating recesses, the depth of the recesses being less than one half of the thickness of the semiconductor wafer substrate . The doped layer is at least covered with the surface of the incident surface. The antireflection layer is on the surface of the doped layer. The doped layers of the first electrode layer each have a eutectic structure. The second electrode layer is opposite in polarity to the first electrode layer, and the second electrode layer is on one side of the backlight surface. A number of embodiments are provided below to further clarify the technical features of the present invention. In a first embodiment of the invention, the recesses are located on the light-facing side of the semiconductor wafer Ο substrate. The doped layer is covered with the smooth surface and the inner wall surface of the recesses. The first electrode layer extends into one of the recesses and forms a eutectic structure with the doped layer of the inner wall surface, and the other end of the first electrode layer is exposed on the surface of the antireflection layer. The second electrode layer is located on the surface of the backlight of the semiconductor wafer substrate and generates a eutectic structure with the semiconductor wafer substrate. In a second embodiment of the invention, the recesses are located on the back side of the semiconductor wafer substrate. The second electrode layer is located on the backlight surface of the semiconductor wafer substrate and the inner wall surface of the recess, and generates a eutectic structure with the semiconductor wafer substrate. One end of the first electrode layer forms a eutectic structure with the doped layer in the anti-reflective layer, and is terminated at the other end and exposed on the surface of the anti-reflective layer. In a third embodiment of the present invention, the recesses are located on the light-facing surface of the semiconductor wafer substrate, and the doped layer is located on the surface of the semiconductor wafer substrate and the inner wall surface of the recesses. The first electrode layer extends into one of the recesses and forms a eutectic structure with the doped layer on the inner wall surface. The other end of the first electrode layer is exposed on the surface of the antireflection layer. In addition, the solar cell panel structure has a plurality of other recesses that are not penetrating, and the other 6 201039451 recess is located on the backlight surface of the semiconductor wafer substrate, and the depth is less than one-half the thickness of the semiconductor wafer substrate. The second electrode layer is located on the surface of the backlight surface and the inner wall surface of the other of the recesses, and generates a eutectic structure with the semiconductor wafer substrate. In a fourth embodiment of the present invention, the recesses are located on the light-facing surface of the semiconductor wafer substrate, and the conductive conductor wafer substrate further has at least one of a light-emitting surface and a backlight surface of the semiconductor wafer substrate. Through hole. The doped layer is located on the surface of the semiconductor wafer substrate, the inner wall surface inside the recess, and the inner wall surface of the through hole. The first electrode layer is located on the semiconductor wafer
D 基板之背光面與其表面之摻雜層相互共晶。第二電極層 是於半導體晶圓基板之背光面伸入此貫穿孔，並與貫穿 孔的内壁表面之掺雜層相互共晶。如此，藉由此實施例 利用背面電極之配置，可增加面板接收入射光之面積，改 善再度提高太陽電池面板之使用效率。 【實施方式】 p 以下將以圖示及詳細說明清楚說明本發明之精神，如 熟悉此技術之人員在暸解本發明之實施例後，當可由本發 明所教示之技術，加以改變及修飾，其並不脫離本發明之 精神與範圍。 本發明為一種太陽能電池面板結構，主要係包括半 導體晶圓基板、摻雜層、抗反射層、第一電極層及第二 電極層。半導體晶圓基板具有一未來用以面對入射光之 向光面及一對應此向光面之背光面，其中半導體晶圓基 板於其向光面及/或背光面上會配置有多個未貫穿的凹 7 201039451 穴。摻雜層堆疊於半導體晶圓基板的表面，至少會位於 向光面之表面。抗反射層位於摻雜層於向光面—側之表 面。第一電極層與第二電極層為相反之極性，第一電極 層位於半導體晶圓基板之向光面及/或背光面之一側，第 二電極層可位於半導體晶圓基板之背光面之一侧。如 此，除了半導體晶圓基板於向光面表面本身外，半導體 晶圓基板上所配置的凹穴之内壁1U表面亦可增加面板 接收入射光之面積，此外，向半導體晶圓基板内部凹下之 凹穴更可縮短載子（即電子或電洞）移動至摻雜層的距離、 幫助摻雜層收集到更多載子’尤其針對入射光之短波長對 於藍光響應的效果，更可提高太陽電池面板之使用效率， 在此，本發明提供以下多個實施例，藉由凹穴及電極 層的多種配置設計，以進一步闡明本案之技術特徵。 首先在介紹下列實施例前，需說明的是，本發明之半 導體晶圓基板100並不限定於非晶矽晶圓（amorphous silicon)、單晶梦晶圓（monocrystalline )或多晶破晶圓 (multicrystalline)之種類。其中半導體晶圓基板1 〇 〇及掺雜 層200之組合需為相反極性，可為p型晶圓基板搭配N 型摻雜層200，或N型晶圓基板搭配P型摻雜層200。 在以下之各實施例中，本發明係以為例，如此，半 導體晶圓基板100與摻雜層200之間將形成P-N接面（PN Junction)° 本發明之一第一實施例中，請參閱第1圖及第2圖所 示，第1圖係本發明第一實施例所示之俯視圖。第2圖係 繪示第1圖之2-2剖面側視圖。上述之此些凹穴11〇均配 201039451 置於半導體晶圓基板100之向 均:地f蓋於半導體晶圓基板⑽之向光面：二： =::广之内壁⑴表面。第-電極層-端 中一凹穴u"’並與此凹穴U0中内壁U1 層200相互產生-共晶結構，抗反射層· ===200之表面’及不具有第-電極層權之 凹八110内壁1U之摻雜層200表面，使得第一 ο 露於抗反射層300之表面。第二電“ 500疋覆蓋於半導體晶圓基板刚之背光面⑽，並與半 J體晶圓基板刚產生一共晶結構。如此，由於第2、圖 中之電子el及電子e2分別相對摻雜層2⑽的直線距離不 一致，電子el與摻雜層2〇〇的直線距離較電子e2與摻雜 層200的直線距離D1來的短長，可幫助摻雜層 到更多的電子^ 〃 ❹ 本發明之一第二實施例中，請參閱第3圖所示，第3 圖係繪示本發明第二實施例所示之剖面側視圖。此些凹穴 110均配置於半導體晶圓基板100之背光面1〇2上。摻 雜層200均勻地覆蓋於半導體晶圓基板1〇〇之向光面 101上。抗反射層300覆蓋於摻雜層2〇〇之表面。第一 電極層400位於半導體晶圓基板100之向光面ι〇1 一 侧，其一端穿過於抗反射層300與摻雜層200產生一共 晶結構，另端並顯露於抗反射層300之表面。第二電極 層500覆蓋半導體晶圓基板1〇〇之背光面1〇2及此些凹 穴110之内壁111表面，並與半導體晶圓基板1〇〇產生 一共晶結構。如此，由於半導體晶圓基板之背光面1〇2 9 201039451 的凹穴110 ’使得第3圖中電洞hi及電洞h2分別相對 第二電極層500的的直線距離不一致，電洞…與第二電 極層50的直線距離較電洞h2與第二電極層5〇〇的直線 距離D2的短，可幫助摻雜層收集到更多的電洞。 一本發明之一第三實施例中，請參閲第4圖所示，係繪 不本發明第三實施例所示之剖面侧視圖。此些凹穴、 11〇’可分別配置於半導體晶圓基板100之向光面1〇1 及背光面102上。摻雜層200均勻地覆蓋於半導體晶圓 0 基板100之向光面101表面及此些凹穴110之内壁 表面。第一電極層400之一端是伸入其中一凹穴丨1〇中， 並與此凹穴110中内壁ln表面之摻雜層2〇〇相互產生 一共晶結構，抗反射層300覆蓋於摻雜層2〇〇之表面， 及不具有第一電極層400之凹穴11〇内壁^丨之摻雜層 200表面。使得第一電極層4〇〇之另端則顯露於抗反射 層|〇〇之表面。第二電極層500覆蓋半導體晶圓基板1〇〇 之背光面102表面及此些凹穴11〇’之内壁Η〗表面， 〇 並與半導體晶圓基板100產生一共晶結構。 本發明之一第四實施例中，請參閱第6E圖所示，係繪 示本發明第四實施例所示之剖面侧視圖。此些凹穴11〇配 置於半導體晶圓基板1〇〇之向光面101上，且半導體晶 圓基板100上更具有至少一貫穿孔12〇，貫穿孔12〇接 通半導體晶圓基板1〇〇之向光面101及背光面102。摻 雜層200均勻地覆蓋於半導體晶圓基板1〇〇表面，包括 向光面101表面、此些凹穴110及貫穿孔12〇的内壁121 表面。第一電極層400之一端伸入背光面1〇2上之貫穿 201039451 孔120開口，卻不及向光面101上之貫穿孔120開口， 第一電極層400之另端並覆蓋於背光面102上之貫穿孔 120,第一電極層400並與貫穿孔120内壁121表面的摻 雜層200產生一共晶結構。上述之第二電極層500則位 於半導體晶圓基板100之背光面102與背光面102之摻 雜層200產生一共晶結構。 如此，由於將半導體晶圓基板100之向光面101原 有電極層結構的設計’改配置於半導體晶圓基板10 0之背 光面102,便可於半導體晶圓基板100之向光面101提供 η 更多面板接收更多入射光的面積，便可再度提高太陽電池 面板之使用效率。 本發明可藉由第四實施例為例，請同時參閱第5圖 及第6Α圖至第6Ε圖所示，第5圖係繪示本發明第四實施 例所示之製造流程圖。第6Α圖-第6Ε圖係繪示第四圖所表 示之結構流程示意圖。以介紹此太陽能電池面板結構10 之製造步驟： 步驟（501)提供一半導體晶圓基板100，例如此實施 〇 例中為提供一 Ρ型半導體晶圓基板100 ; 步驟（ 502)利用雷射工具，依據預定之尺寸及排列方 式分別於半導體晶圓基板100之向光面101上製作多個未 貫穿此半導體晶圓基板100的凹穴110,以及製作至少一 個貫穿半導體晶圓基板1〇〇之貫穿孔120(見第7圖之俯 視圖所示），其中製作凹穴110之細部尺寸及排列方式將 描述於文後； 步驟（ 503 )對此半導體晶圓基板100進行清洗程序 201039451 (Clean )及表面結構處理（Texture); 步驟（ 504)利用含磷擴散源於半導體晶圓基板loo 之表面進行一擴散程序，使得半導體晶圓基板100之表面 包括此些凹穴110内壁111表面及貫穿孔12〇的内壁121 表面，可形成一 N型摻雜層200,即使半導體晶圓基板1〇〇 與推雜層200之間形成P-N接面（PN Junct ion ); 步驟（ 505 )形成一抗反射層300至向光面ι〇1之一侧， 且位於摻雜層200上，抗反射層300之材質可為1化物（例 0 如氮化矽膜，SiNx film)、氧化物（例如氧化矽膜Si〇2 film)、其他材質之多層膜（Ti02/A12〇3)或銦錫氧化物 (Indium Tin Oxide，ITO )薄膜。 惟本發明中並不限制抗反射層300是配置於p型摻雜 層200或N型摻雜層200上，在此值的一提的是，當抗反 射層300採用具透明特性之銦錫氧化物薄膜時，將可提高 抗反射層300的透光度，並提高半導體晶圓基板1〇〇接受 入射光的強度’提升入射光之短波長對於藍光響應的效果； 〇 (506)利用網印方式’依據一預定圖形印刷第一次含 導電金屬膠（例如銀膠或鋁膠）至背光面具貫穿孔120 之位置，並使含導電金屬膠（例如銀膠或铭膠）伸入及覆 蓋貫穿孔120,再依據另一預定圖形印刷第二次含導電金 屬膠（例如鋁膠或銀膠）至背光面1〇2 一側之預設位置上； ( 507)將此未完成之太陽能電池面板川通過一快速 燒結爐進行燒結程序之加熱，使得各處的含導電金屬膠（銀 膠或銘朦）可與摻雜層2〇〇產生共晶結構，即形成破化物 (矽化銀或矽化鋁）的合金，使得覆蓋貫穿孔12〇的矽化 12 201039451 物（石夕化銀㈣仙）的合金便形成上述之第-電極声 400 ’而其他位於背光面1〇2之矽务 曰 从入人庇w 〇·、！_、+、>松 1匕物（矽化銀或矽化鋁） 的合金便形成上述之第二電極層5〇〇。 如此，當第一電極層400及筮_+』说 卑一電極層500皆位於太 陽電池面板之背面電極時，便可擗 -r從J增加面板接收入射光之面 積，以再度提高太陽電池面板之使用效率。 准上述之第-實施例至第三實施例，亦可此用類 似的製造步驟於適當的位置進行製作具凹穴11〇、The back surface of the D substrate is eutectic with the doped layer on its surface. The second electrode layer protrudes into the through hole from the backlight surface of the semiconductor wafer substrate and is eutectic with the doped layer of the inner wall surface of the through hole. Thus, with this embodiment, the arrangement of the back electrodes can increase the area of the panel to receive incident light, and improve the use efficiency of the solar panel again. BRIEF DESCRIPTION OF THE DRAWINGS The spirit of the present invention will be clearly described by the following description and detailed description of the present invention, which can be changed and modified by the teachings of the present invention after the embodiments of the present invention are known. The spirit and scope of the invention are not departed. The invention relates to a solar cell panel structure, which mainly comprises a semiconductor wafer substrate, a doped layer, an anti-reflection layer, a first electrode layer and a second electrode layer. The semiconductor wafer substrate has a future facing surface facing the incident light and a backlight surface corresponding to the light surface, wherein the semiconductor wafer substrate is disposed on the light surface and/or the backlight surface. Through the concave 7 201039451 hole. The doped layer is stacked on the surface of the semiconductor wafer substrate, at least on the surface of the light-facing surface. The antireflection layer is located on the surface of the doped layer on the light-side side. The first electrode layer and the second electrode layer are opposite in polarity, the first electrode layer is located on one side of the light surface and/or the backlight surface of the semiconductor wafer substrate, and the second electrode layer is located on the backlight surface of the semiconductor wafer substrate One side. In this way, in addition to the semiconductor wafer substrate on the surface to the smooth surface itself, the surface of the inner wall 1U of the recess disposed on the semiconductor wafer substrate can also increase the area of the panel to receive the incident light, and further, the interior of the semiconductor wafer substrate is recessed. The recesses can shorten the distance that the carrier (ie, electron or hole) moves to the doped layer, help the doped layer collect more carriers', especially for the short-wavelength of the incident light, and the effect of the blue light. The efficiency of use of the battery panel, the present invention provides the following various embodiments, with various configurations of the recess and the electrode layer to further clarify the technical features of the present invention. Before the following embodiments are described, it should be noted that the semiconductor wafer substrate 100 of the present invention is not limited to amorphous silicon, monocrystalline or polycrystalline wafers ( The type of multicrystalline). The combination of the semiconductor wafer substrate 1 and the doped layer 200 needs to be of opposite polarity, and the p-type wafer substrate can be matched with the N-type doping layer 200, or the N-type wafer substrate can be matched with the P-type doping layer 200. In the following embodiments, the present invention is exemplified, such that a PN junction is formed between the semiconductor wafer substrate 100 and the doped layer 200. In a first embodiment of the present invention, please refer to 1 and 2 are a plan view showing a first embodiment of the present invention. Fig. 2 is a cross-sectional side view taken along line 2-2 of Fig. 1. The above-mentioned recesses 11 are all equipped with 201039451 to be placed on the surface of the semiconductor wafer substrate 100: the ground surface of the semiconductor wafer substrate (10): two: =:: wide inner wall (1) surface. a recess u' in the first electrode layer-end and a mutual eutectic structure with the inner wall U1 layer 200 in the recess U0, the surface of the anti-reflective layer·===200 and the absence of the first electrode layer The surface of the doped layer 200 of the inner wall 1U is recessed so that the first surface is exposed on the surface of the anti-reflection layer 300. The second electric "500" covers the backlight surface (10) of the semiconductor wafer substrate, and has just formed a eutectic structure with the semi-J wafer substrate. Thus, since the electrons el and the electrons e2 in the second embodiment are respectively doped. The linear distance of layer 2 (10) is inconsistent, and the linear distance between the electron el and the doped layer 2〇〇 is shorter than the linear distance D1 between the electron e2 and the doped layer 200, which can help the doped layer to more electrons. In a second embodiment of the present invention, please refer to FIG. 3, which is a cross-sectional side view showing a second embodiment of the present invention. The recesses 110 are disposed on the semiconductor wafer substrate 100. On the backlight surface 1 〇 2, the doped layer 200 is uniformly covered on the light-emitting surface 101 of the semiconductor wafer substrate 1 . The anti-reflection layer 300 covers the surface of the doped layer 2 。. The first electrode layer 400 is located. One side of the semiconductor wafer substrate 100 on the light-emitting side ι〇1 has one end through the anti-reflection layer 300 and the doped layer 200 to form a eutectic structure, and the other end is exposed on the surface of the anti-reflection layer 300. The second electrode layer 500 Covering the backlight surface 1〇2 of the semiconductor wafer substrate 1 and the recesses 110 The surface of the inner wall 111 is formed with a eutectic structure with the semiconductor wafer substrate 1. Thus, the hole 110' of the back surface of the semiconductor wafer substrate 1 〇 2 9 201039451 makes the hole hi and the hole h2 in FIG. The linear distances from the second electrode layer 500 are inconsistent, and the linear distance between the hole and the second electrode layer 50 is shorter than the linear distance D2 between the hole h2 and the second electrode layer 5, which can help the doping layer to collect. To a more hole. In a third embodiment of the invention, please refer to Fig. 4, which is a cross-sectional side view showing a third embodiment of the invention. ' can be respectively disposed on the light-emitting surface 1〇1 and the backlight surface 102 of the semiconductor wafer substrate 100. The doped layer 200 uniformly covers the surface of the light-emitting surface 101 of the semiconductor wafer 0 substrate 100 and the recesses 110 The inner wall surface. One end of the first electrode layer 400 protrudes into one of the pockets 〇1〇, and forms a eutectic structure with the doped layer 2〇〇 of the inner wall ln surface of the recess 110, and the anti-reflection layer 300 covers On the surface of the doped layer 2, and the recess 11 having no first electrode layer 400 The inner wall of the doped layer 200 is such that the other end of the first electrode layer 4 is exposed on the surface of the anti-reflective layer. The second electrode layer 500 covers the back surface 102 of the semiconductor wafer substrate 1 The surface and the inner surface of the recesses are formed in a eutectic structure with the semiconductor wafer substrate 100. In a fourth embodiment of the present invention, please refer to FIG. 6E. A cross-sectional side view of the fourth embodiment of the present invention. The recesses 11 are disposed on the light-emitting surface 101 of the semiconductor wafer substrate 1 and the semiconductor wafer substrate 100 has at least a uniform through-hole 12 〇. The hole 12 turns on the light-emitting surface 101 and the backlight surface 102 of the semiconductor wafer substrate 1 . The doped layer 200 uniformly covers the surface of the semiconductor wafer substrate 1 including the surface of the light-emitting surface 101, the recesses 110, and the surface of the inner wall 121 of the through-hole 12A. One end of the first electrode layer 400 extends into the opening of the backlight surface 1〇2 through the hole of the 201039451 hole 120, but is not open to the through hole 120 on the light surface 101, and the other end of the first electrode layer 400 covers the backlight surface 102. The through hole 120, the first electrode layer 400 and the doped layer 200 on the surface of the inner wall 121 of the through hole 120 form a eutectic structure. The second electrode layer 500 described above generates a eutectic structure on the back surface 102 of the semiconductor wafer substrate 100 and the doped layer 200 of the backlight surface 102. In this manner, since the design of the original electrode layer structure of the light-emitting surface 101 of the semiconductor wafer substrate 100 is changed to the backlight surface 102 of the semiconductor wafer substrate 10, the light-emitting surface 101 of the semiconductor wafer substrate 100 can be provided. η More panels receive more of the incident light area, which can further improve the efficiency of solar panel use. The present invention can be exemplified by the fourth embodiment. Please refer to FIG. 5 and FIG. 6 to FIG. 6 at the same time. FIG. 5 is a manufacturing flow chart showing the fourth embodiment of the present invention. Fig. 6 - Fig. 6 is a schematic diagram showing the structure of the process shown in the fourth figure. To introduce the manufacturing steps of the solar cell panel structure 10: Step (501) provides a semiconductor wafer substrate 100. For example, in this embodiment, a germanium-type semiconductor wafer substrate 100 is provided; and step (502) utilizes a laser tool. A plurality of recesses 110 not penetrating the semiconductor wafer substrate 100 are formed on the light-emitting surface 101 of the semiconductor wafer substrate 100 according to a predetermined size and arrangement, and at least one through-through of the semiconductor wafer substrate is formed. The hole 120 (see the top view of FIG. 7), wherein the size and arrangement of the details of the recess 110 will be described later; Step (503) The cleaning process of the semiconductor wafer substrate 100 is performed 201039451 (Clean) and surface Step 504: performing a diffusion process on the surface of the semiconductor wafer substrate loo by using the phosphorus-containing diffusion source, so that the surface of the semiconductor wafer substrate 100 includes the surface of the inner wall 111 of the recess 110 and the through hole 12〇. On the surface of the inner wall 121, an N-type doped layer 200 can be formed, even if a PN junction is formed between the semiconductor wafer substrate 1 and the dummy layer 200; Step (505) forming an anti-reflection layer 300 to one side of the light-emitting surface ι〇1, and on the doped layer 200, the material of the anti-reflection layer 300 may be a compound (eg, 0 such as a tantalum nitride film, SiNx film) ), an oxide (for example, yttrium oxide film Si〇2 film), a multilayer film of other materials (Ti02/A12〇3) or an indium tin oxide (ITO) film. However, in the present invention, the anti-reflective layer 300 is not disposed on the p-type doped layer 200 or the n-type doped layer 200. In this case, when the anti-reflective layer 300 is made of indium tin having transparent characteristics, In the case of an oxide film, the transmittance of the anti-reflection layer 300 can be improved, and the intensity of the incident light can be increased by the semiconductor wafer substrate 1 ' 'increasing the effect of the short wavelength of the incident light on the blue light response; 〇 (506) Printing method 'prints a conductive metal paste (such as silver glue or aluminum glue) to the position of the backlight mask through hole 120 for the first time according to a predetermined pattern, and extends and covers the conductive metal glue (such as silver glue or gelatin). Passing through the hole 120, and printing a second conductive metal paste (such as aluminum glue or silver glue) to a preset position on the side of the backlight surface 1〇2 according to another predetermined pattern; (507) the unfinished solar cell The panel is heated by a sintering process in a rapid sintering furnace, so that the conductive metal paste (silver glue or immortal) can produce a eutectic structure with the doped layer 2, that is, a broken structure (silver telluride or deuterated) Aluminum alloy, making it covered矽 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 The alloy of _, +, > pine (silver telluride or aluminum telluride) forms the second electrode layer 5〇〇 described above. Thus, when the first electrode layer 400 and the 筮_+』 say that the electrode layer 500 is located on the back electrode of the solar cell panel, the area of the incident light can be received from the J-increasing panel to further increase the solar cell panel. The efficiency of use. With reference to the above-described third to third embodiments, it is also possible to fabricate the recesses 11 at appropriate positions using similar manufacturing steps.
110帛冑極層400及第二電極層的太陽能電池面 板10。 綜上所述，為了於改善入射光之接收面積、載子移動 距離以及收集載子數量下取得最佳化之結果，以及衡量太 陽能電池面板面板結構於現實考量下之強度，具體而言， 此些凹穴110、110’的外型可定義為圓形（或正方形），其 孔徑（或尺寸）可依製作凹穴110、110，的雷射工具而定。 另外’此些凹穴11〇、11〇，的深度不及此半導體晶圓基板 100厚度的一半，可介於微米（micro-meter)至此半導體 晶圓基板100厚度的一半。如此，此些凹穴110、110’的 尺寸外型可與先前技術中之微小起伏之倒金字塔型表面有 所區隔。至於排列方式下，此些凹穴U〇、11〇，可以矩陣/ 陣列的方式或其他非矩陣/陣列的方式排列，只要任二相鄰 之凹穴110、110’間的間距介於〇 5〜10釐米（millimeter) 的半導體晶圓基板100表面即可。 在其他考量下，此些凹穴110、110，之内壁111可形 成傾斜狀’使得入射光照射至其中一内壁111時，可反射 13 201039451 至另一内壁111，不致反射至相反方向而成為無效的光源。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何所屬技術領域中具有通常知識者，在 不脫離本發明之精神和範圍内，當可作各種之更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 » 1 能更明顯易懂，所附圖式之詳細說明如下： 第1圖係繪示本發明第一實施例所示之俯視圖。 第2圖係繪示第1圖之2-2剖面侧視圖。 第3圖係繪示本發明第二實施例所示之剖面侧視圖。 第4圖係繪示本發明第三實施例所示之剖面侧視圖。 第5圖係繪示本發明第四實施例所示之製造流程圖。 第6A圖-第6E圖係繪示第四圖所表示之結構流程示意 D 圖。 第7圖係繪示第6B圖之流程時，半導體晶圓基板之 俯視圖。 【主要元件符號說明】 10:太陽能電池面板結構 110、110’ ：凹穴 100:半導體晶圓基板 111:凹穴内壁 200 :摻雜層 120:貫穿孔 201039451 300 :抗反射層 400 :第一電極層 500 :第二電極層 101 :向光面 102 :背光面 121 :貫穿孔内壁 hi、h2 :電洞 el、e2 :電子 Dl、D2 :距離 步驟：501-507A solar cell panel 10 of 110 drain layer 400 and a second electrode layer. In summary, in order to improve the receiving area of incident light, the moving distance of the carrier, and the number of collected carriers, and to measure the strength of the solar panel panel structure under realistic considerations, specifically, The dimensions of the pockets 110, 110' may be defined as a circle (or square) whose aperture (or size) may depend on the laser tool that makes the pockets 110, 110. Further, the recesses 11〇, 11〇 are less than half the thickness of the semiconductor wafer substrate 100 and may be micro-meter to half the thickness of the semiconductor wafer substrate 100. Thus, the dimensions of such pockets 110, 110' can be distinguished from the inverted pyramid-shaped surface of the prior art which is slightly undulating. As for the arrangement, the recesses U〇, 11〇 can be arranged in a matrix/array manner or other non-matrix/array manner, as long as the spacing between any two adjacent recesses 110, 110' is between 〇5 The surface of the semiconductor wafer substrate 100 of ~10 cm (millimeter) may be used. In other considerations, the inner walls 111 of the recesses 110, 110 may be formed in an inclined shape so that when the incident light is irradiated to one of the inner walls 111, the reflection 13 201039451 to the other inner wall 111 may be ineffective and not invalidated in the opposite direction. Light source. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the scope of the present invention, and it is possible to make various changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention can be more clearly understood. The detailed description of the drawings is as follows: FIG. 1 is a first embodiment of the present invention. The top view shown in the example. Fig. 2 is a cross-sectional side view taken along line 2-2 of Fig. 1. Figure 3 is a cross-sectional side view showing the second embodiment of the present invention. Figure 4 is a cross-sectional side view showing a third embodiment of the present invention. Figure 5 is a flow chart showing the manufacturing process of the fourth embodiment of the present invention. Fig. 6A - Fig. 6E are diagrams showing the structural flow diagram D shown in the fourth figure. Fig. 7 is a plan view showing the semiconductor wafer substrate in the flow of Fig. 6B. [Main component symbol description] 10: Solar cell panel structure 110, 110': recess 100: semiconductor wafer substrate 111: recess inner wall 200: doped layer 120: through hole 201039451 300: anti-reflection layer 400: first electrode Layer 500: second electrode layer 101: illuminating surface 102: backlight surface 121: through-hole inner wall hi, h2: hole el, e2: electron D1, D2: distance step: 501-507
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