201008411 六、發明說明： 【發明所屬之技術領域】 本發明係關於一埋入式結構及其製法。特定言之，本發 明係關於一埋入式電路板結構，其内壁上有較平坦的表面。 【先前技術】 電路板是電子裝置中一種重要的元件。電路板的功能是 用來界定在一固體表面上的預定圖案。在電子裝置不斷追求 尺寸縮小的趨勢下，電路板上導線的線寬與導線之間的距離 於是乎變的越來越小。 ❹ 就目前的技術而言，有兩種符合需求的方法以形成此等 電路板。第一種稱為轉印法，是將圖案化線路轉印至一介電 層上。另外一種方法則是使用雷射方式將基材圖案化，來定 義-鑲嵌形式的結構’再使用—導電材料來填滿在基材 形成的凹穴，以完成-埋入式結構。 料成功在==面要:經過活化，才能使得導電材 技術。更有甚者4 常是使用叫 種基材的材料是不需要先經過無電 201008411 極電鍍技術的活化步驟，就可以讓導電材料填入基材上的凹 穴中。 ” 第1-4圖例示一種形成埋入式結構之習知方法。如第1 * 圖所示’首先，提供基材101。第一圖案化銅層110位於基 材101上，並暴露出部分的基材101。第一介電層120則覆 蓋第一圖案化銅層110以及基材1〇1。 ❹ 再來’如第2圖所示，將第一介電層120圖案化以形成 焊墊開口 122、通孔121以及鄰接焊墊開口 122之溝槽123， 其中盲孔121暴露出部分的第一圖案化銅層no。由於第一 圖案化銅層110所暴露出的表面可能還留有膠渣，而且會妨 礙後續形成的電性連接品質，因此會進行一清孔步驟，如第 3圖所示，以移除第一圖案化銅層11()所暴露出表面可能還 留有的膠渣，以有利於後續形成的電性連接。可以使用電漿 或是氧化劑’例如過錳酸鹽來執行此等清孔除膠渣的步驟。 . 除了移除所有留在第一圖案化銅層110所暴露出表面上的殘 邊外’清孔步驟也會侵勉第一介電層12〇的表面，包括通孔 121、焊墊開口 122以及溝槽123之側壁，於是在第一介電 層120上形成了粗糙的表面。如果此等粗糙的表面再進一步 進行一鋼沉積步驟時，如第4圖所示，在過分粗化的表面下 具有活化基粒的待鍍表面反而容易在銅層130上形成不要的 瘤狀物131，而使孔壁銅層13〇千瘡百孔，並因此減損了銅 201008411 層130的品質，同時元件的信賴度表現不增反減。更有甚者， 溝槽123的粗糙表面使得電路崎嶇，並造成訊號損失。銅層 130的不良品質危及埋入式結構1〇〇、電路板、與其所製得 之電子裝置的可靠度。 ψ % 因此，需要一種具有更佳表面平整度的埋入式結構以及 一種新穎製造方法，以提供一種具有良好可靠度的電路板。 【發明内容】 本發明於是提出一種在側壁上具有較為光滑平整表面 ' 的新穎埋入式結構以及製作此等埋入式結構的方法。由於本 ' 發明埋入式結構的側壁上具有更為光滑平整的表面，當一層 的銅沉積在本發明埋入式結構的側壁上時，可以將銅層上瘤 狀物的形成機率減到最小，進而增進本發明埋入式結構的可 Θ 靠度。‘此外，在本發明的一實施例中，本發明的埋入式結構 ^ 具有實質上平整又光滑的外表面。 本發明首先提出一種埋入式結構。本發明的埋入式結構 中包含包含一介電層、位於介電層中之一焊塾開口，·與位於 焊墊開口中以及介電層中之一通孔，其中焊墊開口與通孔一 起定義出埋入式緒構，通孔之側壁更進一步具有粗糙度C、 焊墊開口之側壁具有粗糙度B，而介電層之外表面具有實質 201008411 上平坦光滑之粗糖度A。其中，粗糙度A、粗糖度B及粗糙 度C三者彼此不同。 • 本發明其次提出另一種埋入式結構。本發明的埋入式結 、 構包含一基材、位於基材上之一第一圖案化導體層並選擇性 暴露此基材、一第一介電層覆蓋第一圖案化導體層與基材、 位於第一介電層中之焊墊開口，與位於焊墊開口中並暴露第 Ο —圖案化導體層之通孔，其中焊墊開口與通孔一起定義出埋 入式結構，通孔之側壁更進一步具有粗糙度C、焊墊開口之 側壁具有粗糙度B，而第一介電層之外表面具有實質上平坦 之粗縫度A。其中，粗糙度A、粗糙度B及粗糖度C三者彼 此不同。 本發明又提出一種形成埋入式電路結構的方法。在本發 明形成埋入式電路結構的方法中，首先提供一介電層。其 〇 次，形成一有機膜層以覆蓋介電層。繼續，形成位於介電層 / 與有機膜層中之通孔。再來，進行一清潔步驟以粗化通孔之 側壁。然後，圖案化介電層與有機膜層，以在介電層中形成 與通孔重疊之焊墊開口。焊墊開口與通孔一起定義出埋入式 結構。介電層之外表面具有粗糙度A，焊墊開口之側壁具有 粗糙度B，通孔之側壁具有粗糙度C。其中，粗糙度A、粗 糙度B及粗糙度C三者彼此不同。 201008411 本發明再提出一種形成埋入式電路結構的方法。在本發 明形成埋入式電路結構的方法中，首先提供具有一圖案化導 體層位於其上之基材。其次，形成一第一介電層以覆蓋第一 " 圖案化導體層與基材。之後，形成一第一有機膜層以覆蓋第 * 一介電層。繼續，形成一穿過第一介電層與第一有機膜層並 暴露第一圖案化導體層之通孔。再來，進行一第一清潔步驟 以粗化通孔之側壁，或是清除殘留餘第一圖案化導體層上之 0 膠渣。然後，圖案化第一介電層與第一有機膜層，以在第一 介電層中形成與通孔重疊之焊墊開口。焊墊開口與通孔一起 定義出埋入式電路結構。第一介電層之外表面具有粗糙度 A，焊墊開口之側壁具有粗糙度B，通孔之側壁具有粗糙度 C。其中，粗糙度A、粗糙度B及粗糙度C三者彼此不同。 本發明更提出一種形成埋入式電路結構的方法。在本發 明另一種形成埋入式電路結構的方法中，首先提供具有一圖 ® 案化導體層位於其上之基材。其次，形成一第一介電層以覆 - 蓋第一圖案化導體層與基材。之後，形成一第一有機膜層以 覆蓋第一介電層。繼續，形成一穿過第一介電層與第一有機 膜層並暴露第一圖案化導體層之通孔。再來，進行一第一清 潔步驟以粗化通孔之側壁及/或清除殘留於第一圖案化導體 層上之膠渣。然後，移除第一有機膜層。接著，進行一第二 清潔步驟以清理第一圖案化導體層。隨後，形成一第二有機 膜層以覆蓋第一介電層。接下來，圖案化第一介電層與第二 7 201008411 _ 有機膜層，以在第一介電層中形成與通孔重疊之焊墊開口。 焊墊開口與通孔一起定義出埋入式電路結構。第一介電層之 外表面具有粗糙度A，焊墊開口之側壁具有粗糙度B，通孔 之側壁具有粗糙度C。其中，粗糙度A、粗經度B及粗糙度 ' C三者彼此不同。 由於本發明新穎的埋入式結構在清潔步驟之後，經過一 魏 圖案化步驟以定義出焊墊開口或是選擇性地定義出溝槽，本 〇 發明埋入式結構的内壁則具有較為光滑平整的表面，同時還 避免了清潔步驟對内壁表面的破壞。此等清潔步驟一方面可 以促進第一圖案化導體層的電性連接，另一方面又使得通孔 中之内連線，亦即内部電性連接，對於通孔之内壁具有較佳 之親和性，其亦可以一第二清潔步驟繼之而更加強化。倘若 此等清潔步驟過或不及，皆屬不欲。 ® 再者，本發明還會減少銅瘤狀物的形成，並在當後續的 • 銅層沉積在本發明埋入式結構的内壁上時’得到品質較佳的 導體層。此外，本發明埋入式結構還會由於有機膜層的保 護，會進一步具有實質上光滑的外表面。 【實施方式】 本發明提供一種新穎的埋入式結構以及製作一種埋入 201008411 w 式電路結構的方法。由於本發明的埋入式結構在清潔步驟之 後才經過一圖案化步驟，所以本發明埋入式結構的内壁係具 有較為平坦的表面，甚至還會減少銅瘤狀物的形成。並由於 ' 此等較為平坦的表面，使得後續銅層的沉積品質變好，更增 進了本發明埋入式結構的可靠度。還有，本發明埋入式結構 還因為製造過程中有機膜層的保護，會進一步具有實質上光 滑的外表面。 ❹ 本發明首先提供一種埋入式結構。第5圖例示本發明埋 入式結構之一實施例。如第5圖所示，本發明的埋入式結構 200包含介電層220、通孔221與焊墊開口 222。 ' 介電層220之外表面224係實質上光滑。例如，介電層 220之外表面224具有粗糙度A。粗糙度A可以使用參數Ra 值來表示。定義此參數Ra之細節部份，請參考JIS B ❹ 0601-1982之規定。若使用參數Ra值來表示粗糙度A時， . 粗糖度A的範圍小於0.5μιη。 在本發明之一具體實施態樣中，介電層220可以進一步 包含多個觸媒顆粒，其中觸媒顆粒可以包含金屬錯合物顆 粒、金屬螯合物顆粒、金屬氧化物顆粒或是金屬氮化物顆 粒，例如锰、鉻、纪、銘、銘、鋅、銅、銀、金、鎳、钻、 錢、銀、鐵、鶴、飢、组、銦、鈦其中之一或是其任意組合 9 201008411 的錯合物、螯合物、氧化物或氮化物。 顆粒例如县 。舉例而言， 疋氧化銅、氮化鋁、 顆粒或鈀金屬顆粒。一 銘姻雙金屬氮化物 這些觸媒 。一但活化以後， 220的活 ’例如使用雷射， 化表面可以輔助另一導電層的沉積。 vi〇3Nx) 介電層 所形成的焊墊開口 222位在介電層22〇之中。此外，通 孔221還形成在焊墊開口 222之中與介電層22〇之中。從俯 〇視角度來觀察，焊墊開口 222形成包圍通孔221 (圖未示）。 通孔221與焊墊開口 222 —起定義出本發明埋入式結構2〇〇 的電路圖樣。每只通孔221中會有至少一個焊墊開口 222。 換句話說’如第5圖所示，每只通孔221中會視情況需要有 •一個焊墊開口 222，或是兩個焊墊開口 222。 另外’介電層220更包含不包圍通孔221但選擇性與通 孔221相通之溝槽223，如第5圖所示。溝槽223則可能賦 有多種構造相異的形狀，如第24圖所示。 類似地，溝槽223的内壁具有粗糙度B，焊墊開口 222 之側壁具有粗糙度B，而通孔221之内壁具有粗糙度C。若 使用參數Ra值來表示，粗糙度B的範圍則介於〇.2μιη與 1.5/mi之間。同樣地，若使用參數Ra值來表示，粗糙度C 的範圍則介於0.5/xm與5·0μιη之間。同時，粗縫度A、粗縫 度B及粗糙度C三者彼此不同。舉例而言，粗糙度A、粗糙 201008411 度B及粗梭度c二本々, —有之間彼此的關係可以為粗輪度c>粗链 度B>粗糙度a。 在本發明之另—㈣實施態樣巾，導顏23G則會填滿 通孔221、焊塾開D 222與選擇性形成的溝槽223，以形成 本發明之埋入式電路結構。導體層23〇通常包含金屬，例如 銅或是1呂’其可以由無電電錢製程（electroless plating ❹Process)來形成。若是介電層22〇包含金屬錯合物顆粒、金 屬螯合物顆粒、金屬氧化物顆粒或是金屬氮化物顆粒時，當 形成於介電層220内壁的活化表面之時，即會作為用於導體 層230之晶種層。 為了要達成介電層220之外表面224為實質上光滑之表 面，在本發明又一具體實施態樣中，埋入式電路結構可以包 含覆蓋介電層220並選擇性暴露通孔221、焊墊開口 222與 ❹選擇性形成的溝槽223之有機臈層25〇，以保護第一介電層 .220之外表面224。有機膜層250不只可以選擇性覆蓋單邊 之介電層220之外表面224，還可以選擇性覆蓋雙邊之介電 層220之外表面224。 有機膜層250可以包含親水性高分子，使得必要時可以 用水洗去。例如’此等親水性高分子的特性官能基可以包含 羥基(-0H)、醯胺基(-C0NH2)、磺酸基(-S03H)、羧基(-C00H) 201008411 .其中之-的官能基團，或者前述各官能基團的任意組合。 或者’有機膜層250亦可以是疏水性高分子。例如，此 .等疏水性高分子㈣性官能基可以包含甲基㈣酸樹脂、苯 .乙烯樹月曰稀丙樹脂、聚丙烯酸樹脂、聚峻樹脂、聚稀烴樹 =、聚醯胺樹脂或聚發氧織脂其中之—的官能基團，或者 前述各官能基團的任意組合。 ❹ 本發明其次知：供另一種埋入式結構。第6圖例示本發明 埋入式結構之一實施例。如第6圖所示，本發明的埋入式結 構200包含基材201、第一圖案化導體層21〇、第一介電層 220、通孔221與焊墊開口 222。基材201通常為用於電路板 . 之非導電性材料。 第一導體層210形成於基材201上，以覆蓋基材201， 並選擇性地暴露出基材201。第一導體層210可以包含例如 ❿銅或是銘之金屬。此外，第一導體層210還被圖案化，以定 義一預定之電路而成為第一圖案化導體層210。 位於第一圖案化導體層210上者為覆蓋基材2〇1與第一 圖案化導體層210之第一介電層220。第一介電層220之外 表面224係實質上光滑。例如，第一介電層220之外表面224 可以具有如前所述之粗糙度A。若使用參數Ra值來表示粗 糙度A時’粗縫度A小於〇.5μιη。第一介電層220亦可以進 12 201008411 一步包含多個觸媒顆粒，其中觸媒顆粒可以是包含如前所述 之金屬錯合物顆粒、金屬螯合物顆粒、金屬氧化物顆粒或是 金屬氮化物顆粒。一但活化以後，例如使用雷射，第一介電 層220的活化表面可以辅助另〆導電層的沉積。 形成焊墊開口 222在第〆介電層220之上。此外’通孔 221還形成在焊墊開口 222之中，從俯視角度來觀察，焊墊 q 開口 222形成包圍通孔221。通孔221暴露出位於下方之第 一圖案化導體層210，使得通孔221與焊墊開口 222 —起定 義出本發明埋入式結構2〇〇的電路圖樣。另外，第一介電層 220更包含非包圍通孔221並選擇性與通孔221相通之溝槽 223,如圖6所示。溝槽223可能竦有多種構造相異的形狀， 如第24圖所示。 〇 類似地’溝槽223的内壁可以具有粗糖度如前所述之 B，焊墊開口 222之側壁具有如前所述之粗糙度b，而通孔 之内壁具有如前所述之粗縫度C。若使用參數尺&值來表示 粗链度A、_度B及粗糙度C三者彼此列。粗輪度^ 粗縫度B及粗縫度C三者之間彼此的關係為粗輪度 度B〉粗糙度A。 祖後 在本發明之另一具體實施態樣中，第二導體層 填滿通孔221、焊墊開口 222與選擇性形成的溝槽 13 201008411 形成本發明之埋入式電路結構。第二導體層230通常包含金 屬，例如銅或是銘，其可以由無電電錢製程（electroless plating process)來形成。若是第一介電層220包含金屬錯合 物顆粒、金屬螯合物顆粒、金屬氧化物顆粒或是金屬氮化物 ' 顆粒時，當形成於第一介電層220内壁的活化表面，即會作 為用於第二導體層230之晶種層。 @ 基材201包含用於電性連接第一圖案化導體層210與第 三圖案化導體層240之内連線214以及第三圖案化導體層 240，如第6圖所示。第三圖案化導體層240通常包含金屬， 例如銅或是銘。 ' 為了要達成第一介電層220之外表面224為實質上光滑 之表面，在本發明又一具體實施態樣中，埋入式電路結構可 以包含如前所述之有機膜層250，其覆蓋第一介電層220並 〇 選擇性暴露通孔221、焊墊開口 222與選擇性形成的溝槽 223，以保護第一介電層220之外表面224。 本發明又提供一形成埋入式電路結構的方法，並更進一 步用來形成埋入式電路結構。請參考第7-13圖，其例示本 發明用以形成埋入式電路結構的方法一實施例。如第7圖所 示，首先提供一介電層220。在本發明之一具體實施態樣中’ 介電層220可以進一步包含多個觸媒顆粒。一但使用例如雷 14 201008411 射活化乂後介電層220的活化表面，可以輔助另一導電層 的沉積。 其-人如第8圖所示’形成有機臈層250，以覆蓋介電 層220。因此，有機膜層250即會保護介電層220之外表面 224，免於任何不欲的損傷。有機膜層250可以選擇性覆蓋 單邊之介電層220之外表面224，或是雙邊之介電層220之 0 外表面224。 介電層220之外表面224具有一原始的粗糙度A，例如， 實質上為光滑。可以使用參數Ra值來表示粗糙度Λ。若以 .參數1^值來表示時，粗糙度Α的範圍小於〇.5μιη。 然後’如第9圖所示，在介電層220與有機膜層250之 ❹中形成至少一通孔221。通孔221穿透介電層220與有機膜 層250 ’以建立一穿透洞（thr0Ugh hole )。可以使用雷射來 移除部份的介電層220與部份的有機膜層250來形成通孔 221。每只通孔221中會有至少一個焊墊開口 222。換句話 說’每只通孔221中會視情況需要，有一個焊墊開口 222， 或是兩個焊墊開口 222。 再來，進行一清潔步驟來咬蝕介電層220與有機膜層 250的内壁，留下了介電層220與有機膜層250都有受攻擊 15 201008411 的内表面’亦即’粗化的表面，如第10圖所示。然而，由 於有機膜層250的保護與屏蔽，介電層220之外表面224即 免受清潔步驟所造成的攻擊，並維持其原始的粗輪度A，例 如，實質上為光滑。清潔步驟可以包含使用能量性粒子，例 如電漿’或是使用氧化劑，例如過鏟酸鹽。 有機膜層250會保護介電層220之外表面224，免受不 ❹欲的攻擊，有機臈層250可以包含親水性高分子，使得在必 要時可以用水洗去。例如，此等親水性高分子之特性官能基 可以包含經基(_〇H)、酿胺基(_c〇NH2)、續酸基(_s〇3h)、叛 基（C〇〇h)其中之一的官能基團，或者前述各官能基團的任 ' 意組合。或是，包含疏水性高分子。例如，此等疏水性高分 子之特性官能基可以包含曱基丙烯酸樹脂、苯乙烯樹脂、烯 丙樹脂、聚丙烯酸樹脂、聚醚樹脂、聚浠烴樹脂、聚醯胺樹 〇 知、聚矽氧烷樹脂其中之任一官能基團’或者前述各官能基 圈的住意組合。 如第11圖所示，之後將導體層210與有機膜層250圖 ”化以形成焊墊開口 222，並同時強化通孔221，或是再選 上眭形成溝槽223。焊墊開口 222環繞通孔221，或是換句 2說，焊墊開口 222與通孔221重疊。焊墊開口 222與通孔 22ι —起定義出本發明之埋入式電路結構。在本發明另一實 施態樣中，亦可以獨立定義出焊墊開口 222。如果焊墊開口 201008411 222中所形成之焊墊，無須藉通孔221而與其他相鄰導電層 電性連接時，焊墊開口 222與通孔221可以不必重疊。 與焊墊開口 222相比，溝槽223並不環繞通孔221，但 • 可選擇性地與通孔221相連接。同理，焊墊開口 222與選擇 性形成的溝槽223，可以使用雷射來移除部份的介電層220 與部份的有機膜層250來達成。當形成了焊墊開口 222與溝 ❹槽223時，則溝槽223的内壁具有粗糙度B，焊墊開口 222 之側壁具有粗糙度B。若使用參數Ra值來表示，粗糙度b 的範圍則介於〇.2μιη與1.5/mi之間。 在形成焊墊開口 222與選擇性形成的溝槽223時，會同 時強化通孔221，使得通孔221之内壁具有不同的粗糙度， 即為粗糙度C。若使用參數5^值來表示，粗糙度c的範圍 則介於〇.5ym與5.〇gm之間。其中，粗輪度a、粗糖度b、 ® 粗糖度C二者彼此不同。甚至，粗糖度a'粗糙度b、粗糖 — 度C二者之間彼此存在一關聯性。例如，為粗縫度c>粗缝 度B>粗糙度A。 如果介電層220包含多個觸媒顆粒，其中觸媒顆粒可以 是包含一金屬錯合物、一金屬螯合物、一金層氧化物或一金 屬氮化物’形成焊墊開口 222與選擇性形成的溝槽223時， 會同時活化此等金屬錯合物、金屬螯合物、金屬氧化物或是 17 201008411 舌化差：& W如使用雷射活化以後’形成的介電屉220的 活化表面即可辅助另—導電層的沉積。 電層挪的 進行明的埋入式電路結構，如第12圖所示， 奶之切使於通孔221、焊塾開口 222與溝槽 無電電二t 。其中，第一沉積步驟可以為- ❹ 媒顆粒二:。如果介電層22°包含多個觸媒顆粒，其中觸 一令厘_ u是包含一金屬錯合物顆粒、一金屬螯合物顆粒、 222與^化物顆粒或—金職化物顆粒，並於形成焊塾開口 為作U槽223的過程中活化，介電層’的活化表面可視 、、電電鑛製程時之晶種層。導體層23〇可 鋼或是鋁之金屬。 ！ ^此外，更可依實際需求，選擇性地再進行一第二沉積步 ❹驟，例如電鍍方法，使得導體層230填入通孔221、焊墊開 2與溝槽223之中。由於在清潔步驟後才形成焊墊開口 =2與溝槽223之内壁，或是同時強化了通孔22丨，於是在 車乂為平垣的表面上減少形成銅瘤狀物的發生。 另外’可以選擇性地保留或者移除有機膜層25〇。當選 擇移除有機膜層250後，介電層220表面為實質上光滑，如 第13圖所示。例如’當有機膜層250是一親水性高分子時， 有機膦層250就可以利用水洗的方式移除。 201008411 本發明再提供一形成埋入式電路結構的方法，並更進一 步用來形成埋入式電路結構。請參考第14-23圖，其例示本 ' 發明用以形成埋入式電路結構的方法一實施例。如第14圖 所示，首先提供一基材201，其中基材201具有一第一圖案 化導體層210位於其上，且第一圖案化導體層210選擇性的 暴露基材201。然後形成第一介電層220以覆蓋第一圖案化 q 導體層210與基材201。 基材201通常為用於電路板之非導電性材料。基材201 包含用於電性連接第一圖案化導體層210與第三圖案化導體 層240之内連線214與第三圖案化導體層240,如第14圖所 示。第一圖案化導體層210或是第三圖案化導體層240通常 包含金屬’例如銅或是銘。 © 第一介電層220之外表面224具有一原始的粗糙度A， 例如，實質上為光滑。可以使用參數Ra值來表示粗糙度A。 若以參數Ra值來表示時，粗链度A小於0.5μιη。 在本發明之一具體實施態樣中，第一介電層220可以進 一步包含多個觸媒顆粒，其中觸媒顆粒可以是如前所述。一 但使用例如雷射活化以後，第一介電層220的活化表面，可 以輔助另一導電層的沉積。 19 201008411 其次，如第15圖所示，形成第一有機膜層250，以覆蓋 第一介電層220。因此，第一有機膜層250即會保護第一介 電層220之外表面224，免於任何不欲的損傷。第一有機膜 層250之材料種類可為如前所述者。 然後，如第16圖所示，在第一介電層220與第一有機 Ο 膜層250之中形成至少一通孔221。通孔221穿透第一介電 層220與第一有機膜層250以暴露出位於下方之第一圖案化 導體層210。可以使用雷射來移除部份的第一介電層220與 部份的第一有機膜層250來形成至少一通孔221。 再來，進行一第一清潔步驟來清除暴露出的第一圖案化 導體層210表面之殘餘膠渣。如前所述，由於一些膠渣211 會散佈在暴露出的第一圖案化導體層210之表面，並因此妨 ❹ 礙後續的電性連接品質，所以一個清潔步驟是需要的，如第 . 17圖所示。 第一清潔步驟可以包含使用能量性粒子，例如電漿’或 是使用氧化劑，例如過錳酸鹽。如前所述，除了會清除散佈 在第一圖案化導體層210暴露出表面的所有膠渣211之外， 清潔步驟還會侵蝕第一介電層220與第一有機膜層250的内 壁，留下了第一介電層220與第一有機膜層250都有受攻擊 20 201008411 的内表面，亦即，粗化的表面，如第17圖所示。然而，由 於第一有機膜層250的保護與屏蔽，第一介電層220之外表 面224即免受清潔步驟所造成的傷害，並維持其原始的粗糙 度A，例如，實質上為光滑。 以下之步驟，為需視第一圖案化導體層210所暴露出表 面的品質情況而選擇性地進行另一清潔步驟。換言之，當第 q 一圖案化導體層210所暴露出表面的情況不需要進一步的清 潔，同時第一有機膜層250還保留在第一介電層220表面 上，即可以略過以下的另一清潔步驟。 •如果第一有機膜層250包含親水性高分子’第一有機膜 層250就可以用水洗去，如第18圖所示。繼續進行一第二 清潔步驟’例如微姓（micro-etching )，以再次清理暴露出之 第一圖案化導體層210表面，如第19圖所示。第二清潔步 ® 驟可以包含使用某些氧化劑，例如過硫酸納加上疏酸’或是 - 過氧化氫加上硫酸，或是僅使用稀硫酸本身。 在第二清潔步驟完成後，再次形成第二有機膜層250’ 以覆蓋第一介電層220與通孔221'如第20圖所示。若在未 進行前述的第二清潔步驟，以及未去除第一有機膜層25〇 時，則第一有機膜層250即成為第一有機膜層250’。在以下 的敘述中，皆統稱為有機膜層250’。 21 201008411 有機膜層250可以保.護第一介電層220之外表面224即 免受任何不欲的傷害。有機臈層25〇,可以包含親水性高分 子，使得必要時可以用水洗去。例如，此等親水性高分子的 特性官能基可以包含羥基(-〇H)、醯胺基(_c〇NH2)、磺酸基 (S〇3H)、|t基(-COOH)其中之一官能基團，或者前述各官能 基團的任意組合。 〇 或者，有機臈層250,亦可以包含疏水性高分子。例如， 此等疏水性高分子之特性官能基可以包含曱基丙烯酸樹 月曰本乙烯樹脂、烯丙樹脂、聚丙晞酸樹脂、聚趟樹脂、聚 烯烴樹脂、聚醯胺樹脂、聚矽氧烷樹脂其中之一官能基團， 或者前述各個官能基團的任意組合。 _ 無論是否要進行第二清潔步驟，如第21圖所示，之後 將第一導體層210與有機膜層250,圖案化以形成焊墊開口 222，並同時強化通孔221，以及選擇性形成溝槽223。焊墊 開口 222環繞通孔221，或是換句話說，焊墊開口 222與通 孔221重疊。焊墊開口 222與通孔221 —起定義出本發明之 埋入式電路結構。 與焊墊開口 222相比’溝槽223並不環繞通孔221，但 可選擇性地與通孔221相連接。同理，焊墊開口 222與選擇 22 201008411 性形成的溝槽223，可以使用雷射來移除部份的第一介電層 220與部份的第一有機膜層250’來達成。當形成了焊墊開口 222與溝槽223時，則溝槽223的内壁具有粗糙度B，焊墊 開口 222之侧壁具有粗糙度B。若使用參數Ra值來表示， 粗糖度B的範圍則介於0.2/mi與1.5/mi之間。 在形成焊墊開口 222與選擇性形成的溝槽223時，會同 0 時強化通孔221，而通孔221之内壁具有不同的粗糙度，即 為粗糙度C。若使用參數Ra值來表示，粗糙度C的範圍則 介於0.5/im與5.0/mi之間。其中，粗經度A、粗糖度B、粗 糙度C三者彼此不同。甚至，粗糙度A、粗糙度B、粗糙度 C三者之間彼此存在一關聯性。例如，為粗糙度C>粗糙度 3>粗縫度A。 如果第一介電層220包含多個觸媒顆粒’其中觸媒顆粒 @ 可以是包含一金屬錯合物、一金屬螯合物、一金屬氧化物或 一金屬氮化物，形成焊墊開口 222與選擇性形成的溝槽223 時會同時活化此等金屬錯合物、金屬螯合物、金屬氧化物或 是金屬氮化物。例如使用雷射活化以後，形成的第一介電層 220的活化表面即可輔助另一導電層的沉積。 為了要形成本發明的埋入式電路結構’如第22圖所示， 進行一第一沉積步驟’使於通孔221、焊墊開口 222與溝槽 23 201008411 "223之中形成一第二導體層230。其中，第一沉積步驟可以 為一無電電鍍製程。如果第一介電層220包含多個觸媒顆 粒，其中觸媒顆粒可以是包含一金屬錯合物顆粒、一金屬螯 合物顆粒、一金屬氧化物顆粒或一金屬氮化物顆粒，並於形 成焊墊開口 222與溝槽223的過程中活化，第一介電層220 的活化表面可視為作為無電電鍍製程時之晶種層。第二導體 層230可以包含例如銅或是鋁之金屬。 〇 此外，更可依實際需求，選擇性地再進行第二沉積步 驟，例如電鍍製程，使得第二導體層230填入通孔221、焊 墊開口 222與溝槽223之中。由於在清潔步驟後才形成焊墊 開口 222與溝槽223之内壁，或是同時強化了通孔221，於 是在較為平坦的表面上減少形成銅瘤狀物的發生’則可得到 較佳電性連接品質的導體層。 ® 另外，可以選擇性地保留或者移除有機膜層250’。當選 • 擇移除有機膜層250’後的第一介電層220表面為實質上光 滑，如第23圖所示。例如，當有機膜層250’是一親水性高 分子時，有機膜層250’就可以利用水洗的方式移除。 綜前所述，由於本發明的埋入式電路結構在清潔步驟 (第一清潔步驟）之後，才經過一圖案化步驟’本發明的通 孔、焊墊開口與溝槽的内壁於是具有較為光滑平整的表面’ 24 201008411 且該光滑平整的表面也會減少形成銅瘤狀物的發生’使得後 續的銅層沉積在本發明埋入式結構的側壁上時，巧*得到权隹 電性連接品質的導體層，並增進本發明埋入式結構的町办 度。此外’本發明的埋入式結構還可以因為製造過程中有機 膜層的保護，而可以具有實質上平整又光滑的外表面。 以上所述僅為本發明之一實施例，凡依本發明申請專利範圍所 © 做之均等變化與修飾’皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 、 第I-4圖例示一種形成埋入式結構之習知方法。 第5圖例示本發明埋入式結構之一實施例。 第6圖例示本發明埋入式結構之另一實施例。 Q 第7_13圖例示本發明用以形成埋入式電路結構的方法 實施例。 第14-23圖例示本發明用以形成埋入式電路結構方法的 另〜實施例。 第24圖例示本發明溝槽多種構造形狀的實施例。 【主要元件符號說明】 1〇〇埋入式結構 25 201008411 101基材 110第一圖案化銅層 120第一介電層 121通孔 122焊墊開口 123溝槽 130銅層 0 131瘤狀物 200埋入式結構 201基材 • 210第一圖案化導體層 211膠渣 214内連線 220介電層、第一介電層 ^ 221通孔 ❹ 222焊墊開口 223溝槽 224外表面 230導體層、第二導體層 240第三圖案化導體層 250、250’有機膜層201008411 VI. Description of the Invention: [Technical Field to Which the Invention Is Ascribed] The present invention relates to a buried structure and a method of manufacturing the same. In particular, the present invention relates to a buried circuit board structure having a relatively flat surface on its inner wall. [Prior Art] A circuit board is an important component in an electronic device. The function of the board is to define a predetermined pattern on a solid surface. As electronic devices continue to pursue shrinking dimensions, the line width of the wires on the board and the distance between the wires become smaller and smaller. ❹ As far as current technology is concerned, there are two ways to meet these requirements to form these boards. The first type, called the transfer method, transfers the patterned lines to a dielectric layer. Alternatively, the substrate can be patterned using a laser to define a structure in the form of a mosaic and then a conductive material to fill the recess formed in the substrate to complete the buried structure. The material is successfully in the == surface: after activation, the conductive material technology can be made. What's more, 4 is often the use of materials called substrates that do not require the first activation process of the 201008411 electrode plating technique to allow conductive materials to be filled into the recesses in the substrate. Figures 1-4 illustrate a conventional method of forming a buried structure. As shown in Figure 1 'First, a substrate 101 is provided. The first patterned copper layer 110 is on the substrate 101 and exposes a portion The substrate 101. The first dielectric layer 120 covers the first patterned copper layer 110 and the substrate 1〇1. ❹ Again, as shown in FIG. 2, the first dielectric layer 120 is patterned to form a solder. a pad opening 122, a through hole 121, and a trench 123 adjacent to the pad opening 122, wherein the blind hole 121 exposes a portion of the first patterned copper layer no. Since the surface exposed by the first patterned copper layer 110 may remain There is glue, and it will hinder the subsequent formation of electrical connection quality, so a cleaning step will be performed. As shown in Fig. 3, the surface exposed by removing the first patterned copper layer 11() may still remain. The slag is used to facilitate the subsequent electrical connection. The step of clearing the slag can be performed using a plasma or an oxidant such as permanganate. In addition to removing all residual edges remaining on the exposed surface of the first patterned copper layer 110, the clearing step also erodes the surface of the first dielectric layer 12, including vias 121, pad openings 122, and The sidewalls of the trenches 123 then form a rough surface on the first dielectric layer 120. If the rough surfaces are further subjected to a steel deposition step, as shown in Fig. 4, the surface to be plated having the activated basal under the excessively roughened surface tends to form unnecessary nodules on the copper layer 130. 131, and the copper layer 13 of the hole wall is riddled with holes, and thus the quality of the copper 201008411 layer 130 is degraded, and the reliability of the component is not increased or decreased. What is more, the rough surface of the trench 123 makes the circuit rugged and causes signal loss. The poor quality of the copper layer 130 jeopardizes the reliability of the buried structure, the circuit board, and the electronic device it produces. ψ % Therefore, there is a need for a buried structure with better surface flatness and a novel manufacturing method to provide a circuit board with good reliability. SUMMARY OF THE INVENTION The present invention therefore proposes a novel buried structure having a relatively smooth flat surface on a sidewall and a method of fabricating such a buried structure. Since the sidewall of the present invention has a smoother and smoother surface, when a layer of copper is deposited on the sidewall of the buried structure of the present invention, the formation of the nodules on the copper layer can be minimized. Further, the reliability of the buried structure of the present invention is enhanced. Further, in an embodiment of the invention, the buried structure ^ of the present invention has a substantially flat and smooth outer surface. The present invention first proposes a buried structure. The buried structure of the present invention comprises a dielectric layer, a solder fillet opening in the dielectric layer, and a via hole in the pad opening and in the dielectric layer, wherein the pad opening is together with the via hole A buried type is defined, the sidewall of the via further has a roughness C, the sidewall of the pad opening has a roughness B, and the outer surface of the dielectric layer has a flat smooth roughness A on the substantial 201008411. Among them, the roughness A, the coarseness B and the roughness C are different from each other. • The present invention secondly proposes another buried structure. The buried junction of the present invention comprises a substrate, a first patterned conductor layer on the substrate and selectively exposing the substrate, and a first dielectric layer covering the first patterned conductor layer and the substrate a pad opening in the first dielectric layer, and a via hole in the pad opening and exposing the second-patterned conductor layer, wherein the pad opening and the via hole together define a buried structure, the through hole The sidewall further has a roughness C, the sidewall of the pad opening has a roughness B, and the outer surface of the first dielectric layer has a substantially flat roughness A. Among them, the roughness A, the roughness B, and the coarseness C are different from each other. The present invention further provides a method of forming a buried circuit structure. In the method of forming a buried circuit structure of the present invention, a dielectric layer is first provided. At this time, an organic film layer is formed to cover the dielectric layer. Continuing, a via is formed in the dielectric layer/and the organic film layer. Further, a cleaning step is performed to roughen the side walls of the through holes. Then, the dielectric layer and the organic film layer are patterned to form a pad opening overlapping the via hole in the dielectric layer. The pad opening and the via define a buried structure. The outer surface of the dielectric layer has a roughness A, the sidewall of the pad opening has a roughness B, and the sidewall of the via has a roughness C. Among them, the roughness A, the roughness B, and the roughness C are different from each other. 201008411 The present invention further proposes a method of forming a buried circuit structure. In the method of forming a buried circuit structure of the present invention, a substrate having a patterned conductor layer thereon is first provided. Next, a first dielectric layer is formed to cover the first "patterned conductor layer and the substrate. Thereafter, a first organic film layer is formed to cover the first dielectric layer. Continuing, a via hole is formed through the first dielectric layer and the first organic film layer and exposing the first patterned conductor layer. Further, a first cleaning step is performed to roughen the sidewalls of the via holes or to remove the 0 slag remaining on the first patterned conductor layer. Then, the first dielectric layer and the first organic film layer are patterned to form a pad opening overlapping the via hole in the first dielectric layer. The pad opening and the via define a buried circuit structure. The outer surface of the first dielectric layer has a roughness A, the sidewall of the pad opening has a roughness B, and the sidewall of the via has a roughness C. Among them, the roughness A, the roughness B, and the roughness C are different from each other. The present invention further provides a method of forming a buried circuit structure. In another method of forming a buried circuit structure of the present invention, a substrate having a pattern of patterned conductor layers thereon is first provided. Next, a first dielectric layer is formed to cover the first patterned conductor layer and the substrate. Thereafter, a first organic film layer is formed to cover the first dielectric layer. Continuing, a via hole is formed through the first dielectric layer and the first organic film layer and exposing the first patterned conductor layer. Further, a first cleaning step is performed to roughen the sidewalls of the vias and/or remove the slag remaining on the first patterned conductor layer. Then, the first organic film layer is removed. Next, a second cleaning step is performed to clean the first patterned conductor layer. Subsequently, a second organic film layer is formed to cover the first dielectric layer. Next, the first dielectric layer and the second 7 201008411 _ organic film layer are patterned to form a pad opening overlapping the via hole in the first dielectric layer. The pad opening together with the via defines a buried circuit structure. The outer surface of the first dielectric layer has a roughness A, the sidewall of the pad opening has a roughness B, and the sidewall of the via has a roughness C. Among them, the roughness A, the coarse longitude B, and the roughness 'C are different from each other. Since the novel buried structure of the present invention, after the cleaning step, passes through a Wei patterning step to define a pad opening or selectively define a groove, the inner wall of the embedded structure of the present invention has a smoother and smoother shape. The surface also avoids damage to the inner wall surface by the cleaning step. On the one hand, the cleaning step can promote the electrical connection of the first patterned conductor layer, and on the other hand, the inner connection in the through hole, that is, the internal electrical connection, has a better affinity for the inner wall of the through hole. It can also be further enhanced by a second cleaning step. If these cleaning steps are too late or not, it is not desirable. Further, the present invention also reduces the formation of copper nodules and obtains a conductor layer of superior quality when a subsequent copper layer is deposited on the inner wall of the buried structure of the present invention. In addition, the buried structure of the present invention will further have a substantially smooth outer surface due to the protection of the organic film layer. [Embodiment] The present invention provides a novel buried structure and a method of fabricating a 201008411 w-type circuit structure. Since the buried structure of the present invention undergoes a patterning step after the cleaning step, the inner wall of the buried structure of the present invention has a relatively flat surface and even reduces the formation of copper nodules. And because of these relatively flat surfaces, the deposition quality of the subsequent copper layer is improved, and the reliability of the buried structure of the present invention is further enhanced. Also, the buried structure of the present invention further has a substantially smooth outer surface due to the protection of the organic film layer during the manufacturing process. ❹ The present invention first provides a buried structure. Fig. 5 illustrates an embodiment of the buried structure of the present invention. As shown in Fig. 5, the buried structure 200 of the present invention includes a dielectric layer 220, vias 221 and pad openings 222. The outer surface 224 of the dielectric layer 220 is substantially smooth. For example, the outer surface 224 of the dielectric layer 220 has a roughness A. Roughness A can be expressed using the parameter Ra value. To define the details of this parameter Ra, please refer to JIS B ❹ 0601-1982. If the parameter Ra value is used to indicate the roughness A, . The range of coarse sugar A is less than 0. 5μιη. In one embodiment of the present invention, the dielectric layer 220 may further include a plurality of catalyst particles, wherein the catalyst particles may comprise metal complex particles, metal chelate particles, metal oxide particles or metal nitrogen. Compound particles, such as manganese, chromium, Ji, Ming, Ming, zinc, copper, silver, gold, nickel, diamond, money, silver, iron, crane, hunger, group, indium, titanium, or any combination thereof 9 A complex, chelate, oxide or nitride of 201008411. Particles such as counties. For example, copper oxide, aluminum nitride, particles or palladium metal particles. A Ming Bimetal Nitride These catalysts. Once activated, the activity of 220, for example using a laser, can assist in the deposition of another conductive layer. Vi〇3Nx) Dielectric layer The pad opening 222 is formed in the dielectric layer 22〇. Further, a via hole 221 is also formed in the pad opening 222 and in the dielectric layer 22A. The pad opening 222 is formed to surround the through hole 221 (not shown) as viewed from a squint angle. The via 221 and the pad opening 222 together define a circuit pattern of the buried structure 2A of the present invention. There is at least one pad opening 222 in each of the through holes 221. In other words, as shown in Fig. 5, one pad opening 222 or two pad openings 222 are required in each of the through holes 221 as appropriate. Further, the dielectric layer 220 further includes a trench 223 that does not surround the via hole 221 but selectively communicates with the via hole 221, as shown in FIG. The grooves 223 may be given a variety of different configurations, as shown in Fig. 24. Similarly, the inner wall of the groove 223 has a roughness B, the side wall of the pad opening 222 has a roughness B, and the inner wall of the through hole 221 has a roughness C. If the parameter Ra value is used, the range of roughness B is between 〇. 2μιη and 1. Between 5/mi. Similarly, if the value of the parameter Ra is used, the range of the roughness C is between 0. Between 5/xm and 5·0μιη. At the same time, the rough degree A, the rough degree B, and the roughness C are different from each other. For example, the roughness A, the roughness 201008411 degrees B, and the coarseness c two 々, - the relationship between each other may be a coarse rotation c > a coarse chain B > roughness a. In the fourth embodiment of the present invention, the guide film 23G fills the through hole 221, the solder fill D 222 and the selectively formed trench 223 to form the buried circuit structure of the present invention. The conductor layer 23 〇 usually contains a metal such as copper or 1 Å which can be formed by an electroless plating process. If the dielectric layer 22 includes metal complex particles, metal chelate particles, metal oxide particles or metal nitride particles, when formed on the active surface of the inner wall of the dielectric layer 220, it is used as A seed layer of the conductor layer 230. In order to achieve a substantially smooth surface of the outer surface 224 of the dielectric layer 220, in another embodiment of the present invention, the buried circuit structure may include a capping dielectric layer 220 and selectively exposing the vias 221, soldering The pad opening 222 and the organic germanium layer 25 of the selectively formed trench 223 protect the first dielectric layer. 220 outer surface 224. The organic film layer 250 can selectively cover not only the outer surface 224 of the single-sided dielectric layer 220 but also the outer surface 224 of the double-sided dielectric layer 220. The organic film layer 250 may contain a hydrophilic polymer so that it can be washed off with water if necessary. For example, the characteristic functional groups of such hydrophilic polymers may include a hydroxyl group (-0H), a guanamine group (-CONH2), a sulfonic acid group (-S03H), and a carboxyl group (-C00H) 201008411. A functional group of - or any combination of the foregoing various functional groups. Alternatively, the organic film layer 250 may be a hydrophobic polymer. For example, this. The hydrophobic polymer (tetra) functional group may comprise a methyl (tetra) acid resin or benzene. A functional group of an ethylene tree, a polyacrylic resin, a polyacrylic resin, a polysulfonate, a polyolefin tree, a polyamine resin or a polyoxygenated resin, or any combination of the foregoing various functional groups. ❹ The invention is secondarily known: for another buried structure. Fig. 6 illustrates an embodiment of the buried structure of the present invention. As shown in Fig. 6, the buried structure 200 of the present invention comprises a substrate 201, a first patterned conductor layer 21, a first dielectric layer 220, a via 221 and a pad opening 222. Substrate 201 is typically used for circuit boards. Non-conductive material. The first conductor layer 210 is formed on the substrate 201 to cover the substrate 201 and selectively expose the substrate 201. The first conductor layer 210 may comprise, for example, beryllium copper or a metal of the name. In addition, the first conductor layer 210 is also patterned to define a predetermined circuit to become the first patterned conductor layer 210. Located on the first patterned conductor layer 210 is a first dielectric layer 220 covering the substrate 2〇1 and the first patterned conductor layer 210. The outer surface 224 of the first dielectric layer 220 is substantially smooth. For example, the outer surface 224 of the first dielectric layer 220 can have a roughness A as previously described. If the parameter Ra value is used to indicate the roughness A, the rough degree A is less than 〇. 5μιη. The first dielectric layer 220 may also include a plurality of catalyst particles in one step, wherein the catalyst particles may be metal complex particles, metal chelate particles, metal oxide particles or metals as described above. Nitride particles. Once activated, for example, using a laser, the activated surface of the first dielectric layer 220 can assist in the deposition of another conductive layer. A pad opening 222 is formed over the second dielectric layer 220. Further, the through hole 221 is also formed in the pad opening 222, and the pad q opening 222 is formed to surround the through hole 221 as viewed from a plan view. The via 221 exposes the first patterned conductor layer 210 located below, such that the via 221 and the pad opening 222 together define a circuit pattern of the buried structure 2 of the present invention. In addition, the first dielectric layer 220 further includes a trench 223 that does not surround the via hole 221 and selectively communicates with the via hole 221, as shown in FIG. The grooves 223 may have a variety of shapes that are different in configuration, as shown in Fig. 24. Similarly, the inner wall of the groove 223 may have a coarse sugar content as described above, B, the side wall of the pad opening 222 has a roughness b as described above, and the inner wall of the through hole has a rough seam as described above. C. If the parameter ruler & value is used, the thick chain degree A, the degree B, and the roughness C are listed. The relationship between the coarseness of the roughness B and the roughness C is the roughness B>roughness A. The ancestors In another embodiment of the invention, the second conductor layer fills the vias 221, the pad openings 222 and the selectively formed trenches 13 201008411 to form the buried circuit structure of the present invention. The second conductor layer 230 typically comprises a metal, such as copper or a metal, which may be formed by an electroless plating process. If the first dielectric layer 220 comprises metal complex particles, metal chelate particles, metal oxide particles or metal nitride particles, when formed on the active surface of the inner wall of the first dielectric layer 220, A seed layer for the second conductor layer 230. The substrate 201 includes interconnects 214 and third patterned conductor layers 240 for electrically connecting the first patterned conductor layer 210 and the third patterned conductor layer 240, as shown in FIG. The third patterned conductor layer 240 typically comprises a metal, such as copper or a metal. In order to achieve a substantially smooth surface of the outer surface 224 of the first dielectric layer 220, in another embodiment of the present invention, the buried circuit structure may comprise the organic film layer 250 as described above. The first dielectric layer 220 is covered and the via 221, the pad opening 222 and the selectively formed trench 223 are selectively exposed to protect the outer surface 224 of the first dielectric layer 220. The present invention further provides a method of forming a buried circuit structure and further for forming a buried circuit structure. Referring to Figure 7-13, an embodiment of a method for forming a buried circuit structure of the present invention is illustrated. As shown in Figure 7, a dielectric layer 220 is first provided. In one embodiment of the invention, the dielectric layer 220 may further comprise a plurality of catalyst particles. Once the activation surface of the succeeding dielectric layer 220 is activated by, for example, Ray 14 201008411, deposition of another conductive layer can be assisted. It is formed as shown in Fig. 8 to form an organic germanium layer 250 to cover the dielectric layer 220. Thus, the organic film layer 250 protects the outer surface 224 of the dielectric layer 220 from any unwanted damage. The organic film layer 250 may selectively cover the outer surface 224 of the single-sided dielectric layer 220 or the outer surface 224 of the double-sided dielectric layer 220. The outer surface 224 of the dielectric layer 220 has an original roughness A, for example, substantially smooth. The parameter Ra value can be used to represent the roughness Λ. If you use . When the parameter 1^ value is used, the range of roughness Α is less than 〇. 5μιη. Then, as shown in Fig. 9, at least one through hole 221 is formed in the crucible of the dielectric layer 220 and the organic film layer 250. The via hole 221 penetrates the dielectric layer 220 and the organic film layer 250' to establish a through hole (thr0Ugh hole). A portion of the dielectric layer 220 and a portion of the organic film layer 250 may be removed using a laser to form the via hole 221. There is at least one pad opening 222 in each of the through holes 221. In other words, each of the through holes 221 may have a pad opening 222 or two pad openings 222 as needed. Then, a cleaning step is performed to bite the inner walls of the dielectric layer 220 and the organic film layer 250, leaving both the dielectric layer 220 and the organic film layer 250 to be attacked. 15 201008411 inner surface 'is 'roughened' The surface is shown in Figure 10. However, due to the protection and shielding of the organic film layer 250, the outer surface 224 of the dielectric layer 220 is protected from attack by the cleaning step and maintains its original coarseness A, for example, substantially smooth. The cleaning step can involve the use of energetic particles, such as plasma, or the use of an oxidizing agent, such as a sulphate. The organic film layer 250 protects the outer surface 224 of the dielectric layer 220 from undesired attack, and the organic germanium layer 250 may contain a hydrophilic polymer so that it can be washed away with water if necessary. For example, the characteristic functional groups of these hydrophilic polymers may include a trans-group (_〇H), a amide group (_c〇NH2), a reductive acid group (_s〇3h), and a thiol group (C〇〇h). A functional group, or any combination of the foregoing various functional groups. Or, it contains a hydrophobic polymer. For example, the functional functional groups of these hydrophobic polymers may comprise a mercapto acrylic resin, a styrene resin, an acryl resin, a polyacryl resin, a polyether resin, a polyanthracene resin, a polyamide resin, and a polyoxyl Any one of the functional groups of the alkane resin or a combination of the aforementioned functional groups. As shown in FIG. 11, the conductor layer 210 and the organic film layer 250 are then patterned to form the pad opening 222, and the via hole 221 is simultaneously strengthened, or the trench is formed by the upper gate. The pad opening 222 is surrounded. The hole 221, or in other words 2, the pad opening 222 overlaps the through hole 221. The pad opening 222 and the through hole 22 ι together define the buried circuit structure of the present invention. In another embodiment of the present invention The pad opening 222 can also be independently defined. If the pad formed in the pad opening 201008411 222 does not need to be electrically connected to other adjacent conductive layers by the through hole 221, the pad opening 222 and the through hole 221 can be There is no need to overlap. The trench 223 does not surround the via 221 as compared to the pad opening 222, but can be selectively connected to the via 221. Similarly, the pad opening 222 and the selectively formed trench 223, A portion of the dielectric layer 220 and a portion of the organic film layer 250 may be removed using a laser. When the pad opening 222 and the trench groove 223 are formed, the inner wall of the trench 223 has a roughness B, The sidewall of the pad opening 222 has a roughness B. If the parameter Ra value is used Show that the range of roughness b is between 〇. 2μιη and 1. Between 5/mi. When the pad opening 222 and the selectively formed trench 223 are formed, the via hole 221 is simultaneously strengthened so that the inner wall of the via hole 221 has a different roughness, that is, the roughness C. If the parameter 5^ value is used, the range of roughness c is between 〇. 5ym and 5. 〇gm between. Among them, the coarse rotation a, the coarse sugar b, and the coarse sugar C are different from each other. Even, there is an association between the crude sugar a' roughness b and the crude sugar-degree C. For example, it is a rough degree c > a rough degree B > roughness A. If the dielectric layer 220 comprises a plurality of catalyst particles, wherein the catalyst particles may comprise a metal complex, a metal chelate, a gold layer oxide or a metal nitride forming a pad opening 222 and selectivity When the trench 223 is formed, the metal complex, the metal chelate, the metal oxide or the 17 201008411 is simultaneously activated: & W, if the laser is used after the activation of the dielectric tray 220 The activated surface assists in the deposition of another conductive layer. The electric layer is moved to make a clear buried circuit structure. As shown in Fig. 12, the milk is cut so that the through hole 221, the pad opening 222 and the groove have no electricity. Wherein, the first deposition step may be - 媒 media particle two:. If the dielectric layer 22° comprises a plurality of catalyst particles, wherein the contact layer comprises a metal complex particle, a metal chelate particle, a 222 and a compound particle or a gold compound particle, and The formation of the solder fillet opening is activated during the process of forming the U-groove 223, and the activation surface of the dielectric layer is visible, and the seed layer of the electro-electrode process. The conductor layer 23 is made of steel or aluminum. ! In addition, a second deposition step, such as an electroplating method, may be selectively performed to fill the via hole 221, the pad opening 2, and the trench 223. Since the pad opening = 2 and the inner wall of the groove 223 are formed after the cleaning step, or the through hole 22 is reinforced at the same time, the occurrence of the formation of the copper knob is reduced on the surface where the rut is flat. Further, the organic film layer 25 can be selectively retained or removed. When the removal of the organic film layer 250 is selected, the surface of the dielectric layer 220 is substantially smooth, as shown in FIG. For example, when the organic film layer 250 is a hydrophilic polymer, the organic phosphine layer 250 can be removed by washing with water. 201008411 The present invention further provides a method of forming a buried circuit structure and further for forming a buried circuit structure. Please refer to Figures 14-23 for illustrating an embodiment of the method of the present invention for forming a buried circuit structure. As shown in Fig. 14, a substrate 201 is first provided, wherein the substrate 201 has a first patterned conductor layer 210 thereon, and the first patterned conductor layer 210 selectively exposes the substrate 201. A first dielectric layer 220 is then formed to cover the first patterned q-conductor layer 210 and the substrate 201. Substrate 201 is typically a non-conductive material for a circuit board. The substrate 201 includes an interconnect 214 and a third patterned conductor layer 240 for electrically connecting the first patterned conductor layer 210 and the third patterned conductor layer 240, as shown in FIG. The first patterned conductor layer 210 or the third patterned conductor layer 240 typically comprises a metal such as copper or a metal. The outer surface 224 of the first dielectric layer 220 has an original roughness A, for example, substantially smooth. The parameter Ra value can be used to represent the roughness A. If expressed by the parameter Ra value, the coarse chain degree A is less than 0. 5μιη. In one embodiment of the invention, the first dielectric layer 220 can further comprise a plurality of catalyst particles, wherein the catalyst particles can be as previously described. Once activated by, for example, laser activation, the activated surface of the first dielectric layer 220 can assist in the deposition of another conductive layer. 19 201008411 Next, as shown in Fig. 15, a first organic film layer 250 is formed to cover the first dielectric layer 220. Therefore, the first organic film layer 250 protects the outer surface 224 of the first dielectric layer 220 from any unwanted damage. The material type of the first organic film layer 250 may be as described above. Then, as shown in Fig. 16, at least one through hole 221 is formed in the first dielectric layer 220 and the first organic germanium film layer 250. The via 221 penetrates the first dielectric layer 220 and the first organic film layer 250 to expose the first patterned conductor layer 210 located below. A portion of the first dielectric layer 220 and a portion of the first organic film layer 250 may be removed by laser to form at least one through hole 221. Further, a first cleaning step is performed to remove the residual slag of the exposed surface of the first patterned conductor layer 210. As previously mentioned, a cleaning step is required since some of the slag 211 will spread over the exposed surface of the first patterned conductor layer 210 and thus hinder subsequent electrical connection quality. Figure 17 shows. The first cleaning step may comprise the use of energetic particles, such as plasma, or the use of an oxidizing agent, such as permanganate. As described above, in addition to removing all of the slag 211 dispersed on the exposed surface of the first patterned conductor layer 210, the cleaning step erodes the inner walls of the first dielectric layer 220 and the first organic film layer 250, leaving Both the first dielectric layer 220 and the first organic film layer 250 are subjected to the inner surface of the attack 20 201008411, that is, the roughened surface, as shown in FIG. However, due to the protection and shielding of the first organic film layer 250, the outer surface 224 of the first dielectric layer 220 is protected from the damage caused by the cleaning step and maintains its original roughness A, for example, substantially smooth. The following steps selectively perform another cleaning step in view of the quality of the surface to which the first patterned conductor layer 210 is exposed. In other words, when the surface of the qth patterned conductor layer 210 is exposed, no further cleaning is required, and the first organic film layer 250 remains on the surface of the first dielectric layer 220, that is, the following another may be skipped. Cleaning steps. • If the first organic film layer 250 contains a hydrophilic polymer 'the first organic film layer 250, it can be washed off with water, as shown in Fig. 18. A second cleaning step, such as micro-etching, is continued to clean the exposed first patterned conductor layer 210 surface again, as shown in FIG. The second cleaning step ® may involve the use of certain oxidizing agents, such as sodium persulfate plus acid s or - hydrogen peroxide plus sulphuric acid, or only dilute sulphuric acid itself. After the second cleaning step is completed, the second organic film layer 250' is formed again to cover the first dielectric layer 220 and the via hole 221' as shown in FIG. If the second cleaning step described above is not performed and the first organic film layer 25 is not removed, the first organic film layer 250 becomes the first organic film layer 250'. In the following description, they are collectively referred to as an organic film layer 250'. 21 201008411 Organic film layer 250 can be guaranteed. The outer surface 224 of the first dielectric layer 220 is protected from any unwanted damage. The organic ruthenium layer is 25 Å and may contain hydrophilic high molecular weight so that it can be washed away with water if necessary. For example, the characteristic functional groups of such hydrophilic polymers may comprise one of a hydroxyl group (-〇H), a guanylamino group (_c〇NH2), a sulfonic acid group (S〇3H), and a |t group (-COOH). a group, or any combination of the foregoing various functional groups. Alternatively, the organic tantalum layer 250 may also contain a hydrophobic polymer. For example, the functional functional groups of the hydrophobic polymers may comprise mercaptoacrylic acid, acryl resin, polyacrylic acid resin, polyfluorene resin, polyolefin resin, polyamide resin, polyoxyalkylene oxide. One of the functional groups of the resin, or any combination of the foregoing various functional groups. _ whether or not a second cleaning step is to be performed, as shown in FIG. 21, after which the first conductor layer 210 and the organic film layer 250 are patterned to form the pad opening 222, and at the same time, the through holes 221 are reinforced, and selectively formed Trench 223. The pad opening 222 surrounds the through hole 221, or in other words, the pad opening 222 overlaps the through hole 221. The pad opening 222 together with the via 221 defines the buried circuit structure of the present invention. The trench 223 does not surround the via 221 as compared to the pad opening 222, but may be selectively connected to the via 221. Similarly, the pad opening 222 and the trench 223 formed by the selection of 2010 20101111 can be achieved by using a laser to remove a portion of the first dielectric layer 220 and a portion of the first organic film layer 250'. When the pad opening 222 and the groove 223 are formed, the inner wall of the groove 223 has a roughness B, and the side wall of the pad opening 222 has a roughness B. If the parameter Ra value is used, the range of the coarse sugar B is between 0. 2/mi and 1. Between 5/mi. When the pad opening 222 and the selectively formed trench 223 are formed, the via hole 221 is strengthened at the same time as 0, and the inner wall of the via hole 221 has a different roughness, that is, the roughness C. If the value of the parameter Ra is used, the range of the roughness C is between 0. 5/im and 5. Between 0/mi. Among them, the coarse longitude A, the coarse sugar B, and the coarseness C are different from each other. Even, the roughness A, the roughness B, and the roughness C have an association with each other. For example, it is roughness C > roughness 3 > roughness A. If the first dielectric layer 220 comprises a plurality of catalyst particles 'where the catalyst particles @ may comprise a metal complex, a metal chelate, a metal oxide or a metal nitride, forming a pad opening 222 and The selectively formed trenches 223 simultaneously activate such metal complexes, metal chelates, metal oxides or metal nitrides. For example, after activation using a laser, the activated surface of the first dielectric layer 220 formed can assist in the deposition of another conductive layer. In order to form the buried circuit structure of the present invention, as shown in FIG. 22, a first deposition step is performed to form a second in the via hole 221, the pad opening 222, and the trench 23 201008411 " Conductor layer 230. Wherein, the first deposition step can be an electroless plating process. If the first dielectric layer 220 comprises a plurality of catalyst particles, wherein the catalyst particles may comprise a metal complex particle, a metal chelate particle, a metal oxide particle or a metal nitride particle, and are formed During activation of the pad opening 222 and the trench 223, the activated surface of the first dielectric layer 220 can be considered as a seed layer during the electroless plating process. The second conductor layer 230 may comprise a metal such as copper or aluminum. Further, a second deposition step, such as an electroplating process, may be selectively performed, such that the second conductor layer 230 is filled in the via hole 221, the pad opening 222, and the trench 223, according to actual needs. Since the inner surface of the pad opening 222 and the trench 223 is formed after the cleaning step, or the through hole 221 is strengthened at the same time, the occurrence of the formation of the copper tumor is reduced on the relatively flat surface, and the electric property is obtained. Connect a quality conductor layer. In addition, the organic film layer 250' can be selectively retained or removed. The surface of the first dielectric layer 220 after the selective removal of the organic film layer 250' is substantially smooth, as shown in Fig. 23. For example, when the organic film layer 250' is a hydrophilic high molecular weight, the organic film layer 250' can be removed by washing. As described above, since the buried circuit structure of the present invention passes through a patterning step after the cleaning step (first cleaning step), the through holes, the pad openings and the inner walls of the trenches of the present invention are relatively smooth. The flat surface ' 24 201008411 and the smooth and flat surface will also reduce the occurrence of the formation of copper tumors', so that when the subsequent copper layer is deposited on the sidewall of the buried structure of the present invention, the quality of the electrical connection is obtained. The conductor layer and the degree of operation of the buried structure of the present invention is enhanced. Further, the buried structure of the present invention may have a substantially flat and smooth outer surface due to the protection of the organic film layer during the manufacturing process. The above is only one embodiment of the present invention, and all changes and modifications made by the scope of the present invention should be within the scope of the present invention. [Simple Description of the Drawings], Figure I-4 illustrates a conventional method of forming a buried structure. Fig. 5 illustrates an embodiment of the buried structure of the present invention. Figure 6 illustrates another embodiment of the buried structure of the present invention. Q Figure 7_13 illustrates an embodiment of the method of the present invention for forming a buried circuit structure. Figures 14-23 illustrate another embodiment of the method of the present invention for forming a buried circuit structure. Fig. 24 illustrates an embodiment of various structural shapes of the groove of the present invention. [Main component symbol description] 1〇〇buried structure 25 201008411 101 substrate 110 first patterned copper layer 120 first dielectric layer 121 through hole 122 pad opening 123 groove 130 copper layer 0 131 knob 200 Buried structure 201 substrate • 210 first patterned conductor layer 211 slag 214 interconnect 220 dielectric layer, first dielectric layer 221 through hole 222 pad opening 223 trench 224 outer surface 230 conductor layer Second conductor layer 240 third patterned conductor layer 250, 250' organic film layer