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TW200950002A - CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode - Google Patents

CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode Download PDF

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Publication number
TW200950002A
TW200950002A TW098100105A TW98100105A TW200950002A TW 200950002 A TW200950002 A TW 200950002A TW 098100105 A TW098100105 A TW 098100105A TW 98100105 A TW98100105 A TW 98100105A TW 200950002 A TW200950002 A TW 200950002A
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TW
Taiwan
Prior art keywords
gate
metal
germanium
layer
dielectric
Prior art date
Application number
TW098100105A
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Chinese (zh)
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TWI497647B (en
Inventor
Cyril Cabral Jr
Jack O Chu
Young-Hee Kim
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Ibm
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Publication date
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Publication of TW200950002A publication Critical patent/TW200950002A/en
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Publication of TWI497647B publication Critical patent/TWI497647B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) axe formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed form gate stacks. A dielectric layer is formed and patterned to cover an -NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET.

Description

200950002 六、發明說明： 【發明所屬之技術領域】 本發明有關一種半導體結構，尤其有關一種具有金 屬矽化物電極及金屬矽化物-鍺化物合金電極的互補金 氧半導體(CMOS)電晶體，及其製造方法。 【先前技術】 具有金屬閘極電極的場效電晶體由於閘極電極的 較高傳導性及因此電晶體操作的信號延遲降低，已使效 能提咼勝於具有多晶碎電極的同等（comparable)場效 電晶體。此外’金屬閘極電極去除了多晶石夕的空乏效應 (depletion effect)’因而允許閘極介電質在電性上變得比 較薄。另外，在p型場效電晶體的例子中，還去除了棚 摻雜物對通道區的擴散。儘管本技術中已知金屬閘極電 極的這些好處，但在互補金氧半導體(〇^〇3)電晶體的 習用製程流程中，已證明金屬閘極電極的整合很難實 施。 明確地說，在源極/汲極（S/D)接面活化退火所需要 的高溫處理步驟期間，大部分的金屬閘極材料與閘極介 電質互相作用。使金屬閘極堆疊免於接收高溫退火的需 要導致「後閘極(gate last)」或「取代閘極」整合方案= 研發，其中在源極/汲極活化及源極及汲極的金屬二之 後製造閘極堆疊，及在後續處理期間使其維持在低於 500 °C_的溫度。 " 200950002 在使用CMOS電晶體的半導體結構中整合金屬閘 極電極因CMOS電晶體的整合需要兩種閘極材料而更 加困難；兩種閘極材料中，一種具有接近通道中半導體 材料之價帶邊緣的功函數’及另一種具有接近相同半導 體材料之導帶邊緣的功函數。例如，在具有石夕通道的 CMOS裝置中，對於η型金氧半導體場效體 (NMOSFET) ’需要具有功函數約4 〇 eV的傳導材料， 及對於p型金氧半導體場效電晶體(PMOSFET)，需要具 有功函數約5.0 eV的另一傳導材料。 、 先前技術已知的取代閘極整合方案通常在源極/汲 極活化退火之後需要形成閘極介電質。在形成閘極介電 質（通常包含鬲k介電材料)之前，利用姓刻使半導體表 面暴露’通常導致在通道及閘極介電質之間的介面缺 陷。此外，兩種不同的金屬閘極材料通常以伴隨的微影 圖案化步驟及平坦化步驟形成。許多先前技術的取代閘 極整合方案在形成閘極介電質時，需要兩個分開的步 驟。因此，儘管先前技術中已知的取代閘極整合方案增 加金屬閘極電極之材料的選擇性’但處理複雜度及成本 的增加比典型習用的CM0S製程流程多出許多。 有鑑於上文，因此需要一種提供包括具雙功函數之 金屬閘極電極之CMO S電晶體之功能優點的半導體結 構，同時避免在閘極介電質及通道之間的損壞及介面狀 態。 200950002 此外，還需要製造此種半導體結構的方法，其同時- 比習用的CMOS整合方案將處理複雜度及成本的增加 降到最低。 【發明内容】 為因應上述需要，本發明提供一種半導體結構包括 一具有一金屬矽化物電極的電晶體及另一具有一金屬 矽化物-鍺化物合金電極的電晶體，及提供製造該半導 體結構的方法。 在本發明中，P型場效電晶體(PFET)及n型場效電 晶體(NFET)藉由圖案化閘極介電層、薄矽層、及矽鍺合 金層而形成。在形成源極/汲極區及閘極間隔物之後， 從=極堆疊移除矽鍺合金部分。形成及圖案化介電層以 覆蓋NFET閘極電極，同時暴露pFET的薄矽部分。將 鍺選擇性沈積在包括暴露之矽部分的半導體表面上。移 除介電層及沈積金屬層並與底下的半導體材料反應以 形成NFET之閘極電極的金屬石夕化物，同時形成丁 之閘極電極的金屬矽化物-鍺化物合金。 為了降低處理複雜度及成本，揭示一種使用犧牲層 的自對準金屬閘極處理方案。犧牲層包括含鍺層。此處 理流程允許對源極及汲極活化退火進行高溫處理，不用 顧及在高k閘極介電質及金屬閘極材料之間的反應。自 對準矽化物部分包括完全矽化的金屬矽化物.閘極電 200950002 極，在一個類型的電晶體（通常為η型場效電晶體）上形 成；及自對準金屬矽化物··鍺化物合金部分包括完全金 屬化的矽化物-鍺化物合金閘極電極，在另一個類型的 電晶體上形成。本發明避免完全實施取代閘極處理步 驟，致使在通道區及閘極介電質之間的介面受到保護。 另外，提供自對準金屬閘極結構的額外優點。儘管僅沈 積一用於金屬化的金屬層，但在ρ型及η型場效電晶體 之間可形成不同的金屬化材料。此外，由於氫會在矽化 物及紗化物-鍺化物合金中擴散，可輕易完成互補金氧 半導體裝置的鈍化。 根據本發明之一方面，提供一種形成一半導體結構 的方法，其包含： 形成一第一閘極介電質於一半導體基板的一第一 半導體部分上及一第二閘極介電質於該半導體基板的 一第二半導體部分上； 形成一第一矽部分於該第一閘極介電質上及一第 二矽部分於該第二閘極介電質上； 形成一閘極側含鍺部分於該第二矽部分上，且沒有 鍺沈積在該第一矽部分上；及 直接形成一包含一金屬石夕化物的第一閘極電極於 該第一閘極介電質上及直接形成一包含一金屬矽化物-鍺化物合金的第二閘極電極於該第二閘極介電質上。 在一具體實施例中，該方法另外包含形成一第一可 棄式含鍺部分於該第一矽部分上及一第二可棄式含鍺 200950002 部分於該第二矽部分上，其中該第一及第二可棄式含鍺 部分包含鍺原子濃度約25%至100%。較佳是，該第一 及第二可棄式含鍺部分的原子濃度介於約50%至 100%。 在另一具體實施例中，該第一及第二可棄式含鍺部 分包含具有相同鍺濃度的鍺或一石夕鍺合金。 在更另一具體實施例中，該方法另外包含形成一第 一閘極間隔物於該第一矽部分及該第一可棄式含鍺部 分的側壁上及一第二閘極間隔物於該第二矽部分及該 第二可棄式含鍺部分的侧壁上。 在又另一具體實施例中，該方法另外包含移除該第 一及第二可棄式含鍺部分而不移除該第一及第二矽部 分0 在還另一具體實施例中，該方法另外包含在該移除 該第一及第二可棄式含鍺部分之後，直接形成一介電遮 罩層於第一及第二矽部分上。 在還又另一具體實施例中，該方法另外包含圖案化 該介電遮罩層，其中在該圖案化之後，以該介電遮罩層 覆蓋該第一矽部分，及其中在該圖案化之後，暴露該第 二矽部分。 200950002 在進一步具體實施例中’該閘極侧 或-矽鍺合金。該閘極側含鍺部分 二；： 於約5%S 100%，原子濃度 ：的土度可介 部分中為實質上-致。 此積的閘極側含錯 接制^ 實斜’採用·性含鍺材料沈 積製程，以形成該閘極侧含鍺部分’其中在選擇= 材料沈積製程期間，在半導體表面上而未在介 2 上沈積鍺或矽鍺合金。 ·《表面 在又進一步具體實施例中，該方法另外包含： ，接沈積一金屬層於該第—矽部分及該閘極侧含 銘部分上，及 金屬化該第一矽部分及一由該閘極侧含鍺部分及 該第二發部分組成的堆疊。 在還進一步具體實施例中，直接形成一包含—金屬 矽化物的第一閘極電極於該第一閘極介電質上及直接 形成一包含一金屬石夕化物-鍺化物合金的第二閘極電極 於該第一閑.極介電質上。 在還又進一步具體實施例中，該第一閘極電極在與 該第一閘極介電質之一介面處具有一成分為MSi及該 第二閘極電極在與該第二閘極介電質之一介面處具有 一成分為MGexSiw，其中x介於約0.05至約〇.85，及 Μ為一元素金屬或一具有一成分為AyBi—y的金屬合 200950002 . 金，其中y介於0至1，及A為一第一元素金屬及B為 一第二元素金屬。 在又另一具體實施例中，該方法另外包含： 形成一第一閘極間隔物於該第一矽部分上及一第 ' 二閘極間隔物於該第二矽部分上；及 形成一第一源極區及一第一汲極區於該第一半導 體部分中及一第二源極區及一第二汲極區於該第二半 導體部分中。 在更又另一具體實施例中，在該圖案化之後，藉由 該介電遮罩層覆蓋該第一源極區及該第一汲極區，及在 該圖案化之後，暴露該第二源極區及該第二汲極區。 在還又另一具體實施例中，該方法另外包含： 直接形成一閘極側含鍺部分於該第二矽部分上； 直接形成一源極側含鍺部分於該第二源極區上；及 直接形成一汲極側含鍺部分於該第二汲極區上，其 中沈積鍺或一含鍺合金並不直接發生於該第一矽部 分、該第一源極區、及該第一没極區上。 在還又另一具體實施例中，該方法另外包含： 直接形成一閘極介電層於該半導體基板上； 直接形成一包含非晶石夕或多晶石夕的石夕層於該閘極 介電層上； 直接形成一包含鍺原子濃度約25%或以上的含鍺 200950002 層於該矽層上；及 圖案化該含鍺層及該矽層，唭中由該矽層形成該第 一矽部分及該第二矽部分，及其中形成一第一可棄式含 鍺部分於該第一矽部分上及形成一第二可棄式含鍺部 分於該第二石夕部分上。 根據本發明之另一方面，提供一種半導體結構，其 包含： 一第一場效電晶體，具有一第一閘極介電質及一直 接位在該第一閘極介電質上的第一閘極電極，其中該第 一閘極電極包含一金屬硬化物及具有一第一厚度；及 一第二場效電晶體，具有一第二閘極介電質及一直 接位在該第二閘極介電質上的第二閘極電極，其中該第 二閘極電極包^—金屬砍化物-錯化物合金及具有一第 二厚度，其中該第二厚度大於該第一厚度。 在一具體實施例中，該半導體結構另外包含： 一源極側金屬矽化物部分，直接位在該第一場效電 晶體的一源極區上及包含該金屬矽化物及具有一第三 厚度； 一汲極側金屬矽化物部分，直接位在該第一場效電 晶體的一及極區上及包含該金屬矽化物及具有該第三 厚度； 一源極側金屬碎化物-鍺化物合金部分，直接位在 該第二場效電晶體的一源極區上及包含該金屬矽化物_ 鍺化物合金及具有一第四厚度；及 200950002 一汲極侧金屬矽化物-鍺化物合金部分’直接位在 該第二場致電晶體的一汲極區上及包含該金屬石夕化物_ 鍺化物合金及具有該第四厚度，其中該第四厚度大於該 第三厚度。 在另一具體實施例中，該金屬石夕化物及該金屬石夕化 物-鍺化物合金係自一形成一金屬單矽化物及一金屬單 鍺化物的金屬衍生。例如，該金屬層可包含鎳、鉑、鈀、 鈷、或其組合。 在更另一具體實施例中，該第二厚度與該第一厚度 之比介於1.0至約L30。該第二厚度與該第一厚度之比 可介於約1.1至約1.30。 〜又另—具體實施例中，該半導體結構另外包含： 一，=閘極間隔物，橫向鄰接該第一閘極電極； —第二閘極間隔物，橫向鄰接該第二閘極電極；及 極的二Γί製程(M0L)介電層，縱向鄰接該第一問極電 隔物的内部側ΐ第二=電極的一頂面、該第-閘極間 | 土、及該第一閘極間隔物的内部侧壁。 -閘极2⑻具體實施射’讀第—閘極電極在與該第 分為]VlGe q* 貝之，丨面處具有一成 -元素金屬有中一0·05至約〇.85，及M為 - '有成刀為的金屬合金，其中 200950002 y介於0至 素金屬。 及Α為一第一元素金屬及Β為一第二元 二閘極電極可具有一縱向漸變成分，其中χ隨 極介電質的距離增加。或者，χ可遍及該 第一閘極電極為實質上不變。 …在還又另-具體實施例中，在該第—開極電極内每 :岔：2矽總量實質上相同於在該第二閘極電極内 每早位面積之發總量。 體 ▲為讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說 明如下： 【實施方式】 如上述，本發明有關具有金屬矽化物電極及金屬砂 化物~鍺化物合金電極的互補金氧半導體（CMOS)電晶 ^’、及其製造方法，現將參考附圖加以詳細說明。注％， 目似參考數字表示相似及對應元件。 參考圖1，根據本發明之示範性半導體結構包含車200950002 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor structure, and more particularly to a complementary metal oxide semiconductor (CMOS) transistor having a metal germanide electrode and a metal telluride-telluride alloy electrode, and Production method. [Prior Art] A field effect transistor having a metal gate electrode has improved performance compared to a polycrystalline crush electrode due to the higher conductivity of the gate electrode and thus the signal delay of the transistor operation. Field effect transistor. In addition, the 'metal gate electrode removes the depletion effect of the polycrystalline spine' and thus allows the gate dielectric to be electrically thinner. In addition, in the example of a p-type field effect transistor, the diffusion of the shed dopant to the channel region is also removed. Although these benefits of metal gate electrodes are known in the art, integration of metal gate electrodes has proven difficult to implement in conventional process processes for complementary metal oxide semiconductors. Specifically, most of the metal gate material interacts with the gate dielectric during the high temperature processing steps required for source/drain (S/D) junction activation annealing. Eliminating the need for high temperature annealing of the metal gate stack results in a "gate last" or "replacement gate" integration scheme = R&D, where the source/drain activation and source and drain metal The gate stack is then fabricated and maintained at a temperature below 500 °C during subsequent processing. " 200950002 Integrating metal gate electrodes in semiconductor structures using CMOS transistors is more difficult due to the need for two gate materials for the integration of CMOS transistors; one of the two gate materials has a valence band of semiconductor material close to the channel The work function of the edge' and another work function with a conduction band edge close to the same semiconductor material. For example, in a CMOS device having a stone channel, a conductive material having a work function of about 4 〇eV is required for an n-type MOSFET (NMOSFET), and a p-type MOS field effect transistor (PMOSFET) is required. Another conductive material having a work function of about 5.0 eV is required. A replacement gate integration scheme known in the prior art typically requires the formation of a gate dielectric after source/zent activation annealing. The use of a surname to expose a semiconductor surface prior to forming a gate dielectric (typically comprising a 鬲k dielectric material) typically results in interface defects between the channel and the gate dielectric. In addition, two different metal gate materials are typically formed with accompanying lithographic patterning steps and planarization steps. Many prior art alternative gate integration schemes require two separate steps in forming the gate dielectric. Thus, while the alternative gate integration scheme known in the prior art increases the selectivity of the material of the metal gate electrode, the processing complexity and cost increase is much greater than the typical CM0S process flow. In view of the above, there is a need for a semiconductor structure that provides the functional advantages of a CMO S transistor including a metal gate electrode having a dual work function while avoiding damage and interface between the gate dielectric and the via. 200950002 In addition, there is a need for a method of fabricating such a semiconductor structure that simultaneously minimizes processing complexity and cost savings over conventional CMOS integration schemes. SUMMARY OF THE INVENTION In order to meet the above needs, the present invention provides a semiconductor structure including a transistor having a metal germanide electrode and another transistor having a metal telluride-telluride alloy electrode, and providing the semiconductor structure. method. In the present invention, a P-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning a gate dielectric layer, a thin germanium layer, and a germanium alloy layer. After forming the source/drain regions and the gate spacers, the tantalum alloy portion is removed from the = pole stack. A dielectric layer is formed and patterned to cover the NFET gate electrode while exposing the thin portion of the pFET. The germanium is selectively deposited on the surface of the semiconductor including the exposed germanium portion. The metal layer and the deposited metal layer are removed and reacted with the underlying semiconductor material to form a metallization of the gate electrode of the NFET, while forming a metal telluride-telluride alloy of the gate electrode of the butt. In order to reduce processing complexity and cost, a self-aligned metal gate treatment scheme using a sacrificial layer is disclosed. The sacrificial layer includes a ruthenium containing layer. This process allows high temperature processing of source and drain activation annealing without regard to the reaction between the high-k gate dielectric and the metal gate material. The self-aligned telluride moiety comprises a fully deuterated metal telluride. The gate is electrically charged to the 200950002 pole and formed on one type of transistor (typically an n-type field effect transistor); and the self-aligned metal telluride·etellide The alloy portion includes a fully metallized telluride-telluride alloy gate electrode formed on another type of transistor. The present invention avoids the full implementation of the replacement gate processing step such that the interface between the channel region and the gate dielectric is protected. In addition, an additional advantage of providing a self-aligned metal gate structure is provided. Although only a metal layer for metallization is deposited, different metallization materials can be formed between the p-type and n-type field effect transistors. In addition, passivation of the complementary MOS device can be easily accomplished because hydrogen diffuses in the bismuth and the sulphide-telluride alloy. According to an aspect of the invention, a method of forming a semiconductor structure includes: forming a first gate dielectric on a first semiconductor portion of a semiconductor substrate and a second gate dielectric a second semiconductor portion of the semiconductor substrate; forming a first germanium portion on the first gate dielectric and a second germanium portion on the second gate dielectric; forming a gate side germanium Part of the second germanium portion, and no germanium deposited on the first germanium portion; and directly forming a first gate electrode including a metallithium on the first gate dielectric and directly forming A second gate electrode comprising a metal telluride-telluride alloy is on the second gate dielectric. In a specific embodiment, the method further includes forming a first disposable yoke portion on the first 矽 portion and a second 锗 锗 200950002 portion on the second 矽 portion, wherein the The first and second disposable ruthenium containing moieties comprise from about 25% to about 100% of the ruthenium atom. Preferably, the first and second disposable ruthenium containing moieties have an atomic concentration of between about 50% and 100%. In another embodiment, the first and second disposable ruthenium containing moieties comprise niobium or a ruthenium alloy having the same rhodium concentration. In still another embodiment, the method further includes forming a first gate spacer on the sidewall of the first buffer portion and the first disposable germanium portion and a second gate spacer The second side portion and the side wall of the second disposable gargle portion. In still another embodiment, the method additionally includes removing the first and second disposable germanium portions without removing the first and second germanium portions 0. In still another embodiment, the The method additionally includes directly forming a dielectric mask layer on the first and second turns portions after the removing the first and second disposable germanium-containing portions. In still another embodiment, the method additionally includes patterning the dielectric mask layer, wherein after the patterning, the first germanium portion is covered with the dielectric mask layer, and wherein the patterning is performed Thereafter, the second portion is exposed. 200950002 In a further embodiment 'the gate side or - bismuth alloy. The gate side contains a bismuth portion 2;: at about 5% S 100%, the atomic concentration: the soil degree can be substantially in the middle portion. The gate side of the product contains a misalignment method, and a tantalum-containing material deposition process is used to form the gate-side germanium portion, which is on the semiconductor surface during the selection=material deposition process. 2 Deposit a tantalum or niobium alloy. In a further embodiment, the method further comprises: depositing a metal layer on the first portion and the gate portion, and metallizing the first portion and The gate side comprises a stack of germanium portions and the second hair portion. In still further embodiments, a first gate electrode comprising a metal telluride is directly formed on the first gate dielectric and a second gate comprising a metal-lithium-telluride alloy is directly formed The pole electrode is on the first free dielectric. In still another embodiment, the first gate electrode has a component MSi at a interface with the first gate dielectric and the second gate electrode is dielectrically coupled to the second gate One of the interfaces has a composition of MGexSiw, wherein x is between about 0.05 and about 〇.85, and Μ is an elemental metal or a metal having a composition of AyBi-y 200950002. Gold, where y is between 0 To 1, and A is a first elemental metal and B is a second elemental metal. In still another embodiment, the method further includes: forming a first gate spacer on the first germanium portion and a first two gate spacer on the second germanium portion; and forming a first A source region and a first drain region are in the first semiconductor portion and a second source region and a second drain region are in the second semiconductor portion. In still another specific embodiment, after the patterning, the first source region and the first drain region are covered by the dielectric mask layer, and after the patterning, the second portion is exposed a source region and the second drain region. In still another embodiment, the method further includes: directly forming a gate side germanium portion on the second germanium portion; directly forming a source side germanium portion on the second source region; And directly forming a drain-side germanium portion on the second drain region, wherein depositing germanium or a germanium-containing alloy does not directly occur in the first germanium portion, the first source region, and the first On the polar zone. In still another embodiment, the method further includes: directly forming a gate dielectric layer on the semiconductor substrate; directly forming a layer of austenite containing alumite or polycrystalline slab at the gate Forming a layer of germanium containing 200950002 containing germanium atoms at a concentration of about 25% or more on the dielectric layer; and patterning the germanium-containing layer and the germanium layer, wherein the first layer is formed by the germanium layer And a second disposable portion, and a first disposable yoke portion is formed on the first ridge portion and a second disposable ytterbium portion is formed on the second diaper portion. According to another aspect of the present invention, a semiconductor structure is provided, comprising: a first field effect transistor having a first gate dielectric and a first directly on the first gate dielectric a gate electrode, wherein the first gate electrode comprises a metal hardened material and has a first thickness; and a second field effect transistor has a second gate dielectric and a direct current in the second gate a second gate electrode on the dielectric material, wherein the second gate electrode comprises a metal cleavage-deformed alloy and has a second thickness, wherein the second thickness is greater than the first thickness. In one embodiment, the semiconductor structure further includes: a source side metal germanide portion directly on a source region of the first field effect transistor and comprising the metal germanide and having a third thickness a 侧-side metal ruthenium portion directly on the first and second regions of the first field effect transistor and comprising the metal lanthanide and having the third thickness; a source side metal-decomposition-telluride alloy a portion directly on a source region of the second field effect transistor and comprising the metal telluride-telluride alloy and having a fourth thickness; and 200950002 a drain side metal telluride-telluride alloy portion Directly located on a drain region of the second field-transisting crystal and comprising the metal-lithium-telluride alloy and having the fourth thickness, wherein the fourth thickness is greater than the third thickness. In another embodiment, the metal cerium compound and the metal sulphate-telluride alloy are derived from a metal forming a metal mono-halide and a metal single telluride. For example, the metal layer can comprise nickel, platinum, palladium, cobalt, or a combination thereof. In still another specific embodiment, the ratio of the second thickness to the first thickness is between 1.0 and about L30. The ratio of the second thickness to the first thickness can range from about 1.1 to about 1.30. In still another embodiment, the semiconductor structure further comprises: a gate spacer adjacent to the first gate electrode; a second gate spacer laterally adjacent to the second gate electrode; a second dielectric process (M0L) dielectric layer, longitudinally adjacent to an inner side of the first interrogation electrode, a top surface of the second=electrode, the first-gate interpole|earth, and the first gate The inner side wall of the spacer. - Gate 2 (8) is specifically implemented to emit 'reading the first gate electrode and the first part of the section] VlGe q* shell, the surface of the surface has one element - elemental metal with a medium 0. 05 to about 〇.85, and M For - 'The metal alloy with a knife, where 200950002 y is between 0 and prime metal. And the first elemental metal and the second element are two second electrodes. The two gate electrodes may have a longitudinally graded composition, wherein the distance of the germanium with the polar dielectric increases. Alternatively, χ may be substantially constant throughout the first gate electrode. In still another embodiment, the total amount of 岔:2 在 in the first open electrode is substantially the same as the total amount of hair per morning area in the second gate electrode. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. The present invention relates to a complementary metal oxide semiconductor (CMOS) transistor having a metal telluride electrode and a metal-salt-telluride alloy electrode, and a method of fabricating the same, which will now be described in detail with reference to the accompanying drawings. Note %, the reference numbers indicate similar and corresponding components. Referring to FIG. 1, an exemplary semiconductor structure in accordance with the present invention includes a vehicle

Μ 200950002 導體基板8，其含有操作基板10、埋藏絕緣層20、及 包=第一半導體部分30A、第二半導體部分30B、及淺— 溝渠隔離結構32的頂部半導體層。第—半導體部分3〇A 及第二基板半導體部分3〇B包含半導體材料，其可選自 (但不限於）：矽、鍺、矽-鍺合金、矽碳合金、矽-鍺-碳 合金、砷化鎵、砷化錮、磷化銦、III-V化合物半導體 材料、II-VI化合物半導體材料、有機半導體材料、及 其他化合物半導體材料。例如，半導體材料可包含矽。 本發明係針對第一及第二半導體部分(30A、30B)包含矽 的情況加以說明，但在此亦明確考慮以下具體實施例： 第一及第二半導體部分(3〇A、3〇B)包含另一半導體材料 ^包含該材料之金屬半導體合金及直接在第一及第二 半導體部分(30A、30B)上的金屬。 較佳是’第一及第二半導體部分(3〇a、30B)之每一 者為單結晶。半導體基板8可以是塊狀基板、絕緣體上 半導體(SOI)基板、或以淺溝渠隔離結構32隔開第一半 導體部分30A及第二半導體部分30B的混合基板。第 及/或第二半導體部分可具有内建應力，以提高電荷 載子的遷移率。雖然本發明就絕緣體上半導體^(^^基 板加以說明’但在此亦明確考慮在塊狀基板或混合基板 上實施本發明。 操作基板10可包含：半導體材料(諸如矽）、介電 材料（諸如石英、玻璃、藍寶石等）、或金屬材料(諸如元 素金屬或金屬合金）。埋藏絕緣層20包含絕緣材料，其 200950002 具有介電常數低於第一及第二半導體部分(3〇a、3〇B) 中半導體材料的介電常數。埋藏絕緣層20可包含氧化 矽或氮化矽。 第一半導體部分30A及/或第二半導體部分30B可 摻雜以電摻雜物，諸如B、Ga、In、P、As、Sb、或其 組合。在第一及第二半導體部分(3〇A、30B)都掺雜的情 況下，第一及第二半導體部分(3〇A、30B)可具有相同或 相反的摻雜類型。本發明說明假設第一半導體部分3〇A 具有P型摻雜及第二半導體部分3〇B具有n型摻雜。然 而’在此亦明確考慮以下具體實施例：第一半導體部分 30Α具有η型摻雜及第二半導體部分3〇]3具有ρ型摻 雜’或第一及第二半導體部分(30Α、3〇Β)中至少—個實 質上為本質半導體。如果第一及第二半導體部分(30Α、 30Β)被摻雜’則第一及/或第；半導體部分(3〇α、3〇β) 的推=物濃度可介於約1.0xl014/cm3至約 ’及較佳是介於約i 〇xl〇15/cm3至約 1’OxlO /cm，但在此亦明確考慮較低及較高的摻雜物 濃度。 閘極介電層40L直接形成於第一半導體部分3〇a 的頂面及第二半導體部分3GB的頂面上。閘極介電層 可包含基於氧化矽的介電層，諸如氧化矽（Si〇2)、 氮，化矽（Sl〇xNy)、或其組合。SiOxNy的X值可介於〇 至、’、勺2，及SiOxNy的y值可介於〇至約〜3。或者，閘 極”電層40L可包含稱為「高k閘極介電材料」的介電 200950002 - 金屬氧，物材料。介電金屬氧化物材料的非限制性範例 包括.氧化銓(Hf〇2)、氧化結(Zr02)、氧化銘(ai2〇3)、 氧化鑭(La2〇3)、氧化釔(γ2〇3)、氧化鈦(ή〇2)、鈦酸錯 (SrTiOs)、鋁酸鑭(LaA1〇3)、氧化釔(γ2〇3)、其矽酸鹽、 其合金、及其非化學計量變體。閘極介電層4〇]L可具有 厚度介於約0.8nm至約2〇nm，及可具有等效氧化物厚 度(EOT)介於約〇·8 nm至約1〇 nm。 利用本技術中已知的方法，包括：低壓化學氣相沈 積(LPCVD)、快速熱化學氣相沈積(j^cvd)、電聚加強 化學氣相沈積(PECVD)、物理氣相沈積(PVD)等，在閘 極介電層40L上形成矽層42L。矽層42L包含矽’且可 含有或不含有電摻雜物，諸如B、Ga、In、P、As、Sb、 或其組合。矽層42L可以是非晶、多晶、或微晶。矽層 42L的厚度可介於約5 nm至約40 nm，且通常介於約 10 nm至約25 nm，但在此亦明確考慮較薄及較厚的厚 度。 、一 利用本技術t已知的方法’包括以上各種化學氣相 沈積(CVD)方法及物理氣相沈積(pvd)，在碎層42上形 成含鍺層44L。含鍺層44L含有鍺原子濃度介於約25% 至100% ’及較佳是介於約50%至1〇〇%。含錯層44L 可以是非晶、多晶、或微晶。含錯層44L的厚度可介於 約1 nm至約160nm’且通常介於約5 nm至約1〇〇 nm， 但在此亦明確考慮較薄及較厚的厚度。 200950002 示範性半導體結構包含第一裝置區100及第二裝 置區200。第一裝置區1〇〇含有第一半導體部分3〇八及 在第一半導體部分30A内及在其上存在或形成的其他 元件。第二裝置區200含有第二半導體部分3〇B及在第 二半導體部分30B内及在其上存在或形成的其他元 件。在本發明中，其後在第一裝置區1〇〇中形成η型金 氧半導體場效電晶體(NMOSFET或NFET)，及其後在第 二裝置區200中形成ρ型金氧半導體場效電晶體 (PMOSFET 或 PFET) ° 參考圖2 ’微影圖案化含錯層44L、石夕層42L、及 閘極介電層40L ’以在第一裝置區1〇〇中形成第一閘極 介電質40Α、第一矽部分42Α、第一可棄式含鍺部分44Α 組成的第一堆疊，及在第二裝置區200中形成第二閘極 介電質40Β、第二矽部分42Β、及第二可棄式含鍺部分 44Β組成的第二堆疊。例如，光阻（未顯示）可塗布於含 鍺層44L的頂面上、經過曝光、及顯影，以用光阻的其 餘部分形成微影圖案。其後利用異向性（anisotropic)姓 刻’諸如反應離子钱刻，將圖案轉印至由含錯層44L、 砍層42L、及閘極介電層40L組成的堆疊。在#刻三個 不同層（44L、42L、40L)期間’可視需要改變在異向性 钱刻處理步驟中的姓刻化學。在蝕刻閘極介電層40L期 間採用的独刻化學較佳是不會餘刻第一及第二半導體 部分(30A、30B)的半導體材料。每一部分(4〇a、40B、 42A、42B、44A、或44B)的高度實質上相同於從中形 成該部分之層（40L、42L、或44L)的厚度。第一可棄式 200950002 - 含鍺部分44A及第二可棄式含鍺部分44B因在後續處 理步驟中移除而為「可棄式」。 參考圖3，在示範性半導體結構中形成源極及汲極 區及閘極間隔物。明確地說，在第一遮罩離子植入步驟 中’用第一植入遮罩（未顯示）遮罩第二裝置區200，及 第一閘極介電質40Α、第一矽部分42Α、及第一可棄式 含鍺部分44Α的第一堆疊用作植入遮罩，將η型摻雜 物植入第一半導體部分30Α具有ρ型摻雜的部分。可 以在形成第一閘極間隔物52之前及在之後，採用多於 一個遮罩離子植入步驟，以形成鄰接第一閘極介電質 40Α的源極及汲極延伸部分（未另外標示）及鄰接埋藏絕 緣部分20的深源極及汲極部分（未另外標示），用於加 強將形成之NMOSFET的效能。第一半導體部分3〇α 的一個植入部分構成具有η型掺雜的第一源極區36α。 第一半導體部分30Α的另一楂入部分構成具有η型摻 雜的第一汲極部分38Α。第一源極部分36Α及第一汲極 ( 部分38八的摻雜物濃度可介於約1.(^1019/(^13至約 1.0xl021/cm3，及較佳是介於約丨〇xl〇2〇/cm3至約 5.0xl〇2G/cm3 ’但在此亦明確考慮較低及較高的摻雜物 濃度。第一半導體部分30A在第一源極區36A及第一 汲極區38A之間的未植入部分構成具有p型摻雜的第 一主體區34A。 同樣地，在第二遮罩離子植入步驟中，用第二植入 遮罩（未顯示）遮罩第一裝置區’及第二閘極介電質 200950002 40B、第二石夕部分42B、及第二可棄式含鍺部分44B的 第二堆疊用作植入遮罩，將P型摻~雜物植入第二半導體 部分30B具有η蜜摻雜的部分。可以在形成第二閘極間 隔物52’之前及在之後，採用多於一個遮罩離子植入步 驟’以形成鄰接第二閘極介電質40Β的源極及汲極延伸 部分(未另外標示）及鄰接埋藏絕緣部分20的深源極及 没極部分（未另外標示），用於加強將形成之PMOSFET 的效能。第二半導體部分30Β的一個植入部分構成具有 Ρ型摻雜的第二源極區36Β。第二半導體部分30Β的另 一植入部分構成具有ρ型摻雜的第二汲極部分38Β。第 二源極部分36Β及第二汲極部分38Β的摻雜物濃度可 介於約1.0xl019/cm3至約1.0xl021/cm3，及較佳是介於 約1.0xl02〇/cm3至約5,Oxl〇20/cm3，但在此亦明確考慮 較低及較高的摻雜物濃度。第二半導體部分30B在第二 源極區36B及第二；；：及極區38B之間的未植入部分構成 具有η型摻雜的第二主體區34B。 利用介電材料層（未顯示）的保形沈積（c0nf0rmal deposition)及接著進行異向性蝕刻’形成第一閘極間隔 物52及第二閘極間隔物52,。第一閘極間隔物52及第 二閘極間隔物52'通常包含相同材料，如氧化石夕、氮氧 化物矽、氮化矽、或其組合。在鄰接半導體基板8的基 部所測量之第一及第二閘極間隔物（52、52，)的橫向厚度 可由在第一或第二閘極介電質（4〇a或40B)的邊緣及其 後直接形成於不同源極及汲極區（36A、38A、36B、或 38B)之金屬半導體合金部分的邊緣之間的所要偏移來 70 i S1 200950002 - 決定。在一組用以形成不同源極及汲極延伸區f来另外 顯示）的遮-罩離子植人步驟及另一 介電層2G之頂面的不同深源㈣及 冰及極區（未另外顯示）㈣轉子植人步驟之間，形成 第一及第二閘極間隔物(52、52，）。 第一閘極間隔物52在第一矽部分42八及第一可棄 式含鍺部分44A之間的介面上方延伸。同樣地，第^ 閘極間隔物52’在第二矽部分42B及第二可棄式含鍺部 分44B之間的介面上方延伸。因此，第—閘^間隔物 52的内部侧壁橫向鄰接第一可棄式含鍺部分44人及第 二閘極間隔物52,的内部侧壁橫向鄰接第二可棄式含鍺 部分44B。第一閘極間隔物52及第二閘極間隔物52, 可具有實質上相同的高度，且可向上延伸到達第一或第 二可棄式含鍺部分(44A或44B)的頂面。 ’ 參考圖4，移除第一及第二可棄式含鍺部分(44A、 44B)而不移除第一及第二矽部分(42A、42B)、第一及第 二閘極間隔物（52、52，）、淺溝渠隔離結構32及半導體 基板8中的不同源極及汲極區（36A、38A、36B、3犯）。 可以採用乾式蝕刻或濕式蝕刻。約25%或更高之相對高 的鍺原子濃度使得該第一及第二可棄式含鍺部分 (44A、=B)可蝕刻，而不蝕刻包含鍺或具有鍺原子濃度 小於=5%(及較佳是小於1%)之示範性半導體結構的其 露表面。針對此化學性質可以採用的示範性蝕刻化 學是H2〇:H2〇2:I1F比例4〇:1:1的混合物，其钱刻含錯 200950002 - 材料而不钱刻不含有錄的材料。可以採用任何其他移除 鍺或含鍺化合物而不移除不含鍺或鍺濃度低（通常低於 5%)之化合物的蝕刻化學。在選擇性蝕刻結束時，移除 第一石夕部分42A的頂面及第二矽部分42B的頂面。 參考圖5 ’在第一及第二石夕部分(42A、42B)、第一 及第一閘極間隔物(52、52)、在半導體基板$中的淺溝 渠隔離結構32及不同源極及及極區（36A、38A、36B、 38B)上形成介電遮罩層60。介電遮罩層6〇包含介電氧 ' 化物或介電氮化物。例如，介電遮罩層00可包含氧化 矽。可以利用電漿加強化學氣相沈積(PECVD)、低壓化 學氣相沈積(LPCVD)、快速熱化學氣相沈積(RTcvD)、 高密度電漿化學氣相沈積(HDPCVD)、或其他已知的沈 積技術’形成介電遮罩層60。較佳是，形成介電遮罩 層60所採用的沈積製程是保形的。介電遮罩層的的厚 度可介於約5 nm至約100 nm，及較佳是介於約1〇 至50 nm，但在此亦考慮較薄及較厚的厚度。 ''一 執行活化退火以活化此時出現在第一源極及汲極 區（36A、38A)及第二源極及汲極區（36B、38B)中的摻雜 物。佔用間隙位置的摻雜物原子移至取代位置，以「活 化」摻雜物’ ，使捧雜物原子能夠當作提供電 真 能帶結構之電荷載子的受體離子，或作為提供電子為 ，何載子的施體離子。還有，在活化退火期間，加埶^ 第一源極及汲極區（36A、38A)及第二源極及汲極、區 (36B 38B)中的任何韓气損壞。可視需要設定活化退火 200950002 的溫度及持續時間，以防止對第一及第二閘極介 (40A、40B)的任何成分造成損壞。對於基於氧化矽的 極介電質，可以採用高達1，15〇ΐ的溫度，而對於包: 高k閘極介電材料的閘極介電質，可以採用較低^溫 度。用於包含高k閘極介電材料之閘極電極的典型退2 溫度介於約800 °C至約1，050 〇C，及通常介於7約85〇 至約 1，000 °c。 參考圖6，將光阻67塗布於介電遮罩層6〇及使其 微影圖案化以覆蓋第一裝置區100，同時暴露第二穿置 區200。利用乾式蝕刻或濕式蝕刻的蝕刻，移除介^遮 罩層60的暴露部分。蝕刻可以是異向性蝕刻或實質上 等向性（isotropic)蝕刻，較佳是，蝕刻不會蝕刻第二矽 部分42B。較佳是，蝕刻也不會移除第二源極區36B及 第二汲極區38B。在暴露第二矽部分42B、 分細、及第二没極部分通之後，可以如== 除光阻67。可以視需要執行合適的表面清洗。 參考圖7，利用不沈積於介電質表面的沈積製程， 在暴露的半導體表面上形成含鍺部分。使至少一'個為鍺 沈積之前驅物的反應物流進含有或沒有另一半導體材 料之另一反應物的化學氣相沈積(CVD)反應器。例如， 將GeH4 Ge2H6、或另一錯前驅氣體提供至不含半導 體材料之任何其他反應物的CVD反應器中，以形成為 具有鍺濃度100%之含鍺部分的鍺部分。或者，可將 GeHU、Ge^6、或另一鍺前驅氣體提供至CV]D反應器 200950002 - 中’反應器中含有半導體材料的另一反應物，諸如Μ 200950002 Conductor substrate 8 comprising a handle substrate 10, a buried insulating layer 20, and a top semiconductor layer including a first semiconductor portion 30A, a second semiconductor portion 30B, and a shallow-drain isolation structure 32. The first semiconductor portion 3A and the second substrate semiconductor portion 3B comprise a semiconductor material, which may be selected from, but not limited to, germanium, germanium, bismuth-tellurium alloy, germanium carbon alloy, germanium-tellurium-carbon alloy, Gallium arsenide, arsenic arsenide, indium phosphide, III-V compound semiconductor material, II-VI compound semiconductor material, organic semiconductor material, and other compound semiconductor materials. For example, the semiconductor material can comprise germanium. The present invention is described with respect to the case where the first and second semiconductor portions (30A, 30B) contain germanium, but the following specific embodiments are explicitly considered here: the first and second semiconductor portions (3A, 3B) A semiconductor material comprising a metal semiconductor alloy comprising the material and a metal directly on the first and second semiconductor portions (30A, 30B) is included. Preferably, each of the first and second semiconductor portions (3a, 30B) is a single crystal. The semiconductor substrate 8 may be a bulk substrate, a semiconductor-on-insulator (SOI) substrate, or a mixed substrate in which the first semiconductor portion 30A and the second semiconductor portion 30B are separated by a shallow trench isolation structure 32. The first and/or second semiconductor portion can have built-in stress to increase the mobility of the charge carriers. Although the present invention is described in terms of a semiconductor-on-insulator substrate, it is explicitly contemplated to implement the present invention on a bulk substrate or a hybrid substrate. The handle substrate 10 may include: a semiconductor material (such as germanium), a dielectric material ( Such as quartz, glass, sapphire, etc., or a metal material such as elemental metal or metal alloy. The buried insulating layer 20 comprises an insulating material, and its 200950002 has a lower dielectric constant than the first and second semiconductor portions (3〇a, 3) 〇B) The dielectric constant of the semiconductor material. The buried insulating layer 20 may comprise hafnium oxide or tantalum nitride. The first semiconductor portion 30A and/or the second semiconductor portion 30B may be doped with an electrical dopant such as B, Ga. , In, P, As, Sb, or a combination thereof. In the case where both the first and second semiconductor portions (3A, 30B) are doped, the first and second semiconductor portions (3A, 30B) may Having the same or opposite doping type. The present invention assumes that the first semiconductor portion 3A has a P-type doping and the second semiconductor portion 3B has an n-type doping. However, the following specific embodiments are also explicitly considered herein. : First Semiconductor Division 30Α has an n-type doping and the second semiconductor portion 3〇]3 has a p-type doping' or at least one of the first and second semiconductor portions (30Α, 3〇Β) is substantially an intrinsic semiconductor. The second semiconductor portion (30Α, 30Β) is doped 'the first and/or the second; the semiconductor portion (3〇α, 3〇β) may have a push concentration of between about 1.0xl014/cm3 to about' and Preferably, it is between about 〇xl 〇15/cm3 to about 1'OxlO/cm, but a lower and higher dopant concentration is also explicitly considered here. The gate dielectric layer 40L is formed directly on the first semiconductor portion. The top surface of 3〇a and the top surface of the second semiconductor portion 3GB. The gate dielectric layer may comprise a yttria-based dielectric layer such as yttrium oxide (Si〇2), nitrogen, bismuth (Sl〇xNy) Or a combination thereof. The X value of SiOxNy may be between 〇 to, ', spoon 2, and y value of SiOxNy may range from 〇 to about 〜3. Alternatively, the gate "electric layer 40L may include a high-k gate. Dielectric materials" dielectric 200950002 - Metal oxygen, material materials. Non-limiting examples of dielectric metal oxide materials include: yttrium oxide (Hf 〇 2), oxidized junction (Zr02), oxidized Ming ( Ai2〇3), yttrium oxide (La2〇3), yttrium oxide (γ2〇3), titanium oxide (ή〇2), titanic acid (SrTiOs), lanthanum aluminate (LaA1〇3), yttrium oxide (γ2〇) 3), its bismuth salt, its alloy, and its non-stoichiometric variations. The gate dielectric layer 4〇]L may have a thickness of from about 0.8 nm to about 2 〇 nm, and may have an equivalent oxide thickness (EOT) is between about 8 nm and about 1 〇 nm. Methods known in the art include: low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (j^cvd), electropolymerization Enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), etc., forming a germanium layer 42L on the gate dielectric layer 40L. The ruthenium layer 42L contains 矽' and may or may not contain an electrical dopant such as B, Ga, In, P, As, Sb, or a combination thereof. The ruthenium layer 42L may be amorphous, polycrystalline, or microcrystalline. The thickness of the germanium layer 42L may range from about 5 nm to about 40 nm, and is typically between about 10 nm and about 25 nm, although thinner and thicker thicknesses are also explicitly considered herein. A method comprising the present technology t includes the above various chemical vapor deposition (CVD) methods and physical vapor deposition (pvd) to form a germanium-containing layer 44L on the fracture layer 42. The germanium containing layer 44L contains a germanium atom concentration of from about 25% to 100% 'and preferably from about 50% to about 1%. The misaligned layer 44L may be amorphous, polycrystalline, or microcrystalline. The thickness of the fault-containing layer 44L may range from about 1 nm to about 160 nm' and is typically between about 5 nm and about 1 〇〇 nm, although thinner and thicker thicknesses are also explicitly contemplated herein. The 200950002 exemplary semiconductor structure includes a first device region 100 and a second device region 200. The first device region 1 〇〇 contains the first semiconductor portion 〇8 and other elements present or formed within the first semiconductor portion 30A and thereon. The second device region 200 contains a second semiconductor portion 3B and other components present or formed within and on the second semiconductor portion 30B. In the present invention, an n-type MOS field effect transistor (NMOSFET or NFET) is subsequently formed in the first device region 1 ,, and then a p-type MOS field effect is formed in the second device region 200. Transistor (PMOSFET or PFET) ° Referring to FIG. 2 ' lithographically patterned dislocation layer 44L, lithographic layer 42L, and gate dielectric layer 40L' to form a first gate dielectric in the first device region 1 〇〇 a first stack of 40 电, a first 矽 portion 42 Α, a first disposable 锗-containing portion 44 ,, and a second gate dielectric 40 Β, a second 矽 portion 42 Β in the second device region 200, and A second stack of second disposable ruthenium containing portions 44 。. For example, a photoresist (not shown) may be applied to the top surface of the ruthenium containing layer 44L, exposed, and developed to form a lithographic pattern with the remainder of the photoresist. Thereafter, the pattern is transferred to a stack composed of the stagger-containing layer 44L, the chopped layer 42L, and the gate dielectric layer 40L by using an anisotropic surname, such as a reactive ion. During the three different layers (44L, 42L, 40L), the surname chemistry in the anisotropic processing step can be changed as needed. The unique chemistry employed during the etching of the gate dielectric layer 40L is preferably a semiconductor material that does not leave the first and second semiconductor portions (30A, 30B). The height of each portion (4〇a, 40B, 42A, 42B, 44A, or 44B) is substantially the same as the thickness of the layer (40L, 42L, or 44L) from which the portion is formed. The first disposable type 200950002 - the defective portion 44A and the second disposable containing portion 44B are "disposable" because they are removed in the subsequent processing steps. Referring to Figure 3, source and drain regions and gate spacers are formed in an exemplary semiconductor structure. Specifically, in the first mask ion implantation step, 'the second device region 200 is masked with the first implant mask (not shown), and the first gate dielectric 40 Α, the first 矽 portion 42 Α, The first stack of the first disposable germanium containing portion 44 is used as an implant mask, and the n-type dopant is implanted into the first semiconductor portion 30 and has a p-type doped portion. More than one mask ion implantation step may be employed before and after forming the first gate spacer 52 to form a source and drain extension adjacent to the first gate dielectric 40 ( (not otherwise labeled) And the deep source and drain portions of the buried insulating portion 20 (not otherwise labeled) are used to enhance the performance of the NMOSFET to be formed. An implant portion of the first semiconductor portion 3?? constitutes a first source region 36? having an n-type doping. The other intrusion portion of the first semiconductor portion 30A constitutes a first drain portion 38A having an n-type doping. The dopant concentration of the first source portion 36 and the first drain (the portion 38 8 may be between about 1. (1019/(^13 to about 1.0xl021/cm3, and preferably between about 丨〇xl) 〇2〇/cm3 to about 5.0xl〇2G/cm3′ but lower and higher dopant concentrations are also explicitly considered here. The first semiconductor portion 30A is in the first source region 36A and the first drain region 38A. The unimplanted portion therebetween constitutes a first body region 34A having a p-type doping. Likewise, in the second mask ion implantation step, the first device is masked with a second implant mask (not shown) The second stack of the region 'and the second gate dielectric 200950002 40B, the second stone portion 42B, and the second disposable germanium portion 44B is used as an implant mask to implant the P-type dopant The second semiconductor portion 30B has a η honey doped portion. More than one mask ion implantation step ' may be employed before and after forming the second gate spacer 52 ′ to form an adjacent second gate dielectric 40 Β source and drain extensions (not otherwise indicated) and deep source and immersed portions of adjacent buried insulation section 20 (not otherwise marked) are used to enhance The performance of the formed PMOSFET. One implant portion of the second semiconductor portion 30A constitutes a second source region 36Β having a Ρ-type doping. The other implant portion of the second semiconductor portion 30Β constitutes a second portion having a p-type doping The drain portion 38 Β. The dopant concentration of the second source portion 36 汲 and the second drain portion 38 可 may range from about 1.0 x l 019 / cm 3 to about 1.0 x 10 21 /cm 3 , and preferably about 1.0 x 10 〇 / cm 3 Up to about 5, Oxl 〇 20/cm3, but lower and higher dopant concentrations are also explicitly considered herein. The second semiconductor portion 30B is in the second source region 36B and the second;; and the polar region 38B The inter-implanted portion constitutes a second body region 34B having an n-type doping. The first gate interval is formed by conformal deposition of a dielectric material layer (not shown) followed by anisotropic etching. The second gate spacer 52 and the second gate spacer 52', the first gate spacer 52 and the second gate spacer 52' generally comprise the same material, such as oxidized oxide, lanthanum oxynitride, tantalum nitride, or a combination thereof. First and second gate spacers (52, 52) measured at a base adjacent to the semiconductor substrate 8. , the lateral thickness of the substrate can be formed directly at the edge of the first or second gate dielectric (4〇a or 40B) and thereafter at different source and drain regions (36A, 38A, 36B, or 38B). The desired offset between the edges of the metal-semiconductor alloy portion is determined by 70 i S1 200950002 - the mask-shield implant step and another in a set of different source and drain extensions f for additional display) First and second gate spacers (52, 52) are formed between different deep sources (4) of the top surface of the dielectric layer 2G and ice and polar regions (not shown) (4) between the rotor implanting steps. The first gate spacer 52 extends over the interface between the first meander portion 42 and the first disposable germanium containing portion 44A. Similarly, the gate spacer 52' extends over the interface between the second turn portion 42B and the second disposable germanium portion 44B. Therefore, the inner side wall of the first gate spacer 52 laterally adjoins the first disposable damming portion 44 and the second gate spacer 52, and the inner side wall laterally abuts the second disposable ytterbium containing portion 44B. The first gate spacer 52 and the second gate spacer 52 may have substantially the same height and may extend upwardly to the top surface of the first or second disposable germanium containing portion (44A or 44B). Referring to FIG. 4, the first and second disposable germanium containing portions (44A, 44B) are removed without removing the first and second germanium portions (42A, 42B), the first and second gate spacers ( 52, 52,), shallow trench isolation structure 32 and different source and drain regions (36A, 38A, 36B, 3) in the semiconductor substrate 8. Dry etching or wet etching can be employed. A relatively high concentration of germanium atoms of about 25% or higher allows the first and second disposable germanium-containing moieties (44A, =B) to be etched without etching germanium or having germanium atomic concentrations less than = 5% ( And preferably less than 1%) of the exposed surface of an exemplary semiconductor structure. An exemplary etch chemistry that can be employed for this chemistry is a mixture of H2 〇: H2 〇 2: I1F ratio 4 〇: 1:1, which is erroneously included in the 200950002 - material and does not contain the recorded material. Any other etch chemistry that removes ruthenium or ruthenium containing compounds without removing compounds that are low in ruthenium or osmium (typically less than 5%) may be employed. At the end of the selective etching, the top surface of the first day portion 42A and the top surface of the second side portion 42B are removed. Referring to FIG. 5 'in the first and second day portions (42A, 42B), the first and first gate spacers (52, 52), the shallow trench isolation structure 32 in the semiconductor substrate $, and different sources and A dielectric mask layer 60 is formed on the pads (36A, 38A, 36B, 38B). The dielectric mask layer 6 〇 contains a dielectric oxide or dielectric nitride. For example, dielectric mask layer 00 can comprise ruthenium oxide. Plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTcvD), high density plasma chemical vapor deposition (HDPCVD), or other known depositions may be utilized. The technique 'forms a dielectric mask layer 60. Preferably, the deposition process employed to form the dielectric mask layer 60 is conformal. The thickness of the dielectric mask layer can range from about 5 nm to about 100 nm, and preferably from about 1 至 to 50 nm, although thinner and thicker thicknesses are also contemplated herein. The activation of the activation is performed to activate the dopants present in the first source and drain regions (36A, 38A) and the second source and drain regions (36B, 38B). The dopant atoms occupying the gap position are moved to the substitution position to "activate" the dopant, so that the dopant atoms can be used as acceptor ions for providing charge carriers of the electrical true band structure, or as electron supply, He Zizi's donor ion. Also, during the activation anneal, any of the first source and drain regions (36A, 38A) and the second source and drain regions (36B 38B) are damaged. The temperature and duration of the activation annealing 200950002 can be set as needed to prevent damage to any of the first and second gate dielectrics (40A, 40B). For ruthenium oxide based dielectrics, temperatures up to 1,15 Å can be used, while for gate: high-k gate dielectric materials, lower temperatures can be used. A typical back-off temperature for a gate electrode comprising a high-k gate dielectric material is between about 800 ° C and about 1,050 〇C, and typically between about 7 〇 and about 1,000 ° C. Referring to Figure 6, a photoresist 67 is applied to the dielectric mask layer 6 and patterned to cover the first device region 100 while exposing the second via region 200. The exposed portions of the mask layer 60 are removed by etching with dry etching or wet etching. The etching may be an anisotropic etching or a substantially isotropic etching, and preferably, the etching does not etch the second germanium portion 42B. Preferably, the etching does not remove the second source region 36B and the second drain region 38B. After exposing the second germanium portion 42B, the minute portion, and the second pole portion, the photoresist 67 can be removed as ==. A suitable surface cleaning can be performed as needed. Referring to Figure 7, a germanium containing portion is formed on the exposed semiconductor surface using a deposition process that is not deposited on the surface of the dielectric. At least one of the reactants for the deposition of the precursor is passed to a chemical vapor deposition (CVD) reactor with or without another reactant of another semiconductor material. For example, GeH4 Ge2H6, or another wrong precursor gas, is supplied to a CVD reactor containing no other reactants of the semiconductor material to form a ruthenium portion having a ruthenium-containing portion having a ruthenium concentration of 100%. Alternatively, GeHU, Ge^6, or another ruthenium precursor gas may be supplied to the CV]D reactor 200950002 - another reactant in the reactor containing the semiconductor material, such as

SiH4、SiH2Cl2、SiHCl3、SiCl4、S12H6 等，以形成具有 鍺濃度低於100%及含有梦或另一半導體材料^含&部 分0 明破地說’直接在第二石夕部分42B上形成閘極侧含 錯部分62 ’直接在第二源極區36B上形成源極侧含錯 部分66,及直接在第二汲極區上形成汲極侧含鍺部分 68。閘極侧含鍺部分62、源極側含鍺部分66、及及^ 側含鍺部分68包含鍺或矽鍺合金。較佳是，閘極侧含 鍺部分62、源極側含鍺部分66、及汲極侧含鍺部分砧 中的鍺原子濃度介於約5%至100%，較佳是介於^5% 至100%，及更佳是介於約50%至1〇〇%。遍及且橫跨沈0 積之閘極侧含鍺部分62、源極側含鍺部分％、及汲 側含鍺部分68的鍺原子濃度可實質上一致。 / 積同分(62、66、68)的沈積製程為選擇性沈 選擇性含鍺材料沈積製程期間，使鍺或 二如矽鍺合金)沈積於半導體表面上，而非沈 = = 面上。明確地說’沒有任何含鍺材料沈積 卜广、淺溝渠隔離結構32、或第二閘極間 ΐ祕「\介電遮罩層60覆蓋第—石夕部分42Α、 第一源極區36Α、及第—、、另托p qoa a 含錯合金)㈣錢積不會發生奴縣If即’錯或 、、由於在源極側含鍺部分66及汲極侧含鍺部 24 I S3 200950002 二68内的錯濃度約5%或更高，在第二源極區灿及源 錯部分66之間、及在第二汲極區38B及汲極側 分68之間有明顯的晶格失配’尤其如果第二源 第二汲極區38β包切的話。因此，所有間 62、源極側含鍺部分66、錄極侧含鍺 形成為非晶或多晶，即，在第二源極區36b 分66之間或在第二沒極區細及沒極 側3鍺。卩分卵之間沒有磊晶對準。 =含錯，62、源極側含錯部分66、 之每—者具有厚度介SiH4, SiH2Cl2, SiHCl3, SiCl4, S12H6, etc., to form a gate having a germanium concentration of less than 100% and containing a dream or another semiconductor material containing a & part 0 clearly said to form a gate directly on the second stone portion 42B The pole side containing portion 62' directly forms the source side misaligned portion 66 on the second source region 36B, and forms the drain side containing portion 68 directly on the second drain region. The gate side containing portion 62, the source side containing portion 66, and the side containing portion 68 comprise tantalum or niobium alloy. Preferably, the ytterbium atom concentration in the gate side yoke portion 62, the source side yttrium portion 66, and the ytterbium side yttrium portion is between about 5% and 100%, preferably between 5% and 5%. Up to 100%, and more preferably between about 50% and 1%. The concentration of germanium atoms throughout the gate side of the sinker portion 62, the source side germanium containing portion %, and the germanium side germanium containing portion 68 may be substantially uniform. / The deposition process of the same fraction (62, 66, 68) is selective deposition of a tantalum-containing material during the deposition process, so that tantalum or a ruthenium alloy is deposited on the surface of the semiconductor instead of sinking = = surface. Specifically, 'there is no bismuth-containing material deposition, the shallow trench isolation structure 32, or the second gate ΐ 「" \ dielectric mask layer 60 covers the first - the stone part 42 Α, the first source region 36 Α, And the first -, and the other p qoa a with the wrong alloy) (4) the money will not occur in the slave county If the 'wrong or, because the source side contains the 锗 part 66 and the bungee side containing the 24 24 I S3 200950002 II The error concentration in 68 is about 5% or higher, and there is a significant lattice mismatch between the second source region and the source-error portion 66, and between the second drain region 38B and the drain side portion 68. 'especially if the second source second drain region 38β is packaged. Therefore, all of the spaces 62, the source side germanium containing portion 66, and the recording side containing germanium are formed amorphous or polycrystalline, that is, at the second source There is no epitaxial alignment between the 36b points 66 or the second non-polar area and the immersed side. There is no epitaxial alignment between the 卩 eggs. = Error, 62, the source side contains the wrong part 66, each Thickness

麵。源極侧含錄部分66的厚 J 的厚度實質上相同’因為第二源極區二鍺 =有實質上相同的摻雜物濃度。根據 二:定’開極側含鍺部分62的厚度 == 於或不同於源極側含錯部分66的厚度。貫質上相同 參考圖8’利用濕式餘刻或乾式钱 介電遮罩層60而不移除閉極側含鍺部分62 3 錯部分66、没極側含錯部分邰 源極側s (36A、38A)、第一石夕部分42A、及第=及^極及及極區 物(52、52，)。蝕刻可以是異向性或較佳卜:極間隔 等向性。例如，如果介電遮罩層60包含質上是 刻可以是使用氫氟酸⑽)的濕式_。夕，職 —參考圖9,在示範性半導體結構頂側上的暴露表面 200950002 上沈積金屬層70。金屬層70通常在整個半導體基板$ 上為連續的。金屬層70直接接觸第一矽部分42A、第 一源極及没極區（36A、38A)、閘極侧含鍺部分62、及 第二源極及汲極區（36B、38B)。在金屬層7(^在源極侧 含鍺部分66的邊緣及汲極側含鍺部分68 (未顯示）中形成梯級。 '' 較佳是，金屬層70包含形成金屬單矽化物及金屬 單錯化物的金屬。金屬層7G之非限制的示範性材料包 括鎳、舶、把、銘或其組合。可利用物理氣相沈 化學氣相沈積(CVD)、或原子層沈積 ： 7〇。可以卿或非保形的方式沈積金H層 金屬沈積實質上是保形的. 較佳疋， ^金屬化退火期間，藉由與金屬層％中的金屬發 反=使直接接觸金屬層％的不同半導體部分金: 在”於約350。(：至約550 °C的溫声下，利闲下、p、 化，其通常在不含氧的氣體大；如，He? 成氣體）中執行。較佳是，在介於約_ ΐ至 度下執行退火。可以採用固定溫度或不同 約^&加4：=執行敎持續介㈣1秒至 ° - 击推r入 IL的額外退火’進一 溫产ϋ屬化。較佳是，在介於約5G(Kc至約70〇°c的 ίϊ火劍仃額外退火。採用不同溫度之多次退火之多段 b的—個伽切成纽率比金屬魏物或 200950002 . 金屬鍺化物之其他相低的金屬單矽化物相及金屬單鍺 化物相。在金屬化製程之後，利用可以是濕式蝕刻的蝕 刻，移除金屬層70未發生反應的部分（出現在介電質表 面之上，諸如第一及閘極間隔物（52、52’)及淺溝渠隔離 結構32上），而不移除不同的金屬半導體合金部分。典 型用於此濕式蝕刻的蝕刻劑採用王水。 參考圖10,顯示以金屬化製程形成的不同金屬半 導體合金部分，其包括第一閘極電極72、第二閘極電 極82、源極侧金屬矽化物部分76、汲極側金屬矽化物 部分78、源極侧金屬矽化物-鍺化物合金部分86、及汲 極侧金屬矽化物-鍺化物合金部分88。利用金屬層70 藉由完全矽化第一矽部分42A，形成第一閘極電極72， 即，金屬化製程觸及第一矽部分42A在第一矽部分42A 及第一閘極介電質40A間之介面處的材料。第一閘極 電極72因而包含金屬矽化物，且較佳是在閘極介電質 介面處（即，與第一閘極介電質40A的介面）的金屬單矽 r 化物。在此將第一閘極電極72的厚度稱為第一厚度tl。 利用金屬層70藉由完全金屬化閘極侧含鍺部分62及第 二矽部分42B，形成第二閘極電極72，即，金屬化製程 進行通過閘極側含鍺部分62的底面及觸及第二矽部分 42B在第二矽部分42B及第二閘極介電質40B間之介 面處的材料。第二閘極電極82較佳是包含在閘極介電 質介面（即與第二閘極介電質40B的介面）之金屬單矽化 物及金屬單鍺化物的合金。在此將第二閘極電極82的 厚度稱為第二厚度t2。由於由第二裝置區200中受金屬surface. The thickness J of the source side containing portion 66 is substantially the same thickness 'because the second source region 锗 = has substantially the same dopant concentration. According to two: the thickness of the open-end side containing portion 62 is fixed or different from the thickness of the source-side containing portion 66. The same applies to FIG. 8' using the wet residual or dry money dielectric mask layer 60 without removing the closed-end side yoke portion 62 3 erroneous portion 66 and the immersed side erroneous portion 邰 source side s ( 36A, 38A), the first stone part 42A, and the = and ^ pole and the polar area (52, 52,). The etching can be anisotropic or better: polar spacing isotropic. For example, if the dielectric mask layer 60 comprises a wet type that is qualitatively etched using hydrofluoric acid (10). Later, with reference to Figure 9, a metal layer 70 is deposited over the exposed surface 200950002 on the top side of the exemplary semiconductor structure. Metal layer 70 is typically continuous throughout semiconductor substrate $. The metal layer 70 directly contacts the first germanium portion 42A, the first source and the gate region (36A, 38A), the gate side germanium portion 62, and the second source and drain regions (36B, 38B). A step is formed in the metal layer 7 (the edge of the source side yoke portion 66 and the drain side yoke portion 68 (not shown). '' Preferably, the metal layer 70 includes a metal tantalum compound and a metal sheet. The metal of the metallization 7G. Non-limiting exemplary materials of the metal layer 7G include nickel, nickel, galvanic, imal, or a combination thereof. Physical vapor deposition chemical vapor deposition (CVD), or atomic layer deposition: 7 Å can be utilized. The deposit of gold H layer metal deposited in a clear or non-conformal manner is substantially conformal. Preferably, during metallization annealing, by inversion with the metal in the metal layer % = direct contact with the metal layer % The semiconductor portion of gold: at "about 350. (: to a temperature of about 550 ° C, the leisure, p, chemical, which is usually large in oxygen-free gas; such as He? gas). Preferably, the annealing is performed at a temperature of about _ ΐ to a degree. It may be a fixed temperature or a different approx. + & plus 4: = performing 敎 continuous mediation (four) 1 second to ° - pushing the r into the IL for additional annealing 'into a temperature Calving. Preferably, it is additionally annealed at about 5G (Kc to about 70 °C). The multi-stage annealing of the temperature has a gamma-cutting rate that is lower than that of the metal material or the 200950002. The metal bismuth phase and the metal single bismuth phase of the metal sulphide. After the metallization process, the utilization It may be a wet etch that removes portions of the metal layer 70 that are not reactive (appearing over the dielectric surface, such as the first and gate spacers (52, 52') and the shallow trench isolation structure 32) Without removing the different metal semiconductor alloy portions, the etchant typically used for this wet etching uses aqua regia. Referring to Figure 10, there are shown different metal semiconductor alloy portions formed by a metallization process including a first gate electrode 72. The second gate electrode 82, the source side metal germanide portion 76, the drain side metal germanide portion 78, the source side metal telluride-telluride alloy portion 86, and the drain side metal telluride-telluride Alloy portion 88. The first gate electrode 72 is formed by completely deuterating the first germanium portion 42A by the metal layer 70, that is, the metallization process touches the first germanium portion 42A at the first germanium portion 42A and the first gate dielectric Quality 40A The material at the interface. The first gate electrode 72 thus comprises a metal telluride, and preferably a metal monolayer at the gate dielectric interface (ie, the interface with the first gate dielectric 40A). Here, the thickness of the first gate electrode 72 is referred to as a first thickness t1. The second gate electrode 72 is formed by the metal layer 70 by completely metallizing the gate side germanium portion 62 and the second germanium portion 42B. That is, the metallization process is performed through the bottom surface of the gate side containing portion 62 and the material contacting the second germanium portion 42B at the interface between the second germanium portion 42B and the second gate dielectric 40B. The electrode 82 is preferably an alloy of a metal single telluride and a metal single telluride contained in a gate dielectric interface (ie, an interface to the second gate dielectric 40B). Here, the thickness of the second gate electrode 82 is referred to as a second thickness t2. Due to the metal received by the second device zone 200

7Ί I 200950002 化之閘極側含鍺部分62所提供的額外半導體材料，第 二厚度t2大於第—厚度。 ~ 源極側金屬矽化物部分76直接在η型金氧半導體 場效電晶體(NMOSFET)的第一源極區36Α上形成且包 含金屬矽化物。汲極侧金屬矽化物部分78直接在η型 金氧半導體場效電晶體的第一汲極區36Β上形成且包 含金屬矽化物。源極侧金屬矽化物部分76及汲極側金 屬石夕化物部分78具有相同的厚度，在此稱為第三厚度 t3。 源極侧金屬梦化物-鍺化物合金部分86直接在p型 金氧半導體場效電晶體(PMOSFET)的第二源極區36B 上形成且包含金屬石夕化物-鍺化物合金。汲極侧金屬石夕 化物-鍺化物合金部分88直接在p型金氧半導體場效電 晶體的第二汲極區38B上形成且包含金屬矽化物·鍺化 物合金。源極侧金屬矽化物-鍺化物合金部分86及汲極 侧金屬矽化物-鍺化物合金部分88具有相同的厚度，在 此稱為第四厚度t4。第四厚度t4大於第三厚度t3，因 為源極侧含鍺部分66及汲極側含鍺部分68提供比矽更 容易金屬化之金屬化的額外材料。 較佳是，第一閘極電極72在與第—閘極介電質4〇A 的介面處具有MSi的成分，及第二閘極電極82在與第 二閘極介電質40B的介面處具有MGexSii-x的成分，其 中X介於約〇.〇5至約〇,85。Μ是具有AyBi—y之成分的 200950002 或ΐ屬合金，其中y介於〇至i，a是第-元 緣之功一70素金屬。通常’具有接近價帶隙邊 我妒社 ~極電極材料對於加強pmosfet的效能 H i在此例，，X較佳是介於約0.25至約0.85，及 右ιψ =於約二至約〇·85 °由於第二硬部分40B的 有限厚度’而定出約〇 85的上限。 第二厚度t2與篦—厘麻 較佳是介於約u、料比介於μ至約h30, 的距離而增加與第二間極介電質備 金屬鍺化物因在金屬㈣金料化物及 不足時會發生此二二 火期間的熱處理有限而混合 極82為實質_或者，X值可以遍及第二閘極電 δζ马貫質上不變，在第二 物及金屬鍺化物因在金屬化^電極82⑽金屬梦化 充分混合使第二閘極電火期_熱處理足夠而 電極82變均勻時會發生此情形。 在金屬化之前，即，在 二閘極電極82之前，第第—閘極電極72及第 的厚度必須相同。如果閘極^似及第二破部分42B 含石夕的另一半導體合金，1 / 3鍺部分62為鍺或不包 電極82僅有的石夕來源。由部分42B是第二閘極 ::分42B的厚度相同及閘極側含夕42么=二砍 矽，在金屬化退火之前， 辞邻刀62不含有任何 石夕部分42B與含鍺部二，—石夕部分42A及由第二 面積的矽含量相同。右八麗/、、'且成的堆疊之間，每單位 〜 在至屬化退火之後形成的第一閘極 200950002 電極72及第二閘極電極82每單位面積具有相同的矽總 置’即，在第一閘極電極72内每單位面積的矽總量實 質上相同於在第二閘極電極82内每單位面積的矽總 量。由於第二厚度t2大於第一厚度tl，第一閘極電極 72每單位體積的矽含量大於第二閘極電極82每單位體 積的石夕含量。如果第一閘極電極72及第二閘極電極82 分別為均質，第一閘極電極72每單位體積的矽含量與 第二閘極電極82每單位體積的矽含量之比相同於第二 厚度t2與第一厚度tl之比。 中段製程(MOL)介電層90可以包括或不包括反應 離子餘刻（RIE)障壁層（未顯示），係沈積於第一閘極電極 72、第二閑極電極82、第一及第二閘極間隔物（52、52，）、 淺溝渠隔離結構32、源極側金屬矽化物部分76、汲極 側金屬矽化物部分78、源極侧金屬矽化物-鍺化物合金 部分86、及汲極侧金屬矽化物-鍺化物合金部分88之 上。MOL介電層90可包含例如CVD氧化物，諸如未 摻雜矽酸鹽玻璃（USG)、硼矽酸鹽玻璃（BSG)、磷矽酸 鹽（PSG)、氟矽酸鹽玻璃（FSG)、硼構矽酸鹽玻璃 (BPSG)、或其組合。或者’ MOL介電層90可包含低k 介電材料’其介電常數低於3.9(氧化矽的介電常數）， 及較佳是低於約2.5。示範性低k介電材料包括有機矽 酸鹽玻璃（OSG)及SiLKTN^MOL介電層90縱向鄰接第 一閘極電極72的頂面、第二閘極電極82的頂面、第一 閘極間隔物52的内部侧壁、及第二閘極間隔物52'的内 部側壁。 200950002 通常’不同的接觸介層孔（未顯示）係形成於MOL 介電層90中且以金屬填充以形成不同的接觸介層（未顯 示）。其後形成第一層級金屬布線(未顯示)後，接著另外 形成額外後段製程(BEOL)結構(未顯示）。 因此，示範性半導體結構包含： η型金氧半導體場效電晶體，具有第一閘極介電質 40Α及直接位在第一閘極介電質40Α上的第一閘極電 極72 ’其中第一閘極電極72包含金屬矽化物及具有第 一厚度tl ;及 P型金氧半導體場效電晶體，具有第二閘極介電質 40B及直接位在第二閘極介電質40B上的第二閘極電極 82 ’其中第二閘極電極82包含金屬矽化物-鍺化物合金及真 有第二厚度t2，其中第二厚度t2大於第一厚度tl。 雖然已針對特定具體實施例說明本發明，但熟習本 技術者從上述說明應明白可進行許多替代、修改、及變 化。因此，本發明旨在涵蓋所有此類落在本發明及以下 申請專利範圍之範疇及精神的替代、修改、及變化。 200950002 【圖式簡單說明】 圖1-10為根據本發明之示範性半導體結構的連續 垂直截面圖。 【主要元件符號說明】 8 半導體基板 10 操作基板 20 埋藏絕緣層 30A 第一半導體部分 30B 第二半導體部分 32 淺溝渠隔離結構 34A 第一主體區 34B 弟二主體區 36A 弟--*源極區 36B 弟二源極區 38A 第一没極部分 38B 第二汲極部分 40A 第一閘極介電質 40B 第二閘極介電質 40L 閘極介電層 42A 第一矽部分 42B 第二矽部分 42L 矽層 44A 第一可棄式含鍺部分 44B 第二可棄式含鍺部分 200950002 44L 含錯層 52 第一閉極間隔物 52, 第二閘極間隔物 60 介電遮罩層 62 閘極側含錯部分 66 源極侧含鍺部分 67 光阻 68 汲極側含鍺部分 70 金屬層 72 第一閘極電極 76 源極側金屬矽化物部分 78 汲極側金屬矽化物部分 82 第二閘極電極 86 源極侧金屬矽化物-錯化物合金部分 88 汲極側金屬矽化物-鍺化物合金部分 90 中段製程(MOL)介電層 100 第一裝置區 200 第二裝置區 tl 第一厚度 t2 第二厚度 t3 第三厚度 t4 第四厚度7Ί I 200950002 The additional semiconductor material provided by the germanium portion 62 of the gate side, the second thickness t2 is greater than the first thickness. The source side metal germanide portion 76 is formed directly on the first source region 36 of the n-type MOSFET (NMOSFET) and contains a metal telluride. The drain side metal germanide portion 78 is formed directly on the first drain region 36 of the n-type MOS field effect transistor and contains a metal telluride. The source side metal telluride portion 76 and the drain side metal lithiate portion 78 have the same thickness, referred to herein as the third thickness t3. The source side metal dreaming-telluride alloy portion 86 is formed directly on the second source region 36B of the p-type MOS field effect transistor (PMOSFET) and comprises a metal lithium-telluride alloy. The drain side metallization-telluride alloy portion 88 is formed directly on the second drain region 38B of the p-type MOS field effect transistor and comprises a metal telluride/telluride alloy. The source side metal telluride-telluride alloy portion 86 and the drain side metal telluride-telluride alloy portion 88 have the same thickness, referred to herein as the fourth thickness t4. The fourth thickness t4 is greater than the third thickness t3 because the source side germanium containing portion 66 and the drain side germanium containing portion 68 provide additional material that is more metallizable than tantalum. Preferably, the first gate electrode 72 has a component of MSi at the interface with the first gate dielectric 4A, and the second gate electrode 82 is at the interface with the second gate dielectric 40B. A composition having MGexSii-x, wherein X is between about 〇.〇5 to about 〇, 85. Μ is a 200950002 or bismuth alloy with AyBi-y composition, where y is between 〇 and i, and a is a ternary metal. Usually, 'has a close to the valence band gap. The performance of the electrode material for strengthening the pmosfet. In this case, X is preferably between about 0.25 and about 0.85, and the right ι is at about two to about 〇. 85 ° sets an upper limit of about 85 due to the finite thickness ' of the second hard portion 40B'. The second thickness t2 and the bismuth-cyanate are preferably at a distance of about u, the ratio of the material to the range of μ to about h30, and the second inter-electrode quality metal halide is formed in the metal (tetra) metallization and Insufficient, the heat treatment during the second and second fires is limited, and the mixed pole 82 is substantially _ or the X value can be constant throughout the second gate electric δ, and the second material and the metal telluride are metallized. ^ Electrode 82 (10) Metal Dreaming Full Mixing This occurs when the second gate is in a fire period _ heat treatment is sufficient and the electrode 82 is uniform. Prior to metallization, i.e., prior to the two gate electrodes 82, the first gate electrode 72 and the first thickness must be the same. If the gate electrode and the second broken portion 42B contain another semiconductor alloy of the stone, the 1/3 portion 62 is the only source of the stone or the electrode 82. The portion 42B is the second gate: the thickness of the portion 42B is the same and the gate side is 42. = the second chopping. Before the metallization annealing, the adjacent knife 62 does not contain any the stone portion 42B and the crotch portion. - The Shixia part 42A and the second area have the same content of bismuth. Between the stacks of right 丽 、, 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The total amount of germanium per unit area in the first gate electrode 72 is substantially the same as the total amount of germanium per unit area in the second gate electrode 82. Since the second thickness t2 is greater than the first thickness t1, the content of germanium per unit volume of the first gate electrode 72 is greater than the content of germanium per unit volume of the second gate electrode 82. If the first gate electrode 72 and the second gate electrode 82 are respectively homogeneous, the ratio of the germanium content per unit volume of the first gate electrode 72 to the germanium content per unit volume of the second gate electrode 82 is the same as the second thickness. The ratio of t2 to the first thickness t1. The mid-stage process (MOL) dielectric layer 90 may or may not include a reactive ion residual (RIE) barrier layer (not shown) deposited on the first gate electrode 72, the second idle electrode 82, first and second Gate spacers (52, 52,), shallow trench isolation structures 32, source side metal germanide portions 76, drain side metal germanide portions 78, source side metal telluride-telluride alloy portions 86, and germanium The pole side metal telluride-telluride alloy portion 88 is over. The MOL dielectric layer 90 can comprise, for example, a CVD oxide such as undoped silicate glass (USG), borosilicate glass (BSG), phosphonium silicate (PSG), fluorosilicate glass (FSG), Boron silicate glass (BPSG), or a combination thereof. Alternatively, the 'MOL dielectric layer 90 can comprise a low-k dielectric material' having a dielectric constant less than 3.9 (the dielectric constant of yttrium oxide), and preferably less than about 2.5. An exemplary low-k dielectric material comprising an organic tellurite glass (OSG) and a SiLKTN^MOL dielectric layer 90 longitudinally adjoining a top surface of the first gate electrode 72, a top surface of the second gate electrode 82, and a first gate The inner sidewall of the spacer 52 and the inner sidewall of the second gate spacer 52'. 200950002 Typically, 'different contact via holes (not shown) are formed in the MOL dielectric layer 90 and filled with metal to form different contact vias (not shown). Thereafter, a first level metal wiring (not shown) is formed, followed by an additional back end of line (BEOL) structure (not shown). Therefore, the exemplary semiconductor structure includes: an n-type MOS field effect transistor having a first gate dielectric 40 Α and a first gate electrode 72 ′ directly on the first gate dielectric 40 其中A gate electrode 72 includes a metal telluride and has a first thickness t1; and a P-type MOS field effect transistor having a second gate dielectric 40B and directly on the second gate dielectric 40B. The second gate electrode 82' wherein the second gate electrode 82 comprises a metal telluride-telluride alloy and has a second thickness t2, wherein the second thickness t2 is greater than the first thickness t1. While the invention has been described with respect to the specific embodiments of the present invention, it will be understood Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variations in the scope of the invention and the scope of the invention. 200950002 BRIEF DESCRIPTION OF THE DRAWINGS Figures 1-10 are continuous vertical cross-sectional views of an exemplary semiconductor structure in accordance with the present invention. [Main component symbol description] 8 semiconductor substrate 10 operation substrate 20 buried insulating layer 30A first semiconductor portion 30B second semiconductor portion 32 shallow trench isolation structure 34A first body region 34B second body region 36A brother - * source region 36B 2nd source region 38A first poleless portion 38B second drain portion 40A first gate dielectric 40B second gate dielectric 40L gate dielectric layer 42A first turn portion 42B second turn portion 42L矽 layer 44A first disposable yoke portion 44B second disposable yttrium containing portion 200950002 44L with misaligned layer 52 first closed pole spacer 52, second gate spacer 60 dielectric mask layer 62 gate side Misaligned portion 66 Source side yttrium containing portion 67 Photoresist 68 Bipolar side yttrium containing portion 70 Metal layer 72 First gate electrode 76 Source side metal germanide portion 78 Bipolar side metal germanide portion 82 Second gate Electrode 86 source side metal telluride-deformed alloy portion 88 drain side metal telluride-telluride alloy portion 90 mid-range process (MOL) dielectric layer 100 first device region 200 second device region tl first thick The thickness t2 of the second third thickness t3 fourth thickness t4

Claims (1)

200950002 七、申請專利範圍： 1. 一種形成一半導體結構之方法，其包含： 形成一第一閘極介電質於一半導體基板的一第一半導 體部分上及一第二閘極介電質於該半導體基板的一第二半 導體部分上； 形成一第一矽部分於該第一閘極介電質上及一第二矽 部分於該第二閘極介電質上； 形成一閘極侧含鍺部分於該第二矽部分上，且沒有鍺 沈積在該第一矽部分上；及 直接形成一包含一金屬^夕化物的第一閘極電極於該第 一閘極介電質上及直接形成一包含一金屬矽化物-鍺化物 合金的第二閘極電極於該第二閘極介電質上。 2. 如請求項1之方法，另外包含在該形成該閘極側含鍺 部分之前，形成一第一可棄式含鍺部分於該第一矽部分上 及一第二可棄式含鍺部分於該第二矽部分上，其中該第一 及第二含鍺部分包含鍺原子濃度介於約25%至100%。 3. 如請求項2之方法，其中該第一及第二可棄式含鍺部 分包含具有一相同鍺濃度的錯或一 z夕鍺合金。 4 · 如請求項2之方法’另外包含形成一第一閘極間隔物 於該第一矽部分及該第一可棄式含鍺部分的側壁上及一第 二閘極間隔物於該第二矽部^分及該第二可棄式含鍺部分的 200950002 . 侧壁上。 5. 如請求項2之方法，另外包含移除該第一及第二可棄 式含鍺部分而不移除該第一及第二梦部分。 6. 如請求項5之方法，另外包含在該移除該第一及第二 可棄式含鍺部分之後，直接形成一介電遮罩層於該第一及 第二矽部分上。 7. 如請求項6之方法，另外包含圖案化該介電遮罩層， 其中在該圖案化之後，藉由該介電遮罩層覆蓋該第一矽部 分，及其中在該圖案化之後，暴露該第二矽部分。 8. 如請求項7之方法，其中該閘極側含鍺部分包含鍺或 一梦鍺合金。 9. 如請求項8之方法，其中採用一選擇性含鍺材料沈積 製程以形成該閘極侧含鍺部分，其中在該選擇性含鍺材料 沈積製程期間，鍺或該矽鍺合金係沈積於半導體表面上而 非沈積於介電質表面上。 10. 如請求項8之方法，另外包含： 直接沈積一金屬層於該第一矽部分及該閘極侧含鍺部 分上；及 35 200950002 金屬化該第一矽部分及一由該閘極側含鍺部分及該第 二石夕部分組成的堆疊。 ~ 11. 如請求項10之方法，其中利用一退火以一介於約350 °C至約550 °C的溫度進行該金屬化。 12. 如請求項10之方法，其中一包含一金屬石夕化物的第一 閘極電極直接在該第一閘極電極上形成，及一包含一金屬 矽化物-鍺化物合金的第二閘極電極直接在該第二閘極電 極上形成。 13. 如請求項12之方法，其中該第一閘極電極在與該第一 閘極介電質之一介面處具有一成分為MSi及該第二閘極電 極在與該第二閘極介電質之一介面處具有一成分為 MGeJik，其中X介於約0.05至約0.85，及Μ為一元素 金屬或一具有一成分為AyBi_y的金屬合金，其中y介於0 至1，及A為一第一元素金屬及B為一第二元素金屬。 14. 如請求項7之方法，另外包含： 形成一第一閘極間隔物於該第一矽部分上及一第二閘 極間隔物於該第二矽部分上；及 形成一第一源極區及一第一汲極區於該第一半導體部 分中及一第二源極區及一第二汲極區於該第二半導體部分 l|^ 〇 200950002 區/14之方法’其中該第—源極區及該第一没極 :極二：:匕之後藉由該介電遮罩層覆蓋，及其中該第 ’、π &第二汲極區在該圖案化之後被暴露。 16.如請求们5之方法，其另外包含： 及 其中 該第 接形成一汲極侧含鍺部分於該第二汲極區上 ^積錯或-含鍺合金並不直接發生於該第 一源極區、及該第一汲極區上。 丨刀 ^形成—閘極侧含鍺部分於該第二碎部分上 形成一源極侧含鍺部分於該第二源極區上 17 如請求項1之方法，另外包含： 直接形成一閘極介電層於該半導體基板上； 層上直接形成—包含非㈣或多晶料韻於該閘極介電 該矽層 及 2形，-包含鍺料濃度約25%相上的含錯層於 矽部分f::::層及該矽層’其中由該矽層形成該第一 分於姑第一矽部分，及其中形成一第一可棄式含錄部 二石夕心/夕部分上及形成—第二可棄式含鍺部分於該第 種半導體結構，其包含： η 18. 200950002 極電極包含—金屬梦化物及具有一第一厚度；及 位在；晶體，具有一第二閉極介電質及-直接 位在該第一閘極介電質上的第二閘極電極，发 金—金及具有第:: 度，/、中該第二厚度大於該第一厚度。 19.如請求項18之半導體結構，另外包含·· 源極側金屬石夕化物部分，直接位在該第一場效電晶 體的一源極區上及包含該金屬矽化物及具有—第三厚度； 汲極側金屬矽化物部分，直接位在該第一場效電晶 體的一汲極區上及包含該金屬矽化物及具有一第三厚度； 源極側金屬梦化物-鍺化物合金部分，直接位在該第 一場效電晶體的一源極區上及包含該金屬矽化物鍺化物 合金及具有一第四厚度；及 一沒極侧金屬矽化物_鍺化物合金部分，直接位在該第 一場效電晶體的一沒極區上及包含該金屬石夕化物-鍺化物 合金及具有該第四厚度，其中該第四厚度大於該第三厚度。 20.如請求項19之半導體結構，其中該金屬矽化物及該金 屬矽化物-鍺化物合金係衍生自一形成一金屬單矽化物及 一金屬單鍺化物的金屬。 21·如請求項19之半導體結構，其中該第二厚度與該第一 厚度之比介於至約1.30。 CS1 38 200950002 22. 如請求項18之半導體結構，另外包含： 一第一閘極間隔物，橫向鄰接該第一閘極電極； 一第二閘極間隔物，橫向鄰接該第二閘極電極；及 一中段製程(MOL)介電層，縱向鄰接該第一閘極電極 的一頂面、該第二閘極電極的一頂面、該第一閘極間隔物 的内部側壁、及該第二閘極間隔物的内部侧壁。 23. 如請求項18之半導體結構，其中該第一閘極電極在與 該第一閘極介電質之一介面處具有一成分為MSi，及該第 二閘極電極在與該第二閘極介電質之一介面處具有一成分 為MGejik，其中X介於約0.05至約0.85，及Μ為一元 素金屬或一具有一成分為AyB^y的金屬合金，其中y介於 0至1，及A為一第一元素金屬及B為一第二元素.金屬。 24. 如請求項18之半導體結構，其中在該第一閘極電極内 每單位面積之矽總量實質上相同於在該第二閘極電極内每 單位面積之石夕總量。 25. 如請求項18之半導體結構，其中該第一場效電晶體為 一 η型場效電晶體，而該第二場效電晶體為一 p型場效電200950002 VII. Patent Application Range: 1. A method of forming a semiconductor structure, comprising: forming a first gate dielectric on a first semiconductor portion of a semiconductor substrate and a second gate dielectric a second semiconductor portion of the semiconductor substrate; forming a first germanium portion on the first gate dielectric and a second germanium portion on the second gate dielectric; forming a gate side a portion of the second germanium portion and no germanium deposited on the first germanium portion; and directly forming a first gate electrode including a metal oxide on the first gate dielectric and directly A second gate electrode comprising a metal telluride-telluride alloy is formed on the second gate dielectric. 2. The method of claim 1, further comprising forming a first disposable germanium portion on the first germanium portion and a second disposable germanium portion before forming the gate side germanium portion And wherein the first and second cerium-containing moieties comprise a germanium atom concentration of between about 25% and 100%. 3. The method of claim 2, wherein the first and second disposable ruthenium containing moieties comprise a mis- or a zirconium alloy having the same erbium concentration. 4. The method of claim 2, further comprising forming a first gate spacer on the sidewall of the first buffer portion and the first disposable germanium portion and a second gate spacer in the second The ^ part ^ and the second disposable 锗 containing part of the 200950002. on the side wall. 5. The method of claim 2, further comprising removing the first and second disposable portions without removing the first and second dream portions. 6. The method of claim 5, further comprising directly forming a dielectric mask layer on the first and second germanium portions after the removing the first and second disposable germanium containing portions. 7. The method of claim 6, further comprising patterning the dielectric mask layer, wherein after the patterning, the first germanium portion is covered by the dielectric mask layer, and after the patterning, Expose the second part. 8. The method of claim 7, wherein the gate-side containing portion comprises niobium or a nightmare alloy. 9. The method of claim 8, wherein a selective germanium-containing material deposition process is employed to form the gate-side germanium portion, wherein the germanium or tantalum alloy is deposited during the selective germanium-containing material deposition process On the surface of the semiconductor rather than on the surface of the dielectric. 10. The method of claim 8, further comprising: directly depositing a metal layer on the first germanium portion and the gate side germanium portion; and 35 200950002 metallizing the first germanium portion and one of the gate sides A stack consisting of a ruthenium containing portion and a second zeolitic portion. The method of claim 10, wherein the metallizing is performed using an annealing at a temperature of between about 350 ° C and about 550 ° C. 12. The method of claim 10, wherein a first gate electrode comprising a metal ruthenium compound is formed directly on the first gate electrode, and a second gate comprising a metal telluride-telluride alloy The electrode is formed directly on the second gate electrode. 13. The method of claim 12, wherein the first gate electrode has a component MSi and the second gate electrode and the second gate electrode at an interface with the first gate dielectric One of the dielectric interfaces has a composition of MGeJik, wherein X is between about 0.05 and about 0.85, and Μ is an elemental metal or a metal alloy having a composition of AyBi_y, wherein y is between 0 and 1, and A is A first elemental metal and B are a second elemental metal. 14. The method of claim 7, further comprising: forming a first gate spacer on the first germanium portion and a second gate spacer on the second germanium portion; and forming a first source And a first drain region in the first semiconductor portion and a second source region and a second drain region in the second semiconductor portion l|^ 〇200950002 region/14, wherein the first The source region and the first dipole: the pole 2:: is covered by the dielectric mask layer, and wherein the ', π & second drain region is exposed after the patterning. 16. The method of claim 5, further comprising: wherein the first connection forming a drain side containing germanium portion on the second drain region is incorrect or the germanium containing alloy does not directly occur in the first a source region and the first drain region. The ^ ^ 形成 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸a dielectric layer on the semiconductor substrate; directly formed on the layer - comprising a non-(tetra) or polycrystalline material, the gate layer is dielectrically bonded to the gate layer and the second layer, and comprises a miscible layer having a tantalum concentration of about 25% a portion of the f:::: layer and the layer of the layer, wherein the first layer is formed by the layer of the first layer, and the first portion of the first part of the group is formed And forming a second disposable germanium-containing portion in the first semiconductor structure, comprising: η 18. 200950002 a pole electrode comprising - a metal dream and having a first thickness; and a crystal; having a second closure a dielectric material and a second gate electrode directly on the first gate dielectric, the gold-gold and having a:::, wherein the second thickness is greater than the first thickness. 19. The semiconductor structure of claim 18, further comprising: a source side metallization portion directly on a source region of the first field effect transistor and comprising the metal halide and having a third a thickness; a drain-side metal germanide portion directly on a drain region of the first field effect transistor and comprising the metal telluride and having a third thickness; a source side metal dreaming-telluride alloy portion Directly on a source region of the first field effect transistor and comprising the metal germanide telluride alloy and having a fourth thickness; and a non-polar side metal telluride_telluride alloy portion directly at And comprising the metal-lithium-telluride alloy and having the fourth thickness, wherein the fourth thickness is greater than the third thickness. 20. The semiconductor structure of claim 19, wherein the metal telluride and the metal telluride-telluride alloy are derived from a metal forming a metal monohalide and a metal single telluride. 21. The semiconductor structure of claim 19, wherein the ratio of the second thickness to the first thickness is between about 1.30. CS1 38 200950002 22. The semiconductor structure of claim 18, further comprising: a first gate spacer laterally adjacent to the first gate electrode; a second gate spacer laterally adjacent to the second gate electrode; And a mid-stage process (MOL) dielectric layer, a top surface of the first gate electrode, a top surface of the second gate electrode, an inner sidewall of the first gate spacer, and the second portion The inner sidewall of the gate spacer. 23. The semiconductor structure of claim 18, wherein the first gate electrode has a component MSi at one interface with the first gate dielectric, and the second gate electrode is at the second gate One of the dielectrics has a composition of MGejik, wherein X is between about 0.05 and about 0.85, and the tantalum is an elemental metal or a metal alloy having a composition of AyB^y, wherein y is between 0 and 1 And A is a first elemental metal and B is a second element. Metal. 24. The semiconductor structure of claim 18, wherein the total amount of germanium per unit area in the first gate electrode is substantially the same as the total amount of stone per unit area in the second gate electrode. 25. The semiconductor structure of claim 18, wherein the first field effect transistor is an n-type field effect transistor and the second field effect transistor is a p-type field effect transistor
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