US20130175619A1

US20130175619A1 - Silicon-on-insulator transistor with self-aligned borderless source/drain contacts

Info

Publication number: US20130175619A1
Application number: US13/345,201
Authority: US
Inventors: Susan S. FAN; Balasubramanian S. Haran; David V. Horak; Charles W. Koburger, III
Original assignee: International Business Machines Corp
Current assignee: Alsephina Innovations Inc
Priority date: 2012-01-06
Filing date: 2012-01-06
Publication date: 2013-07-11
Also published as: US8623730B2; US20130178052A1; US20140061799A1; US9368590B2

Abstract

A transistor includes a semiconductor layer, a gate spacer on the semiconductor layer, a gate dielectric comprising a first portion above the semiconductor layer and a second portion on sidewalls of the gate spacer, a work function metal layer comprising a first portion on the first portion of the gate dielectric and a second portion on sidewalls of the gate dielectric, a gate conductor on the first portion of the work function layer and abutting the second portion of the work function layer, a dielectric layer on the semiconductor layer and abutting the gate spacer, an oxide film above only one of the work function layer and the gate conductor, an oxide cap, source/drain regions, and a source/drain contact passing through the dielectric layer and contacting an upper surface of one of the source/drain regions. A portion of the source/drain contact is located directly on the oxide cap.

Description

FIELD OF THE INVENTION

The present invention generally relates to the field of semiconductor devices, and more particularly relates to silicon-on-insulator (SOI) transistors with self-aligned borderless source/drain contacts.

BACKGROUND OF THE INVENTION

As semiconductor devices move to ever smaller dimensions, the space for source/drain contacts is reduced even more than the reduction in scale of the transistor. For example, in the 20 nm generation, the lithographic contact dimension is about 65 nm, and this must be reduced to about 20 nm in the etch. With such drastic reductions, the source/drain contact cannot be guarantee to land on the silicided area of the source/drain. The source/drain contact will frequently impinge on the area between the side of the gate stack and the edge of the silicided area of the source/drain. This critical area must be protected in order to prevent modification of the critical dopant concentration required for advanced junction designs. Further, if a portion of the source/drain contact lands on the gate, the transistor will be shorted. Such source/drain contacts that land on the gate must be prevented from shorting the device or punching through the silicon beneath the gate spacer.

SUMMARY OF THE INVENTION

One embodiment of the present invention provides a method for fabricating a transistor. According to the method, a replacement gate stack is formed on a semiconductor layer, a gate spacer is formed on sidewalls of the replacement gate stack, and a dielectric layer is formed on the semiconductor layer and abutting the gate spacer. After forming the gate spacer and the dielectric layer, the dummy gate stack is removed to form a cavity. A gate dielectric is formed in the cavity, and a work function metal layer is formed in the cavity. After forming the gate dielectric and the work function metal layer, a remaining portion of the cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed to form a recess. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap directly on the upper surface of the gate dielectric, the upper surface of the oxide film, and a portion of the upper surface of the dielectric layer. An interlayer dielectric is formed, and the interlayer dielectric and the dielectric layer are etched to form at least one contact cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.
Another embodiment of the present invention provides a transistor that includes a semiconductor layer, a gate spacer located on the semiconductor layer, a gate dielectric located above the semiconductor layer, a work function metal layer located on the gate dielectric and vertical sidewalls of the gate dielectric, and a gate conductor located on the work function metal layer. The transistor also includes a dielectric layer located on the semiconductor layer and abutting the gate spacer, an oxide film, and an oxide cap. The oxide film is located above one and only one of the work function metal layer and the gate conductor. The upper surface of the dielectric layer is co-planar with the upper surface of the oxide film and the upper surface of the second portion of the gate dielectric, and the oxide cap is located directly on the upper surface of the gate dielectric, the upper surface of the oxide film, and a portion of the upper surface of the dielectric layer. The transistor further includes source/drain regions located in the semiconductor layer, and a source/drain contact passing through the dielectric layer and contacting an upper surface of one of the source/drain regions. A portion of the source/drain contact being located directly on the oxide cap.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating various embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional view of a substrate, buried insulator layer, and a semiconductor layer according to a first embodiment of the present invention;

FIG. 2 shows a cross-sectional view of the structure after a replacement gate structure has been formed according to the first embodiment of the present invention;

FIG. 3 shows a cross-sectional view of the structure after the replacement gate structure has been removed to form a gate cavity according to the first embodiment of the present invention;

FIG. 4 shows a cross-sectional view of the structure after a dielectric layer and a gate conductor have been formed within the gate cavity according to the first embodiment of the present invention;

FIG. 5 shows a cross-sectional view of the structure after the gate conductor is recessed according to the first embodiment of the present invention;

FIG. 6 shows a cross-sectional view of the structure after a silicon dioxide film is formed in the recess according to the first embodiment of the present invention;

FIG. 7 shows a cross-sectional view of the structure after a silicon dioxide cap is grown on top of the silicon dioxide film according to the first embodiment of the present invention;

FIG. 8 shows a cross-sectional view of the structure after formation of source/drain contacts according to the first embodiment of the present invention;

DETAILED DESCRIPTION

Borderless source/drain contacts are now being used to prevent source/drain contacts that land on the gate from shorting the transistor. A borderless source/drain contact requires no border between the gate and the contact. The gate stack is encapsulated in dielectric so that the borderless source/drain contact can land on the gate without shorting the device. In gate-first transistor fabrication processes, the gate stack can just be encapsulated during gate formation. In particular, after depositing the gate layers, a dielectric layer is deposited over the structure. Then when the gate stack is etched to pattern the gate, this overlying dielectric layer is also etched at the same time to protect the top of the gate stack. Dielectric spacers are then formed on the sides of the gate stack to produce a gate stack that is encapsulated and thus protected from being shorted by source/drain contacts that land on the gate.
However, in gate-last transistor fabrication processes, such an encapsulation method cannot be used to encapsulate the gate stack. A dummy gate is formed in gate-last transistor fabrication processes. This dummy gate is later removed to open a cavity from the top, and then the actual gate is formed in this cavity. Because the dummy gate and everything above it is removed when opening the cavity, the gate-first encapsulation method cannot be used to encapsulate the gate stack in gate-last transistor fabrication processes. One method for encapsulating the gate in gate-last transistor fabrication processes is to recess both the work function metal and the gate conductor, and then fill this recess with a dielectric material. However, this requires a precise deep etch of both the work function metal and the gate conductor. Such a precise deep etch of both materials is difficult to obtain and can significantly lower the gate conductance.
Embodiments of the present invention provide a silicon-on-insulator (SOI) transistor with self-aligned borderless source/drain contacts. After formation of the gate stack, a shallow recess is made in one of the metal layers of the gate stack (e.g., the work function metal or the gate conductor). A dielectric film is formed in the recess and then used as a seed to selectively grow a dielectric cap over the gate stack. The dielectric cap protects the gate stack during the etching of the source/drain contacts. This borderless contact integration scheme can be used in gate-last fabrication processes that utilize a replacement metal gate structure and in gate-first fabrication processes that utilize a full metal gate.
FIGS. 1 to 8 illustrate a process for forming an SOI transistor having self-aligned borderless source/drain contacts according to a first embodiment of the present invention. As shown in FIG. 1, there is provided an SOI wafer having a silicon substrate 102, a buried insulator layer (BOX) 104, and a semiconductor layer 106.
The substrate 102 of this embodiment is a semiconductor substrate comprising a single crystalline semiconductor material such as single crystalline silicon, a polycrystalline semiconductor material, an amorphous semiconductor material, or a stack thereof. The thickness of the substrate 102 is from 50 microns to 1,000 microns, although lesser and greater thicknesses are employed in further embodiments. The BOX layer 104 includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The thickness of the BOX layer 104 is from 50 nm to 500 nm, although lesser and greater thicknesses are employed in further embodiments.
The semiconductor layer 106 is any semiconducting material such as Si (silicon), strained Si, SiC (silicon carbide), SiGe (silicon germanium), SiGeC (silicon-germanium-carbon), Si alloys, Ge, Ge alloys, GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or any combination thereof. The thickness of the semiconductor layer 106 is from 3 nm to 60 nm, and typically from 5 nm to 10 nm, although lesser and greater thicknesses are employed in further embodiments.
The semiconductor layer 106 can be undoped or doped with either p-type or n-type dopants through ion implantation, plasma doping, or gas phase doping. P-type transistors are produced by doping the semiconductor layer 106 with elements from group III of the periodic table (e.g., boron, aluminum, gallium, or indium). As an example, the dopant can be boron in a concentration ranging from 1×10E18 atoms/cm3 to 2×10E21 atoms/cm3. N-type transistors are produced by doping the semiconductor layer 106 with elements from group V of the periodic table (e.g., phosphorus, antimony, or arsenic). In this example, the BOX layer 104 is composed of silicon oxide and the semiconductor layer 106 is composed of silicon and doped with a first conductivity type dopant.
Next, an active area for the transistor is isolated by shallow trench isolation (STI). In this embodiment, shallow trench isolation (STI) structures 312 and 313 are formed by making trenches extending from the top surface of the semiconductor layer 106 to the BOX layer 104, filling the trenches with a dielectric material, and removing excess dielectric material from above the top surface of the semiconductor layer 106. This forms an STI region 312 and 313 above the BOX layer 104 that is continuous around the active area.
As shown in FIG. 2, a replacement (or dummy) gate stack structure is formed to act as a place holder for the actual gate stack that is formed later. The replacement gate stack structure of this embodiment includes a replacement gate dielectric 414 and a replacement gate material 416 that are formed on the active area of the silicon layer 106. The replacement gate dielectric 414 is a dielectric material that can function as an etch stop layer during subsequent removal of the replacement gate material 416. In this embodiment, the replacement gate dielectric 414 is silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
The replacement gate material 416 is a dielectric or conducting material that can be removed selectively with respect to the replacement gate dielectric 414 and a gate spacer 418. In this embodiment, the replacement gate material 416 is a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof). The thickness of the replacement gate stack structure 414 and 416 is from 10 nm to 500 nm, although lesser and greater thicknesses are employed in further embodiments.
The gate spacer 418 is a dielectric material (such as silicon oxide, silicon nitride, silicon oxynitride, or a combination of these) formed on the sidewalls of the replacement gate stack 414 and 416. In this embodiment, the gate spacer 418 is formed by deposition of a conformal dielectric material layer and then etching to remove the dielectric material except from the sidewalls of the dummy gate stack 414 and 416. The thickness of the gate spacer 418 at the base that contacts the semiconductor layer 106 is from 10 nm to 120 nm, and typically from 20 nm to 60 nm, although lesser and greater thicknesses are employed in further embodiments.
In the illustrated embodiment, source and drain extension regions 424 and 426 are formed by introducing dopants into exposed portions of the semiconductor layer 106, employing the replacement gate stack structure 414 and 416 as a mask. The source and drain extension regions 424 and 426 have doping of a second conductivity type, which is the opposite of the first conductivity type. In this embodiment, source and drain regions 420 and 422 are formed by deep implanting dopants into exposed portions of the semiconductor layer 106, employing the combination of the replacement gate stack structure 414 and 416 and the gate spacer 418 as a mask. The source and drain regions 420 and 422 have the same type of doping as the source and drain extension regions 424 and 426. A thermal anneal can be performed to activate and diffuse the implanted ions.
In this embodiment, for an NFET, the source/ drain regions 420 and 422 are heavily doped with an n-type dopant and the source/ drain extension regions 424 and 426 are lightly doped with the same or a different n-type dopant. Conversely, for a PFET, the source/ drain regions 420 and 422 are heavily doped with a p-type dopant and the source/ drain extension regions 424 and 426 are lightly doped with the same or a different p-type dopant. Silicided areas for contacts are then formed on the source and drain regions.
After the source/ drain regions 420 and 422 have been formed, a dielectric layer 528 is formed over the entire structure. In this embodiment, the dielectric layer 528 is a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof that is formed through chemical vapor deposition (CVD). This dielectric layer 528 is etched down to the level of the top surface of the replacement gate stack 414 and 416.
As shown in FIG. 3, the replacement gate stack 414 and 416 is then selectively removed with respect to the gate spacer 418 (e.g., via selective etching). This forms a gate cavity 630 that is laterally surrounded by the gate spacer 418. The inner sidewalls of the gate spacer 418 and a portion of the top surface of the semiconductor layer 106 are exposed by formation of the gate cavity 630.
Optionally, an interfacial layer is formed on the exposed surface of the semiconductor layer 106 by conversion of a surface portion of the semiconductor material into a dielectric material. For example, the semiconductor layer 106 can be single crystalline silicon, and the interfacial layer can be silicon oxide which is formed by thermal oxidation, chemical oxidation, or plasma oxidation of the surface portion. The thickness of the interfacial layer is from 0.1 nm to 1.5 nm, although lesser and greater thicknesses are employed in further embodiments. The thickness, however, may be different after processing at higher temperatures, which are usually required during device fabrication.
A high-k dielectric layer is then blanket deposited to form a high-k gate dielectric layer 836 on the bottom and vertical sidewalls of the gate cavity, as shown in FIG. 4. The high-k dielectric layer 836 is a dielectric metal oxide having a dielectric constant greater than 8.0. The dielectric metal oxide is deposited by a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD), etc. In this embodiment, the high-k gate dielectric layer 836 comprises HfO₂or ZrO₂. However, other materials such as La₂O₃, Al₂O₃, TiO₂, SrTiO₃, LaAlO₃, Y₂O₃, HfO_xN_y, ZrO_xN_y, La₂O_xN_y, Al₂O_xN_y, TiO_xN_y, SrTiO_xN_y, LaAlO_xN_y, Y2O_xN_y, a silicate thereof, and an alloy thereof are applicable as well (each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2). The thickness of the high-k gate dielectric layer 836 is from 0.5 nm to 6 nm, and typically from 1.0 nm to 3 nm, although lesser and greater thicknesses are employed in further embodiments.
After the high-k gate dielectric 836 has been formed, a work function metal layer 850 is deposited on the gate dielectric layer 836. This work function metal layer 850 is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), physical vapor deposition (PVD), or a combination thereof. The work function metal layer 850 optimizes the performance of the transistor by tuning the work function of the gate electrode. In this embodiment, this work function metal layer 850 is a p-type work function material, such as TiN. Other metallic materials such as Pt, Rh, Ir, Ru, Cu, Os, Be, Co, Pd, Te, Cr, Ni, Hf, Ti, Zr, Cd, La, TI, Yb, Al, Ce, Eu, Li, Pb, Tb, Bi, In, Lu, Nb, Sm, V, Zr, Ga, Mg, Gd, Y, TiAl, alloys thereof, conductive oxides thereof, conductive nitrides thereof, and any combinations of the foregoing can also be used.
Next, a gate conductor material 56 is deposited in the gate cavity. The gate conductor material 852 comprises a conductive material, which can be a doped semiconductor material, a metallic material, or a combination thereof. The doped semiconductor material can be doped polysilicon, doped polycrystalline germanium, a doped silicon-germanium alloy, any other doped elemental, a compound semiconductor material, or a combination thereof. The metallic material can be any metallic material that can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination thereof, such as aluminum, tungsten, ruthenium, or a conductive refractory metal nitride, such as TaN (tantalum nitride), TiN (titanium nitride), WN (tungsten nitride), TiAl (titanium aluminum), TiAlN (titanium aluminum nitride), TaCN (triazacyclononane), or an alloy thereof. In the illustrated embodiment, the gate conductor material 852 can be aluminum, tungsten, ruthenium, or any conductive metal or metal alloy (such as aluminum-cobalt). The thickness of the gate conductor material 852 is selected to completely fill the gate cavity.
The portions of the high-k gate dielectric layer, work function metal layer, and gate conductor material above the top surface of the dielectric layer 528 are removed by planarization, which can be performed by chemical mechanical planarization (CMP), recess etch, or a combination thereof. The remaining portion of the high-k gate dielectric layer constitutes a U-shaped gate dielectric 836, the remaining portion of the work function metal layer constitutes a U-shaped work function metal layer 850, and the remaining portion of the gate conductive material layer 56 constitutes a gate conductor 852.
The top surface of the U-shaped gate dielectric 836, the top surface of the U-shaped work function metal layer 850, and the top surface of the gate conductor 852 are coplanar with the top surface of the dielectric layer 528 after planarization, as shown in FIG. 4. The U-shaped gate dielectric 836, the U-shaped work function metal layer 850, and the gate conductor 852 collectively constitute the gate stack of the transistor. The gate spacer 418 laterally surrounds the gate stack and has a top surface that is coplanar with the top surface of the dielectric layer 528.
After completing the gate stack, the gate conductor 852 is selectively recessed, as shown in FIG. 5. In this embodiment, this selective recess is preformed through a dry etch (for example, using Cl₂-based, BCl₃-based, or CH₃F-based chemistry). The depth of this recess does not have to be well controlled and the recess can be very shallow (e.g., 2-8 nm). The recess just has to be deep enough that at least part of the subsequently deposited layer survives the planarization step following its formation. While a deeper recess can also be used, it should not be so deep as to affect the gate conductance. A shallow recess performs the necessary function while maintaining a high gate conductance. Further, the recesses do not have to be uniform in the gates of all transistors of an integrated circuit. In the illustrated embodiment, the recess has an exemplary depth of 5-10 nm.
Next, a silicon dioxide film 846 is formed in the recess that was made in the gate conductor 852, as shown in FIG. 6. In this embodiment, a damascene process is used to inlay the silicon dioxide film 846 in the recess. More specifically, silicon dioxide is deposited over the entire device so as to overfill the recess, and then CMP is performed to remove the silicon dioxide down to the level of the top of the dielectric layer 528. The silicon dioxide film 846 that is within the recess is not removed.
A silicon dioxide cap 848 is then selectively grown on top of the damascened silicon dioxide film 846, as shown in FIG. 7. The silicon dioxide cap 848 is wider than the gate stack, and preferably its width extends beyond the outer edges of the gate spacer 418 (i.e., the lateral extent of the cap is greater than the lateral extent of the gate spacer). Thus, the combination of the silicon dioxide cap and the gate spacer encapsulates the gate stack. In this embodiment, the silicon dioxide cap 848 is grown by molecular layer dielectric chemical vapor deposition (MLD CVD). Thus, the silicon oxide film 846 in the recess in the gate conductor 852 acts as a seed to grow the silicon dioxide cap 848 above the gate stack. The silicon dioxide cap 848 is self-aligned, with no patterning or other processing required. Further, the silicon dioxide cap 848 grows only above the gate stack where it is needed.
Next, an interlayer dielectric 910 is deposited over the structure, as shown in FIG. 8. In this embodiment, the interlayer dielectric 910 is a nitride layer. A photolithography mask for the source/drain contacts is then deposited and patterned. An etch is then performed to form cavities for the source/drain contacts. This etch forms contact cavities through the interlayer dielectric 910 and dielectric layer 528, stopping on the semiconductor layer 106 (at least partially on the silicided area of the source/drain region). In this embodiment, a reactive ion etch (RIE) is used to form the contact cavities.
Due to the selectivity between silicon dioxide and nitride, the silicon dioxide cap 848 is not removed during etching of the nitride interlayer dielectric 910. The silicon dioxide cap 848 on top of the gate stack serves as an etch stop layer during the etching for the contacts, guiding the source/drain contact away from the gate stack. Thus, the source/drain contact is borderless with respect to the gate stack. The contact cavities are then filled with a conducting material to form the source/drain contacts 920. In this embodiment, the source/drain contacts are formed by a metal such as copper, tungsten, aluminum, ruthenium, or TiN. Conventional fabrication steps are then performed to form the remainder of the integrated circuit that includes this transistor.
FIGS. 9 to 12 illustrate a process for forming an SOI transistor having self-aligned borderless source/drain contacts according to a second embodiment of the present invention. In this embodiment, the work function metal layer is selectively recessed.
The gate stack is first formed in the manner described above with reference to FIGS. 1-4. After completing the gate stack, the work function metal layer 850 is selectively recessed, as shown in FIG. 9. In this embodiment, this selective recess is preformed through a dry etch (for example, using Cl₂-based, BCl₃-based, or CH₂F-based chemistry). The depth of this recess does not have to be well controlled and the recess can be very shallow (e.g., 2-4 nm). In the illustrated embodiment, the recess has an exemplary depth of 5-10 nm.
Next, a silicon dioxide film 930 is formed in the recess that was made in the work function metal layer 850, as shown in FIG. 10. In this embodiment, a damascene process is used to inlay the silicon dioxide film 930 in the recess. A silicon dioxide cap 940 is then selectively grown on top of the damascened silicon dioxide film 930, as shown in FIG. 11. The silicon dioxide cap 940 is grown so as to cover the entire gate stack and be wider than the gate stack, preferably extending beyond the outer edges of the gate spacer 418. This growth is seeded at the edges of the gate and the growing cap joins in the center of the gate stack, as shown in the cross-section of FIG. 11. In this embodiment, the silicon dioxide cap 940 is grown by MLD CVD Thus, the silicon oxide film 930 in the recess in the work function metal layer 850 acts as a seed to grow the silicon dioxide cap 940 above the gate stack. The silicon dioxide cap is self-aligned and grows only where it is needed.
Next, an interlayer dielectric 910 is deposited over the structure, as shown in FIG. 12. In this embodiment, the interlayer dielectric 910 is a nitride layer. A photolithography mask for the source/drain contacts is then deposited and patterned. An etch is then performed to form cavities for the source/drain contacts. This etch forms contact cavities through the interlayer dielectric 910 and dielectric layer 528, stopping on the semiconductor layer 106 (at least partially on the silicided area of the source/drain region). In this embodiment, a reactive ion etch (RIE) is used to form the contact cavities.
The silicon dioxide cap 940 on top of the gate stack serves as an etch stop layer during the etching for the contacts, guiding the source/drain contact away from the gate stack. Thus, the source/drain contact is borderless with respect to the gate stack. The contact cavities are then filled with a conducting material to form the source/drain contacts 920. In this embodiment, the source/drain contacts are formed by a metal, such as W, Cu, Al, or TiN. Conventional fabrication steps are then performed to form the remainder of the integrated circuit that includes this transistor.
The present invention is also applicable to gate-first fabrication with a full metal gate. In one embodiment, the final metal gate is capped with a nitride layer. By judiciously choosing materials, this nitride film can be selectively recessed with respect to the surrounding nitride interlayer dielectric. For example, the nitride cap material can be hydrogenated nitride film that has high wet etch rates, while the nitride interlayer dielectric can be IRAD nitride or PECVD nitride with a very low wet etch rate. The recess then can be formed through a wet etch in dilute HF. After the recess is formed, processing continues in the manner described above.
Accordingly, the present invention provides an SOI transistor with self-aligned borderless source/drain contacts. After formation of the gate stack, a shallow recess is made in one of the metal layers of the gate stack (e.g., the work function metal or the gate conductor). The recess is formed in less than all of the top-exposed layers of the gate stack, and preferably is formed in only one of the top-exposed layers of the gate stack. A dielectric film is formed in the recess and then used as a seed to selectively grow a dielectric cap over the gate stack. The dielectric cap protects the gate stack during the etching of the source/drain contacts. This borderless contact integration scheme can be used in gate-last fabrication processes that utilize a replacement metal gate structure and in gate-first fabrication processes that utilize a full metal gate.
It should be noted that some features of the present invention may be used in an embodiment thereof without use of other features of the present invention. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples, and exemplary embodiments of the present invention, and not a limitation thereof.
It should be understood that these embodiments are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.
The circuit as described above is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
The methods as discussed above are used in the fabrication of integrated circuit chips.
The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard, or other input device, and a central processor.
As required, detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure. Further, the terms and phrases used herein are not intended to be limiting; but rather, to provide an understandable description of the invention.
The terms “a” or “an”, as used herein, are defined as one as or more than one. The term plurality, as used herein, is defined as two as or more than two. Plural and singular terms are the same unless expressly stated otherwise. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically. The terms program, software application, and the like as used herein, are defined as a sequence of instructions designed for execution on a computer system. A program, computer program, or software application may include a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system.
Although specific embodiments of the invention have been disclosed, those having ordinary skill in the art will understand that changes can be made to the specific embodiments without departing from the spirit and scope of the invention. The scope of the invention is not to be restricted, therefore, to the specific embodiments, and it is intended that the appended claims cover any and all such applications, modifications, and embodiments within the scope of the present invention.

Claims

1-9. (canceled)

10. A transistor comprising:

a semiconductor layer;

a gate spacer located directly on the semiconductor layer;

a U-shaped gate dielectric comprising a horizontal portion located directly on the semiconductor layer and a vertical portion located on vertical sidewalls of the gate spacer, an upper surface of the gate spacer being co-planar with an upper surface of the vertical portion of the gate dielectric;

a U-shaped work function metal layer comprising a horizontal portion located directly on the horizontal portion of the gate dielectric and a vertical portion located on vertical sidewalls of the vertical portion of the gate dielectric;

a gate conductor comprising a conductive material, the gate conductor being located directly on the horizontal portion of the work function metal layer and abutting vertical sidewalls of the vertical portion of the work function metal layer;

a dielectric layer located on the semiconductor layer and abutting the gate spacer;

an oxide film located directly on one and only one of the work function metal layer and the gate conductor, an upper surface of the dielectric layer being co-planar with an upper surface of the oxide film and the upper surface of the vertical portion of the gate dielectric;

an oxide cap located directly on the upper surface of the vertical portion of the gate dielectric, the upper surface of the oxide film, and a portion of the upper surface of the dielectric layer;

source/drain regions located in the semiconductor layer; and

a source/drain contact passing through the dielectric layer and contacting an upper surface of one of the source/drain regions, a portion of the source/drain contact being located directly on the oxide cap.

11. The transistor of claim 10, further comprising:

a substrate; and

a buried insulator layer above the substrate, the semiconductor layer being located on the buried insulator layer.

12. The transistor of claim 10,

wherein the oxide film is located directly on the gate conductor and is not located directly on the work function metal layer,

the oxide cap is also located directly on an upper surface of the vertical portion of the work function metal layer, and

the upper surface of the vertical portion of the work function metal layer is also co-planar with the upper surface of the dielectric layer.

13. The transistor of claim 10,

wherein the oxide film is located directly on the work function metal layer and is not located directly on the gate conductor,

the oxide cap is also located directly on an upper surface of the gate conductor, and

the upper surface of the gate conductor is also co-planar with the upper surface of the dielectric layer.

14. The transistor of claim 10, further comprising an interlayer dielectric located on the dielectric layer and the oxide cap.

15. The transistor of claim 14, wherein the oxide film is composed of silicon oxide, the oxide cap is composed of silicon oxide, and the interlayer dielectric is composed of silicon nitride.

16. The transistor of claim 10, wherein a lateral extent of the oxide cap is greater than a lateral extent of the gate spacer.

17. The transistor of claim 10, wherein the oxide film has a thickness of less than about 8 nm.

18. The transistor of claim 10, wherein the oxide film has a thickness of about 5-10 nm.

19. An integrated circuit comprising a plurality of transistors, at least one of the transistors comprising:

a semiconductor layer;

a gate spacer located directly on the semiconductor layer;

source/drain regions located in the semiconductor layer; and

20. The integrated circuit of claim 19,

21. The integrated circuit of claim 19,

22. The integrated circuit of claim 19, wherein the at least one transistor further comprises:

an interlayer dielectric located on the dielectric layer and the oxide cap,

wherein the oxide film is composed of silicon oxide, the oxide cap is composed of silicon oxide, and the interlayer dielectric is composed of silicon nitride.

23. The integrated circuit of claim 19, wherein the oxide film has a thickness of less than about 10 nm.

24. The transistor of claim 10, wherein no portion of the oxide cap is located below the upper surface of the oxide film.

25. The transistor of claim 10, wherein the oxide cap is located above all of the U-shaped gate dielectric and all of the U-shaped work function metal layer.

26. The transistor of claim 10, wherein the oxide cap extends beyond outer edges of the gate spacer so that a combination of the oxide cap and the gate spacer encapsulates a gate stack comprising the U-shaped gate dielectric, the U-shaped work function metal layer, and the gate conductor.

27. The transistor of claim 10, wherein all of the oxide cap is located above a gate stack comprising the U-shaped gate dielectric, the U-shaped work function metal layer, and the gate conductor.

28. The integrated circuit of claim 19, wherein the oxide cap extends beyond outer edges of the gate spacer so that a combination of the oxide cap and the gate spacer encapsulates a gate stack comprising the U-shaped gate dielectric, the U-shaped work function metal layer, and the gate conductor.

29. The integrated circuit of claim 19, wherein all of the oxide cap is located above a gate stack comprising the U-shaped gate dielectric, the U-shaped work function metal layer, and the gate conductor.