TW200912876A - Display device, driving method of the same and electronic equipment incorporating the same - Google Patents

Abstract

Disclosed herein is a display device including: a pixel section having pixel circuits arranged to form a matrix with at least a plurality of columns, pixel data being written to each of the pixel circuits via a switching element; at least one scan line disposed to be associated with rows of the pixel circuits and adapted to control the conduction of the switching elements; a plurality of signal lines disposed to be associated with columns of the pixel circuits and adapted to convey the pixel data; and a horizontal driving circuit having a plurality of signal drivers, the plurality of signal drivers being associated with a plurality of groups into which the signal lines are divided, and being adapted to convey the image data supplied to the signal lines.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device having a thin film transistor used as a switching element formed on a transparent insulating substrate, a driving method thereof, and an electronic device including the same. And specific to the improvement of a signal line drive technology. The present invention includes Japanese Patent Application No. JP 2007-1 7 1691, filed on Sep. 29, 2007, the Japanese Patent Application, and Japanese Patent Application No. 8_1192 〇 1 related subject matter, the entire contents of which are incorporated herein by reference. [Prior Art] such as using a liquid crystal cell as a pixel display element (electrooptic element)

An output image.

Active matrix image display LCD display surface to display

Hz or higher, usually by the way, if the image frame rate is 6 〇 Hz or the eyes do not feel the screen flicker. However, at this frequency, it is felt in moving images and still images. In order to provide an improvement to this problem, that is, the blur can eliminate the blur in the moving image, 128893.doc 200912876 requires a frame frequency of 240 times four times higher than 60Hz, for example, in the Japanese Patent Licensing Publication 2006. No. 78505 (hereinafter referred to as patents) is not disclosed. As for the writing scheme using a thin film transistor (TF), the display method disclosed in the patent document uses a pixel displayed in order from the left side to write a human frame image within 1/240 of one second. Alternatively, the display method is performed by shifting the time and writing to the liquid crystal in (10) of -second and performing the update within 1/24 of a second (Patent 21 in Patent Document 1). On the other hand, one (four) is disclosed in Japanese Patent Laid-Open No. 8 (hereinafter referred to as Patent Document 2), which allows writing of video material at a data transmission rate of about MHz. The liquid crystal display device stores a data line in the memory circuit 2 via the old illustration as illustrated in the figure. Then, during the lower-line interval, the red (8) video data is selected from the same clothing blush (R) 'green (G) and blue (B) video data, and the video data is stored in a memory using switches q to 4_3 in the same place. In the body circuit 3. Next, the same device reads the data for the single-drive (four) scale from the memory circuit via a switch W (or 5_2 or 5_3). The switch to the Μ system uses the switch 1 to switch. The same device writes the data to the drive 仄w (or 6-2 or 6-3) and simultaneously writes the data to another drive ic. The same device uses the same-mode to write green (6) and blue (B) video data. This allows different video data pieces to be simultaneously written to individual drives! c. The liquid crystal display panel 7 displays the video based on the video material of the driver n ICs. However, in the above Patent Document 1, the description of the input timing (input method) regarding the image signal data to the 128893.doc 200912876 bead line driving circuit is not performed. A specific data writing system has not yet been established for the 24 Hz image frame frequency. On the other hand, the technique disclosed in Patent Document 2 writes the shirt image to the drives 1C 6-1 to 6-3 in synchronization with each other. Further, the data pieces supplied to the three drivers 1C are synchronized with each other. This condition causes an increase in noise at the leading edge or trailing edge of the clock between the image data and the adjacent writes, thereby causing voltage fluctuations of the image data and the pulse signal itself and making the data unstable in time. The input of the deformed image data causes an error in the image data of the driver 1C, thereby greatly reducing the image quality. A waveform formed by a buffer circuit produces a waveform that tends to be erroneous in data. Specifically, at frequencies above 100 MHZ, the noise between adjacent gauges in an electrical gauge or printed board is almost negligible. Today, VGA (800x600 pixels) requires 27 MHz and 1 〇 8 MHz clock frequencies at four times the frame rate. In addition, (4) UVGA (10) 0xl4 〇〇 pixels), the minimum clock frequency is 135 MHz. A frequency four times larger than 135 MHz is 54 〇 MHz, which cannot be controlled by a common printed board. This is why you need to split the driver. However, in terms of the proportion of the panel system, four or five divided drives are considered as limits. Under this condition, a potential is due to the high frequency component of the parasitic capacitance between adjacent writers that are adapted to supply signals to the abbreviated drive K:. This potential indicates itself as noise in the clock and image data, causing errors in the clock signal and image data and ultimately reducing the panel image quality. A fourth embodiment of the present invention provides a display device that allows "high frequency image poor material without degrading image quality, and provides a boat moving method thereof and an electronic device including the same. [Invention] According to the present invention The display device of the first embodiment includes a pixel segment, and the ancient slave Tf has a pixel circuit configured to form a matrix having at least a plurality of rows. The pixel data is written by the switch TL device to each of the dedicated pixel circuits. · ^¥, &amp; The beta display device further includes at least a scan line 'which is arranged to be associated with the columns of the pixel circuits The display device is adapted to control the conduction of the switching elements. The display device further includes a plurality of number lines </ RTI> arranged to be associated with the row of the pixel circuits The modulation device is adapted to convey the pixel data. The display device has a horizontal driving circuit of a plurality of signal drivers, and the signal drivers are separated from the signal lines by a virtual gamma 6 The knife-edge is associated with a plurality of groups, and

U is applicable to convey the image data supplied to the missing φ search line. The plurality of signal drivers drive the image data to the phase μ signal line to return a separate drive pulse. The drive pulses supplied to the signal drivers are offset in phase. Preferably, the data is fed to the signal drivers adjacent to each other in a split square noisy manner. Also preferably, the timing feeds the images to the signal drivers at the timing of the disc tracks. Preferably, the display device f+ includes a multiphase clock data generator. It is also preferred that the same generator employs and self-sees that the member rate jaws drive pulses at a frequency of two normal frequency frequencies to supply the drive pulses that are offset in phase with each other to the signal drivers. Preferably, the same generator splits the image data, reconfigures the segmented data pieces to a data configuration t suitable for input to the signal drivers, and supplies the data pieces. Preferably, the multiphase clock data generator supplies independent drive pulses that are offset in phase with each other to the signal drivers, respectively. Also preferably, the drive pulses comprise a clock pulse and a start pulse, respectively. Preferably, a time interval φ at which the drive pulses are offset in phase with each other is set to satisfy the relationship φ^(τ/2)/Ν, where (τ/2) is a half cycle of the image clock and Ν The number of divisions. Preferably, the display device includes a selector switch disposed between each of the signal drivers and their associated signal lines. Also preferably, the selector switch is adapted to select the image data in a time division manner. A display device uf driving method according to a second mode of the specific embodiment of the present invention includes a driving method of a pixel segment-display device, the 6-Hour pixel segment having a configuration to form at least a plurality of rows The pixel circuit of the moment p car. Pixel data is written to each of the pixel circuits via the -switching element. The display device further includes at least a "scan line", * # arranged to be associated with the columns of the pixel circuits and adapted to control conduction of the switching elements. The display device further includes a plurality of signal lines ‘ arranged to be associated with the rows of the pixel circuits and adapted to be dedicated = pixel data. The display device further includes a _ horizontal drive circuit having a plurality of letters \ drive a. The signal drivers are associated with a plurality of groups divided by lines 128893.doc 200912876 and adapted to convey the image data supplied to the signal lines. The driving method supplies separate drive pulses that are offset in phase with each other to the plurality of signal drivers such that each of the subscriber drivers communicates the image data to an associated signal line in response to the received drive pulse. A third mode of this embodiment of the invention is an electronic device comprising a display device. The display device includes a pixel segment having a pixel circuit configured to form an array having at least a plurality of rows. Pixel data is written to each of the pixel circuits via a switching element. The display device advancement includes at least one scan line disposed to be associated with the columns of the pixel circuits and adapted to control conduction of the switching elements. The display device further includes a plurality of signal lines arranged to be associated with the rows of the pixel circuits and adapted to communicate the pixel data. The display device further includes a horizontal drive circuit having a plurality of signal drivers. The signal driving n is associated with a plurality of groups into which the signal lines are divided, and is adapted to convey the image-bean material supplied to the money lines. Each of the plurality of 彳 § drives communicates the image data to the associated % &amp; line in response to the detach drive pulse. The drive pulses supplied to the signal drivers are offset in phase with each other. Embodiments of the present invention supply separate drive pulses that are offset in phase with each other to the plurality of signal drivers. Each of the signal drivers communicates the image data to the signal line in response to the received drive pulse. [Embodiment] 128893.doc 200912876 The specific embodiment of the present invention multi-guards, controls the clock, acts as a start pulse of the synchronization signal, and images and generates multi-phase pulses, thus permitting a method that does not degrade image quality. Load high frequency image data. A typical water circuit will be described before explaining this embodiment of the invention. Fig. 2 is a diagram showing an example of a driving pulse supplied to a blood-skinned running; &amp;; a signal driver of the octagonal water-driven circuit 130 as a comparative example of one of the examples. In this case, the signals are driven to cut into a plurality of horizontal display areas, wherein the image data is fed at four times the frequency. In this example, the image signal is loaded by the _ single 衩 clock, which is clear from Figure 2. m ,, ' 匕 'These signal drivers must process the control clock to be the input pulse of the data frequency of the clock synchronization. Even if an attempt is made to input the image data at four times the frequency to achieve the frame rate display under this condition, the image data may not be fed to the liquid crystal display 1 or not. The reason for this is that the signal driver ic Responsiveness and adaptability are used to convey the fragrance; the second lesser ~ the impedance of the cable like Bellow is not suitable for two frequencies. In addition, as illustrated in FIG. 3, it is said that the noise caused by the interference generated by the high frequency of the parasitic between the signal lines adversely affects the clock pulse itself and the Image data, you can't display an image properly. That is to say, the poor materials that are supplied to the drivers and crying Tpi are all in phase. This strain causes the image data as well as the adjacent edge of the clock between the adjacent folds and the adjacent writes, or the addition of the noise NIS, so that the button 兮 &amp; the edge of the image data and the pulse signal itself 128889. Doc 12 200912876 Electrical fluctuations and instability of the data and signals. In the example shown in FIG. 3, the potentials of the horizontal clock pulses HCK1, HCK2, HCKMHck4i^^ are mutually grown, as shown, for example, by reference numeral X in FIG. 3: daily pulse pulses HCK1, HCK2 HCK3ahck4 is derived from a synchronization number. It should be noted that the normal waveform of the image data IMD is displayed by the dashed line and the error portion is indicated by the solid line in Fig. 3.

As a solution to this problem, it is necessary to reduce the frequency supplied to the driving states of the signals and the phases of the offset clock pulses, hck2, and HCK4 to prevent noise growth. Incidentally, in vga, the clock frequency is 27 MHz at a frame frequency of 60 Hz, and the clock frequency is 108 MHz at a frame rate of four times ❻. In order to solve the above-described problems, the present embodiment multiplexes the clock, the start pulse used as a synchronization signal, and the image data to generate a multi-phase pulse, thereby permitting the loading of the high-frequency image data. The specific embodiments are described in detail below with reference to the accompanying drawings. Fig. 4 is a block diagram showing an example of the configuration of a liquid crystal display device in accordance with this embodiment of the present invention. A liquid crystal display device 100 includes an effective pixel section u, a vertical drive circuit (VDRV) 120, a horizontal drive circuit (HDRV) 13A, and a multi-phase clock data generator 140' as illustrated in FIG. The effective pixel section 110 has a plurality of pixel circuits 111 arranged in a matrix form. Each of the pixel circuits 111 includes a thin film transistor (TFT) 1 12 serving as a switching element, a liquid crystal cell! 13 and holding capacitor (storage capacitor) 128893.doc •13- 200912876 The liquid crystal unit 113 has its pixel electrode connected to the drain (or source) electrode of the TFT Π2. The holding capacitor Π4 has one of its electrodes connected to the electrodeless electrode of the TFT 112. The stone identical circuit 1 11 is provided with gate (scan) lines 115-1 to 1 15-m, and each column of the pixel circuits 1 has a gate line. Signal lines 116-1 to 116·n are arranged along the same circuit 111, and each row of the pixel circuits 111 is a signal line. Γ

The TFTs 112 of the pixel circuits 1 in each column have their gate electrodes connected to the same-gate (scan) line (the TFT i of the pixel circuit 11 i in each row of one of the claws p) 12 all have their source (or drain) electrodes connected to the same signal line (one of 116-1 to 116_n). In addition, the liquid crystal cell 113 has its pixel electrode connected to the drain electrode of the TFT ΐ2 and makes it relatively The electrodes are connected to a common line 117. The holding capacitor ι4 is connected between the drain electrode of the TFT 112 and the common line 117. The common line U7 is supplied with a shirt exchange money as a common voltage core of the VCOM circuit. (10) 'The circuit is integrally formed with the driving and other circuits on the glass substrate. Each of the prime circuits U1 is written to the holding capacitor 114 via the TFT U2 serving as a switching element, and is electrically connected. According to the pixel data written to the holding grid 114, the liquid crystal display device displays an image by controlling the transmittance of a pair of undisclosed light. For the eclipse not showing the &quot;&quot; Based on the surface of the liquid crystal arrangement of the unit 113, and the other lines is arranged on the back surface thereof.

The gate line 115-1 to 1 s m and enter A. Production line u "Guangzhou by the vertical drive power (four) drive m 仏唬 line 116-1 to U6-n 邱 邱 Qiushan, Wang 0P by horizontal drive circuit 130A drive 128893.doc -14- 200912876 In response to a vertical start signal VST, a vertical clock VCK, and an enable signal = excitation, the vertical drive circuit (10) vertically scans the pixel circuit i n connected to the scan lines U5-! to 115, respectively, in order, according to the column by column. The same circuit 1 1 1 is selected. That is, when a closed-pole pulse GP1 is supplied to the gate line by the vertical drive circuit 120, the pixel in the -first column is selected. When the scan pulse GP2 is supplied to the gate line 115_2 Selecting the pixels in the second column. Similarly, the gate pulses GP3 to GPM are respectively supplied to the gate lines 115_3 to 115_. It should be noted that the timing controller is different from the one of the multiphase clock data generators 14 The separation does not show that the second timing controller generates the vertical start signal vst, the vertical clock VCK, and the enable signal enab. The first timing controller and hst, hckl, hck2, hck3 such as supplied to the multiphase clock data generator 1 , hck4 and data d0 horizontal signal synchronous operation The vertical drive circuit 120 and the enable horizontal drive circuit 13A output data to the - wheel enable signal 〇 TEN of the # line lines 116-1 to 116-n are synchronized. The horizontal drive circuit 130A divides the signal lines into a plurality of signals. Groups (four groups in the present embodiment based on the simplification of the description). One of the signal drivers 131 to ι 34 is provided for each group. Figure 6 illustrates the signal supplied to the horizontal drive circuit 13 An example of the drive pulses of the drivers 131 to 13 4. In the present embodiment, the drive pulses are separately supplied to the signals 128893.doc 200912876 drivers 131 to 134. Each of the drive pulses includes a horizontal start pulse HST and horizontal clock pulse hck^ horizontal start pulse HST is used to guide the start of a horizontal scan. The horizontal clock pulse HCK is used as a reference for horizontal scanning. A horizontal start pulse HST2 supplied to the signal driver 丨32 is supplied from the source. One of the horizontal start pulses HST1 of the signal driver 131 is offset (delayed) by 1/4 of a clock period in phase. Similarly, a horizontal start pulse HST3 is supplied to the signal driver 133. The horizontal start pulse HST2 supplied to the signal driver i 32 is offset (delayed) by 1/4 of a clock period in phase. A horizontal start pulse HST4 supplied to the signal driver 134 is supplied from one of the #唬 drivers 133. The horizontal start pulse HST3 is offset (delayed) in phase by one quarter of a clock cycle. A horizontal clock pulse 11 supplied to the ## driver 132 (:1&lt;:2 is supplied from one of the levels to the nickname driver 13 1 The clock pulse HCK 偏移 is offset (delayed) in phase by one-fourth of a clock period. Similarly, a horizontal clock pulse HCK3 supplied to the signal driver 13 is offset (delayed) by 1/4 of a clock period from the horizontal clock pulse HCK2 supplied to the k-number driver 132. A horizontal clock pulse HCK4 supplied to the 彳5 driver 134 is offset (delayed) by 丨/4 of one clock period from one horizontal clock pulse HCK3 supplied to the 仏 driver 133. In the example shown in Figures 4 and 6, signal driver 131 generates a sample pulse in response to a horizontal start 128893.doc -16 - 200912876 pulse HST1 that is adapted to direct the initiation of a horizontal scan and is used as a horizontal scan. Reference horizontal pulse pulse HCK1. The horizontal start pulse HST1 and the horizontal clock pulse HCK1 are supplied from the multiphase clock data generator ι4〇. The signal driver 1 3 1 sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulse and supplies the data to the signal line ία" to 11 6-3 as a write to the pixel circuit. 1丨丨 data signal. Signal driver 132 generates a sample pulse in response to a horizontal start pulse HST2 that is adapted to direct the initiation of a horizontal scan and a horizontal clock pulse HCK2 that serves as a reference for a horizontal scan. The horizontal start pulse HST2 and the horizontal clock pulse HCK2 are supplied from the multiphase clock data generator 140. The signal driver 132 sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulse and supplies the data to the signal lines 丨丨6_4 to 11 6 - 6 as writing to the pixel circuit 111. Information signal. The signal driver 133 generates a sampling pulse in response to a horizontal start pulse HST3 adapted to direct the start of the horizontal % and a horizontal clock pulse HCK3 used as a reference for a horizontal scan. The horizontal start pulse HST3 and the horizontal clock pulse HCK3 are supplied from the multiphase clock data generator 140. The L driver 13 3 sequentially samples the input image data r (red), g (green), and B (blue) in response to the generated sampling pulse and supplies the data to the signal line i Μ - ? to 116-9 as a write to the pixel. The data signal of circuit 111. The L-drive 134 generates a sampling pulse in response to a horizontal start pulse HST4 that is adapted to direct the start of the horizontal scan and a horizontal clock pulse HCK4 that serves as a reference for a horizontal scan. The horizontal start pulse HST4 and the horizontal clock pulse hck4 are supplied from the multiphase clock data generator 140. 128893.doc 17 200912876 Signal driver 1 3 4 samples the input image data R (red), G (green) and B (blue) in order to respond to the generated sampling pulse and supplies the data to signal lines 116_1〇 to 116-12 as write The data signal that is input to the pixel circuit 11 1 . As explained above, the present embodiment divides the plurality of signal lines into the plurality of groups in the horizontal drive circuit 1 30A. One of the plurality (four in the present embodiment) of signal drivers 131 through 134 provides each of the groups of the signal lines to communicate the image data.

The horizontal start pulses HST1, HST2, HST3, and HST4 and the horizontal clock pulses HCK1, HCK2, HCK3, and HCK4 are offset in phase with each other. These pulses are used as drive pulses adapted to control the driving of the plurality of signal drivers 131 to 134. More specifically, the data is fed to the signal drivers 131 to 134 adjacent to each other in a divided manner. The signal drivers 131 to 134 are controlled by horizontal clock pulses HCK1 to hck4 having respective phases independent of each other and a horizontal start pulse. The image data is fed at a timing synchronized with the independent pulses and the start pulse. That is, the number drivers 131 to 134 operate by arbitrarily offsetting the horizontal start pulse HST and the horizontal clock pulse (1/4 of the clock period in this embodiment) as shown in Figs. The last image signal is output in synchronization with the output enable signal OTEN. : The slap can use the clock pulse, the start pulse and the image data to drive the material (4) at a lower frequency than the original frequency. The reason for driving the horizontal drive power 128893.doc 200912876 way 130A is explained in the above specific embodiment as described above. If the image frame rate is 60 Hz or higher, the screen will usually not feel the flicker. However, at this frequency, people can feel the blur in moving images and still images. To provide an improvement to this problem, a frame frequency of 240 Hz is required to eliminate blurring in the moving image. Therefore, if there is a problem with the moving image characteristics of an active matrix display device today, such characteristics are improved by displaying an image, which uses a number of frames displayed four times larger than the normal number and is compared with the normal map. The frame frequency is four times larger than the frame frequency. The normal frame frequency is 6 〇 Hz. Therefore, the quadruple frame frequency is 240 Hz. Normally, the clock frequency is 135 MHz in UXGA (1600xRGBxl20〇). Ordinary 矽ic can operate at this frequency. However, if the frame frequency is four times larger, the clock frequency is 54 〇 MHz.矽1C is more difficult to operate at this high frequency. Further, the image signal generated at this frequency can be easily transmitted to the liquid crystal device via the cable due to interference between the signal lines. The frequency must be reduced to overcome the above problem. This embodiment maintains the image data clock while providing a reduced frequency. Next, the multiphase clock data generator 丨4 说明 will be described. The multiphase clock data generator 140 receives the horizontal start pulse hst and the horizontal clock pulses hck1 to hck4 and divides the pulses into 1/4 frequencies. Never shown 128893.doc •19- 200912876 Figure 1C supplies the horizontal start pulse hst and the horizontal clock pulses hckl to hck4, for example at a frequency four times higher than the normal frequency. The multiphase clock data generator 140 supplies the horizontal start pulse HST1 and the horizontal clock pulse HCK1 from the divided frequency to the signal driver 13 1 of the horizontal drive circuit 130A. The horizontal clock pulse HCK1 is offset (delayed) from the horizontal start pulse HST1 by 丨/4 of one clock period. Further, the multiphase clock data generator 14 generates a horizontal start pulse HST2' which is offset (delayed) from the horizontal start pulse HST1 by 1/4 of a clock period. The same generator 14 turns the horizontally activated pulse HST2 and the horizontal clock pulse HCK2 from the divided frequency to the signal driver 132 of the horizontal drive circuit 130A. The horizontal clock pulse HCK2 is offset (delayed) from the horizontal start pulse HST2 by 1/4 of a clock period. Further, the multi-phase clock data generator 140 generates a horizontal start pulse HST3 which is offset (delayed) from the horizontal start pulse HST2 by 1/4 of a clock period. The same generator 14 turns the horizontally activated pulse HST3 and the horizontal clock pulse HCK3 from the divided frequency to the signal driver 133 of the horizontal drive circuit 130A. The horizontal clock pulse HCK3 is offset (delayed) from the horizontal start pulse HST3 by 1/4 of a clock period. Further, the multiphase clock data generator 14 generates a horizontal start pulse HST4 which is offset (delayed) from the horizontal start pulse HST3 by 1/4 of a clock period. The same generator 14 turns the horizontally activated pulse HST4 and the horizontal clock pulse HCK4 from the divided frequency to the signal driver 134 of the horizontal drive circuit 丨3 〇a. The horizontal clock pulse HCK4# is offset (delayed) from the horizontal start pulse 黯4 by 丨/4 of one clock period. 128893.doc •20- 200912876 A time interval φ in which the clock pulses are offset in phase with each other is set to satisfy the relationship φ &lt;(τ/2)/ν, where (τ/2) is The half cycle of the image clock and the number of crossovers. In addition, the multiphase clock data generator 140 places the supplied image data ribs in the line buffer. Then, the same generator 14 重新 reconfigures the image data that has been divided and configured in the online memory buffer into a plurality of (four in this embodiment) line memory buffers, and then The data is supplied from the individual line memory buffer circuits to the signal drivers. Figure 7 is a diagram illustrating a particular configuration example of a multiphase clock data generator 14 in accordance with the present embodiment. Fig. 8 is a view showing an example of timing control and data writing after frequency division by the multiphase clock data generator according to the present embodiment. The multiphase clock data generator 140 includes a timing controller (Tc) 141, a data memory buffer counter 142, a first counter flip flop (CNT/FF) 143, a second CNT/FF 144, and a third CNT/ FF 145 and fourth CNT/FF 146. In response to the start pulse hsti and the horizontal clock pulses hck1 to hck4 at a frequency four times higher than the normal frequency, the timing controller 141 supplies the trigger point signals a1 to a4 to the first to fourth CNT/FF m 5 1 μ 々乐143 to W6. The trigger point signals a 1 to a4 are offset by φ in phase with each other. The more recent timing controller 141 supplies the trigger point signal a 1 to the first CNT/FF 143. The same controller 141 supplies a trigger point signal a2 to a second CNT/FF 丨 44 offset from the trigger point signal 128893.doc -21 - 200912876 in phase Φ. Further, the controller 141 supplies the trigger point signal a3 to the third CNT/FF 145 which are offset from the trigger point signal a2 by Φ in phase. The same controller ΐ4ι supplies the trigger point signal which is offset from the trigger point signal a3 by φ to the fourth CNT/FF 146. In addition, the timing controller (4) supplies the trigger point signals bl to b4 to the data memory buffer counter 142 in order to activate the pulse hsti and the horizontal clock pulse hekmek4 at a frequency four times higher than the normal frequency. The trigger point signals b 1 to b4 are offset φ in phase with each other. More slowly, the timing controller 丨4丨 supplies the trigger point signal b 到 to the data memory buffer counter 142. The trigger point signal b2 is offset from the trigger point signal b 1 by φ in phase. In addition, the timing controller 141 supplies the trigger point signal to "to the data memory buffer meter S 142. The trigger point signal b3 is offset in phase Φ from the trigger point signal 。. The material point signal b4 is from the trigger point signal (four) phase The ground offset φ 〇 should be noted that the timing controller 141 generates the trigger point signals 31 to 34 and bl to b4 so that the signals are maintained in synchronization with each other. The timing controller 141 generates an output enable signal OTEN serving as a horizontal interval control signal and The signal is output to the horizontal drive circuit and the vertical drive circuit. In response to the input data do, the data memory buffer counter 142 and the trigger point signal from the timing controller 141 are "four times longer than the period of the synchronization extension data". The same counter 142 reconfigures the data d0 in the data pieces di, 128893.doc • 22· 200912876 D2 D3 D4, etc. and outputs the data pieces. These data pieces, D2, D3, D4, etc. are offset by φ in phase with each other. The reconfigured data pieces D1, D2, D3, D4, etc. are composed of R (red) and G (green) ΛΒ (blue) data. The first-CNT/FF 143 splits the horizontal start pulse hst and the horizontal clock pulse hckl in response to the trigger point signal u. The first CNT/FF 143 supplies the horizontal drive pulse HST1 and the horizontal clock pulse HCK1 from the divided frequency to the signal driver 13 1 of the horizontal drive circuit 13A. The horizontal clock pulse HCK1 is offset (delayed) from the horizontal start pulse HST1 by 1/4 of a clock period. The second CNT/FF 144 uses the frequency division horizontal start pulse hst and the horizontal clock pulse hck2 in response to the trigger point signal a2. The second cnt/FF 144 produces a horizontal start pulse HST2 which is offset (delayed) from the horizontal start pulse HST 1 by 1/4 of a clock period. The second CNT/FF 144 supplies the horizontal start pulse HST2 and the horizontal clock pulse HCK2 to the signal driver 132 of the horizontal drive circuit 13A. The horizontal clock pulse HCK2 obtained from the frequency division is offset (delayed) from the horizontal start pulse HST2 by 1/4 of a clock period. The third CNT/FF 145 uses the frequency division horizontal start pulse hst and the horizontal clock pulse hck3 in response to the trigger point signal a3. The third CNT/FF 145 also produces a horizontal start pulse HST3 which is offset (delayed) from the horizontal start pulse HST2 by 1/4 of a clock period. The third CNT/FF 145 supplies the horizontal start pulse HST3 and the horizontal clock pulse HCK3 to the signal driver 133 of the horizontal drive circuit 130A. The horizontal clock pulse HCK3 derived from the frequency division is offset in phase from the horizontal start pulse HST3 128893.doc -23- 200912876 (delay) 1/4 of a clock cycle. The fourth CNT/FF 146 uses the frequency division horizontal start pulse hst and the horizontal clock pulse hck4 in response to the trigger point signal a4e. The fourth cnt/FF 146 generates a horizontal start pulse HST4 which is offset in phase from the horizontal start pulse HST3 (delay ) 1 / 4 of a clock cycle. The fourth CNT/FF 146 supplies the horizontal start pulse HST4 and the horizontal clock pulse HCK4 to the signal driver 134 of the horizontal drive circuit 13A. From frequency division

The horizontal clock pulse HCK4 is offset (delayed) from the horizontal start pulse HST4 by 1/4 of a clock period. As explained above, to display an image at a frame rate four times higher, the multiphase clock data generator 140 receives horizontal clock pulses hck 1 to hck4 and horizontal clock pulses at a frequency four times higher than the normal frequency. The hck丨 to hck4 synchronized horizontal drive start pulse hst, as illustrated in FIG. The timing controller 141 stores a horizontal interval from the horizontal clock pulse 11 (^1 to 11 (^4 and the start pulse hst to generate the trigger point signal ^ to .... in response to the trigger point signal ^ to ...), the data memory buffer counter 142 stores a horizontal interval. The horizontal image data is reconfigured to fit the signal drivers 131 to 134 that are independently configured with each other. The output and input data intervals in a horizontal interval are displayed here. These intervals allow processing of the data. Here, τ Indicates the horizontal clock pulse used as the control clock of the signal driver (Ic). T1 indicates the data interval in the horizontal interval after the frequency division into the _ Bay rate. T2 indicates a positive horizontal interval. The data interval 'and T3 indicate a horizontal interval. 128893.doc •24· 200912876 The following relationship remains between the above intervals. T3 &gt; ΤΙ &gt; T2 is the data in a horizontal interval after dividing into 1/4 frequency The interval T1 is longer than the original &gt; interval T2 in a horizontal interval of one of the high frequencies before the frequency division into the 1/4 frequency, but shorter than the horizontal interval T3. This relationship must be satisfied to be full. Timing diagrams for providing different functions of the present embodiment. Further, as illustrated in FIGS. 7 and 8, the CNT/FFs 143 to 146 independent of each other generate horizontal clock pulses HCK1 to HCK4 and horizontal start pulses ^^^^ to HST4. They are offset in phase with each other and supplied to the signal drivers 131 to 134 of the present embodiment. The image clock pulse hck and the start pulse hst used as the sync 彳5 are fed from the original video source to the CNT/FF 143 to Each of the pulses is divided by the frequency under the control of the timing controller 141. In addition, the simultaneously fed image data is also frequency-divided and arranged in the data memory buffer counter 142. Then, The image data ribs are reconfigured in the four independent data pieces D1 to D4. Therefore, the CNT/FFs 143 to 140, that is, the line memory buffers 143 to 146 can supply independent outputs to the signal drivers. The frequency clock shifts the data in phase according to the division frequency. As explained above and indicated by the reference numeral γ in Fig. 9, the horizontal clock pulse HCK1 is offset in phase from the horizontal clock pulse HCK2. The horizontal clock pulse HCK1 is only affected by the noise of the horizontal clock pulse HCK2, 128893.doc -25- 200912876. Similarly, the horizontal clock pulse HCK2 is only affected by the horizontal clock pulse, ie the noise of the NIS. That is, there is less noise generated by the superposition of the potentials of the horizontal clock pulses Hck 1, HCK2, HCK3, and HCK4 caused by the synchronization signal. Therefore, the buffers are not displayed by the s-number drivers 131 to 134. The image data IMD after the formation of the circuit exhibits a normal rectangular waveform which is inferior to the error portion shown by the reference numeral 图 in FIG. The time interval φ at which the clock pulses are offset in phase with each other is equal to half the period of the image clock divided by the number of divisions of integers, or less. This relationship can be expressed by Φ€(Τ/2)/Ν. The operation of the liquid crystal display device 100 configured as explained above will be explained with reference to Figs. As illustrated in Fig. 4, the 'vertical drive circuit 12' selects the pixel circuit 111 column by column in order to respond to the vertical enable signal VST, the vertical clock VCK, and the enable signal ENAB as illustrated in FIG. The pixel circuit in which is connected to the scan lines 115-1 to 115-m is vertically scanned for each field interval of the individual signal 'the vertical drive circuit 120', so that the same circuit 111 is selected in order according to the column by column. The multiphase clock data generator 140 receives the horizontal start pulse hst and the horizontal clock pulses hck1 to hck4 and divides the pulses into 1/4 frequencies. The graph 1C is never shown to supply the horizontal start pulse hst and the horizontal clock pulses hckl to hck4, for example at a frequency four times higher than the normal frequency. The multiphase clock data generator 140 supplies the horizontal start pulse 128893.doc -26·200912876 HST1 and the horizontal clock pulse HCK1 to the horizontal drive circuit 130A. The signal driver 131 ° horizontal clock pulse hckI is from the horizontal start pulse. HST1 is offset (delayed) by 丨/4 of one clock period in phase. Similarly, the multi-phase clock data generator 14 generates a horizontal start pulse HST2' which is offset (delayed) from the horizontal start pulse HST1 by 1/4 of a clock period. The same generator 140 supplies the horizontal drive pulse HST2 and the horizontal clock pulse HCK2 from the divided frequency to the signal driver 13 2 of the horizontal drive circuit 13 3A. The horizontal clock pulse HCK2 is offset (delayed) from the horizontal start pulse HST2 by 1/4 of a clock period. Further, the multi-phase clock data generator i 4 〇 generates a horizontal start pulse HST3 ' which is offset (delayed) from the horizontal start pulse HST2 by 1/4 of a clock period. The same generator 140 supplies the horizontal start pulse HST3 and the horizontal clock pulse HCK3 from the divided frequency to the signal driver 133 of the horizontal drive circuit 130A. The horizontal clock pulse HCK3 is offset (delayed) from the horizontal start pulse HST3 by 1/4 of a clock period. Further, the multi-phase clock data generator 14 generates a horizontal start pulse HST4 which is offset (delayed) from the horizontal start pulse hST3 by 1/4 of a clock period. The same generator 140 supplies the horizontal drive pulse HST4 and the horizontal clock pulse HCK4 from the divided frequency to the signal driver 134 of the horizontal drive circuit 130A. The horizontal clock pulse HCK4 is offset (delayed) from the horizontal start pulse HST4 by 1/4 of a clock period. 128893.doc -27- 200912876 In addition, the multiphase clock data generator 140 arranges the supplied image data to be placed in the line buffer. Then, the same generator H〇 re-aligns the image data that has been divided and arranged in the line, and the plurality of (in the present embodiment, four) line memories The data is then buffered and then supplied from the individual line memory buffer circuits (Fig. 8) to the 4k driver. The 唬 driver 131 generates a sampling pulse in response to the horizontal start pulse HST1 adapted to direct the start of the horizontal scan and the horizontal clock pulse HCK used as a reference for a horizontal scan to supply the level from the polyphase clock data generator 140. Start pulse HST丨 and horizontal clock pulse i. In addition, the signal driver i 3 取样 sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulses. The ## driver 13 1 supplies the data to the line b 116-1 to 116_3 in synchronization with the output enable signal OTEN as a material signal written to the pixel circuit lu. Similarly, the 彳s driver i 3 2 generates a sampling pulse in response to the horizontal start pulse hST2 adapted to initiate the initiation of a horizontal scan and the horizontal clock pulse HCK2 used as a reference for horizontal scanning. The horizontal start pulse HST2 and the horizontal clock pulse HCK2 are offset in phase from the horizontal start pulse and the horizontal clock pulse HCK1, respectively. In addition, the signal driver 132 sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulses. The 乜唬 driver 132 supplies the data to the k-th lines 11 6-4 to 116_6 in synchronization with the output enable signal 〇 TEN as a material signal written to the pixel circuit ln. The ## driver 133 generates a sampling pulse in response to the horizontal start pulse HST3 that is adapted to guide the start of a horizontal scan of 128893.doc -28-200912876 and the horizontal clock pulse HCK3 used as a reference for a horizontal scan. The horizontal start pulse HST3 and the horizontal clock pulse HCK3 are offset in phase from the horizontal start pulse HST2 and the horizontal clock pulse HCK2, respectively. Further, the 'signal driver 133' sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulses.

The ^-number driver 133 supplies the data to the #-number lines 116-7 to 116-9 in synchronization with the output enable signal oten as a material signal written to the pixel circuit n丨. The t-wave driver 134 generates a sample pulse in response to a horizontal start pulse HST4 that is adapted to direct the start of the horizontal scan and a horizontal clock pulse HCK4 that serves as a reference for a horizontal sense. The horizontal start pulse HST4&amp; horizontal clock pulse HCK4 is offset in phase from the horizontal start pulse HST3 and the horizontal clock pulse HCK3, respectively. In addition, the 'h driver i 34 sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulse. The nickname driver 134 supplies the data to the L-number lines 116_1 〇 to 116_12 in synchronization with the output enable signal OTEN as writing to the pixel circuit 1. Information signal. It should be noted that the vertical drive circuit 12 can output a gate pulse in response to the high-level Hi·element ε π &amp; k to the low-level output enable signal oten at the trailing edge of the same-sister rjTcxT L is OTEN. The same signal OTEN enables the horizontal drive circuit 13A to output data to the signal line m-en". As described above, a plurality of groups. The specific embodiment divides the plurality of signal lines into each of the groups. One of the plurality of signal drivers i 3 i to 134 that is adapted to convey the image data for the # # 893.doc -29- 200912876 should be given to the ## line. Horizontal start pulses HST1, HST2, HST3 and HST4 And horizontal clock pulses HCK1, HCK2, HCK3, and HCK4 are offset in phase with each other. These pulses are used as drive pulses that are adapted to control the driving of the plurality of signal drivers 131-134. Horizontal clock pulse HCK丨 to hck4 and f

The horizontal start pulse HST1sHST4 is used to control the signal drivers 131 to 134. The image data is fed at a timing synchronized with the independent clocks and start pulses. In the present embodiment, the signal drivers i3i to 134 operate by arbitrarily offsetting the horizontal start pulse HST and the horizontal clock pulse in the same phase. The last image signal is output in synchronization with the output enable signal 〇 T E N . The signals can be driven by the clock pulses, the start pulses, and the image data at frequencies lower than the original frequency. Port: This can transmit high-resolution images at high speed without reducing any images. In addition, the display (4) frame rate image scrolling is provided with the existing frame frequency. The greatly improved moving image feature' eliminates the imager, thus allowing for low-cost rotation: a high-speed image signal driver designed like a signal driver.胄Special use should be noted ‘When image data is written to the panel by time division 128893.doc • 30· 200912876 H This embodiment of the invention is also effective. This embodiment of the invention is applicable when the time division switch is used as illustrated in Fig. 1 ′, especially in the case where the number of time divisions does not adequately match the electrical and image characteristics within the horizontal selection interval. In this case, as explained above, the signal drivers divide the clock pulse (control pulse), the start pulse, and the input frequency of the image data. In Fig. 10, a signal 3¥ from the signal drivers 131 to 134 is transmitted to the signal line 1 16 (1 16-1 to 116-12) via the selector SEL having a plurality of transmission gates TMG, respectively. In the conduction, the transmission gate TMG (analog switch) is controlled by a selection signal Si, its inverted signal XS1, the selection signal S2, its inverted signal XS2, the selection signal S3, its inverted signal χδ3, and the like. As explained above, a high definition (UXGA) and high frame rate active matrix display device can use a selector to time split drive 'which ensures a reduced number of connection terminals in the mechanical connector and improved reliability. It should be noted that CMOS signaling, LVDS (low voltage differential signaling) or TMDS (minimized transition differential signaling) can be used to transmit the digital data used in this embodiment. These transmission schemes are used on the input and output sides of the multiphase clock data generator 140. An active matrix display device, and typically an active matrix liquid crystal display device, is used as one of OA devices (e.g., personal computers and word processors and televisions). Moreover, the present display device is particularly suitable for use as one of the display sections of electronic devices such as mobile phones and PDAs whose bodies are increasingly smaller and tighter. 128893.doc • 31 - 200912876 That is, the liquid crystal display device 100 according to the present embodiment can be applied to various electronic devices illustrated in FIGS. 11 to 11G. For example, the same device 100 can be applied to one of electronic devices (including digital cameras, laptop personal computers, mobile phones, and camcorders) in all fields. These pieces of equipment are designed to display an image or video of a video signal that is fed to or generated within the electronic device. • An example of the above-described electronic device to which the specific embodiment of the present invention is applied is shown below. Fig. 11A illustrates a television set to which the embodiment of the present invention is applied as an example. The television set 300 includes a video display screen 3〇3 which is comprised of, for example, a front panel 301, a filter glass 302, and other components. The television set is manufactured by using the display device according to this embodiment of the present invention as a visual display screen 303. Figures UB and 11C illustrate a digital camera 3 10 to which the embodiment of the present invention is applied as an example. The digital camera 3A includes an imaging lens 〇 U flash emission section 312, a display section 313, a control switch 314, and other parts. The digital camera is manufactured by using the display device according to this embodiment of the present invention as the display section 313. Figure 1 1D illustrates a camcorder to which a particular embodiment of the present invention is applied. The camcorder 32A includes a main body section 321, a lens 322 provided on the side surface facing the front to image an object, an image start/stop switch (2), a display section 324, and other parts. The video camera is manufactured by using the display device according to the present invention and the #gastric embodiment as a display section. 128893.doc -32-

It should be noted that the apparatus in which the present invention is equally applicable to other active matrix display devices, optical (EL) elements as each of the pixels has been applied. 200912876 Figure 1 1E and 1 IF illustrate a mobile terminal device 330 to which the particular embodiment of the present invention is applied. The mobile terminal device 33A includes an upper housing 331, a lower outer casing 332, a connecting section (in this example, a hinge section) 333, a display 334, a sub-display 335, an image light 336, a camera 337, and other parts. . The mobile terminal device is manufactured by using the display device according to the embodiment of the present invention as the display 334 and the sub-display 335. Figure 1 1G illustrates a laptop personal computer 340 to which the specific embodiment of the present invention is applied. The laptop personal computer 34 includes a keyboard 342 adapted to manipulate input text or other information in a body 341, a display section 343 adapted to display an image, and other parts. A laptop personal computer is manufactured by using the display device according to this embodiment of the present invention as the display section 343. The above specific embodiment will be described as an example in the case of an active matrix liquid crystal display device. However, the specific embodiment of the present invention is not limited thereto, but for example, an EL display using an electroluminescent optical element. Those skilled in the art should understand that various modifications, combinations, subgroups, and skins may be based on design requirements and others. Factors out of % + Mountain Brothers are required to be within the scope of the accompanying patent application or its equivalent. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a diagram illustrating a prior art diagram that allows data of about 200; the data transfer rate of MHz is written to video 128893.doc • 33· 200912876 Figure 2 is a diagram illustrating a signal driver supplied to a typical horizontal drive circuit An example of a driving pulse is taken as a comparative example of the present embodiment; FIG. 3 is a diagram illustrating a problem of the driving pulse in FIG. 2; and FIG. 4 is a view showing a liquid crystal display device according to the embodiment of the present invention. A block diagram of a configuration example; FIG. 5 is a waveform diagram illustrating a relationship between an output enable signal and a gate pulse; FIG. 6 is an illustration of an example of a drive pulse of the signal drivers supplied to the horizontal drive circuit Figure 7 is a diagram illustrating a specific configuration example of a multiphase clock data generator in accordance with the present embodiment; Figure 8 is a diagram illustrating the multiphase clock data generator in accordance with the present embodiment. FIG. 9 is a diagram illustrating an effect of the specific embodiment; FIG. 9 is a diagram illustrating the effect of the specific embodiment; FIG. The particular configuration of the invention, a block diagram of one example of apparatus of the liquid crystal display of Example; and FIGS. 11A to 11G based illustrating examples of electronic equipment using display device according to the embodiment of the present specific embodiment. FIG. [Main component symbol description] 1 Switch 2 Memory circuit 3 Memory circuit 4-1 to 4-3 Switch 128893.doc • 34- 200912876

5-1 to 5-3 Switch 6-1 to 6-3 Driver 1C 7 Liquid crystal panel 100 Liquid crystal display device 110 Effective pixel section 111 Pixel circuit 112 Thin film transistor (TFT) 113 Liquid crystal cell 114 Holding capacitor 115-1 to 115-m gate line 116-1 to 116-n signal line 117 common line 120 vertical drive circuit (VDRV) 130 horizontal drive circuit 130A horizontal drive circuit (HDRV) 131 signal driver 132 signal driver 133 signal driver 134 signal driver 140 Phase clock data generator 141 Timing controller (TC) 142 Data memory buffer counter 143 First counter flip-flop (CNT/FF) 144 Second CNT/FF 128893.doc -35- 200912876 145 Third CNT /FF 146 Fourth CNT/FF 300 TV 301 Front panel 302 Filter glass 303 Video display screen 310 Digital camera 311 Imaging lens 312 Flash emission section 313 Display section 314 Control switch 320 Camcorder 321 Body section 322 Lens 323 imaging start/stop switch 324 display section 330 mobile terminal device 331 upper housing 332 lower housing 333 connection section 334 display 335 sub-display 336 the camera image 337 lamp 128893.doc - 36 - 200912876 340 341 a laptop personal computer main body section 343 does not significantly selector SEL TMG transmission gate 128893.doc -37-

Claims (1)

200912876 X. Patent application scope: A display device comprising: a prime segment 'having a pixel circuit formed by a matrix to form a matrix circuit having a row, through which each of the pixel circuits; Pixel data is written to at least a scan line 'which is arranged to be associated with a column of the pixel circuits' and adapted to control conduction of the #_ element; a plurality of signal lines arranged to be associated with the rows of the pixel circuits and adapted to convey the pixel data; and: a horizontal drive circuit having a plurality of signal drivers, the plurality of semaphore drivers being associated with the plurality of signal drivers The plurality of groups divided by the equal signal lines are associated and adapted to convey image data supplied to the signal lines, wherein each of the plurality of 彳§ drivers transmits the image data to the correlation %彳Line 5, in response to a separate drive pulse, and the drive pulses supplied to the signal drivers are offset in phase with each other. 2. The display device of claim 1, wherein the data is fed to the signal drivers adjacent to each other in a split-segment manner, and the image data is fed to the signal drivers at timing synchronized with the drive pulses. 3. A display device as claimed in claim 1, comprising: a multiphase clock data generator adapted to use a frequency to divide the drive pulse at a frequency of a positive rate of 128893.doc 200912876 to supply each other The drive pulses are offset in phase with each other to the signal drivers, and the multi-phase clock-bead generator is also adapted to split the image data, reconfiguring the segmented data pieces to be suitable for input to the signals The data configuration of the drive is configured to supply the data piece. 4. The display device of claim 2, comprising: a multiphase clock data generator adapted to divide the frequency by a frequency higher than a normal frequency Driving pulses to supply the drive pulses that are offset in phase with each other to the signal drivers, the multiphase clock data generator is also adapted to segment the image data, reconfiguring the segmented data pieces into a suitable input Data configuration to the signal drivers' and supply of such data pieces. 5. The display device of claim 3, wherein the multiphase clock data is generated Independent drive pulses offset from each other in phase are respectively supplied to the signal drivers, and the drive pulses respectively include a clock pulse and a start pulse. 6_ Display device of claim 4, wherein the multiphase clock data generator Providing the independent driving pulses that are offset in phase with each other to the signal drivers, and the driving pulses respectively include a clock pulse and a start pulse. 7. The display device of claim 4, wherein the driving pulses are in phase with each other One time interval Φ of the ground offset is set to satisfy the relationship Φ^(Τ/2)/Ν, where (T/2) is the half cycle of an image clock, and the number of frequency divisions is 128889.doc 200912876 8. The display device of claim 6, wherein the drive pulses are offset in phase with each other by a time interval φ set to satisfy a relationship Φ &lt; (Τ/2) / ν, where (τ/2) is an image The display device of any of the preceding claims, comprising: a selector switch disposed in each of the signal drivers Between the signal lines, the selector switch is adapted to select the image data in a time division manner. ^10, A method of driving a display device, comprising the steps of: arranging a pixel segment having a configuration to form a pixel circuit having a matrix of at least a plurality of turns, writing pixel data to each of the pixel circuits via a switching element; arranging at least one scan line associated with the columns of the pixel circuits, and Adapting to control the conduction of the switching elements; arranging a plurality of money lines associated with the rows of the pixel circuits and adapted to convey the pixel data; arranging a horizontal driving circuit having a plurality of signals a driver, the plurality of signal drivers being associated with a plurality of groups into which the signal lines are divided, and adapted to convey the image data supplied to the signal lines; respectively supplying the offsets in phase with each other And independently driving pulses to the signal drivers; and causing each of the signal drivers to communicate the image data to the associated letter Line, in response to receiving the driving pulse. 128893.doc 200912876 11. An electronic device 6 having a display device, the display device comprising: a pixel segment, and θ 士 / - ', /, configured to form at least a plurality of The image of the matrix of the matrix is % A_ , 〃 a pixel element is written to each of the pixel circuits by a switching element. The scan line 'is arranged to be associated with the columns of the pixel circuits, And adaptively controlling the conduction of the switching elements; a plurality of signal lines arranged to be associated with the rows of the pixel circuits and adapted to communicate the pixel data; and a horizontal drive circuit having a plurality of signal drivers, the plurality of drivers The plurality of groups divided by the signal lines are associated and adapted to convey the image data supplied to the signal lines, wherein each of the plurality of signal drivers conveys the image data to the associated image The line is responsive to a separate drive pulse, and the drive pulses supplied to the equal drive are offset in phase with each other. 128893.doc