TW200919738A - Flash memory - Google Patents

Abstract

A flash memory is provided. The flash memory includes a substrate, a first insulation layer formed on the substrate, a control gate installed on the first insulation layer, and two floating gates coplanar with the substrate individually installed on both sides of the control gate.

Description

200919738 IX. Description of the invention: [Technical field to which the invention belongs] Each of the Ming dynasty has a kind of 缉 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Set the flash memory of the gate. [Prior Art] In the conductor memory device, the non-volatile memory, the β-sexual silver-related body (erasable pr:; can, except for the programmable read-only memory) Words, flashing genre is right: "(10)017, EPR〇M). One / 匕 has a pole (a floating gate with a control storage 1 load, control (four) pole is used for:: heart two and: out is it can be for the entire record just change: she ^ just! 5 ^ 订 Order erase, and erase speed is fast, about ν. Therefore, in recent years, flash memory has been widely used in private - for example: digital camera, digital camera, mobile turtle, laptop or walkman Etc., to form a high-density semiconductor on the integrated circuit chip = such as = the memory of each memory cell (mem〇ryceii): the power consumption, so that its operating speed is accelerated. Force φ, φ r P, Shi 1 The search and death of the thousands of crystal design τ for & the smaller-sized memory unit, must be as short as possible to reduce the horizontal area of the memory unit = flash memory process in the process Miniaturization to large: When the following, the floating floating dielectric layer will be difficult to continue down. For example, the component is limited by the above size 'cannot be developed to a smaller size.= 200919738

When the 7L line width is reduced, it is also prone to short channel effect or hot carrier effect and reliability. SUMMARY OF THE INVENTION The present invention provides an embodiment of a flash memory comprising: a substrate; a first insulating layer formed on the substrate; and a control gate disposed on the first insulating layer And two gates respectively coplanar with the substrate, which are respectively disposed on two sides of the control gate.之一 An embodiment of the invention provides a cone memory. In the Yi Kei unit, the spear is set to fast flash / /, and there are two separate sets in the control gate: the net gate of the side. Since the control gate can control the two poles at the same time, the input and output of the two sets of data can be performed at the same time, and the division of this t = does have substantial help. And due to the design of the original two caused by = = below = this 2!: The above purposes, features and advantages can be more obvious and easy, only special examples, and with the drawings, for detailed description such as [embodiment] 』ΐΐ第=说: One embodiment of the present invention, a type of flashing Fig. 2 is a plan view of a flash memory device. A partial cross-sectional view of the brother 1 along the Α-Α section line. In the embossed Θ], the reference numeral 100 denotes an active area, the reference numeral 110 denotes a gate = layer, and the reference numeral 120 on both sides of the closed _110 denotes two floating idle diagrams, and the flash memory 10 includes a substrate. 2, the first absolute 200919738 edge layer 14 two control gate 16, two floating gates ι8 and a second insulation d first. The bain layer 14 is formed on the substrate 12. The control gate 16 is disposed on the first insulating layer 14. The two floating gates 18 are coplanar with the substrate 12 and are disposed on both sides of the control gate 16. The second permanent control gate 16 is first formed between the 1 yl, -, and rim layers 14 and between the control gate 16 and the two floating gates 18. Substrate 12 can be a P-type or 11-type germanium substrate. Insulation layer " Oxide layer. The control gate 16 can be formed by a polysilicon. Floating

The pole 18 can be composed of a 5 dielectric constant material. The high dielectric constant material can be 3 nitrided (tetra) oxides, wherein the I compound can be silicon nitride (silicon mn e ' and the oxide can be a metal oxide, such as oxidation (hafnium H^ 结 ( Xide) or oxidizes aluminium oxide. The second insulating layer 2 can be an oxide layer. The memory 10 further includes a source 22 and a pole 24 formed in the &quot;&quot; The two sides of the gate 16. The substrate 12 further includes a channel 26 formed between the source 22 and the drain 24. The external channel 26 and the source/drain (22/24) are further included. • Pn junction 28. The pn junction 28 can be a gradual junction (conducting junction), and its concentration variation range is reduced to lxl〇n within 2Q microns. 』”攸1x10 body junction-floating interpole Flash memory: Flash memory. In its memory unit, it has two split = floating gates on both sides. Since the control gate can control two i-rates at the same time: Lifting II simultaneously performs two sets of f-materials The input and output of the device have a continuous help to the component efficiency. And due to the design principle, the number of poles in the floating period is increased by 200919738, instead of the gate. The shrinkage of the inch, therefore, can avoid the shortcomings such as short channel effect or hot carrier effect caused by the size reduction. When the electrons are collected by the floating gate, they will be parked in the floating gate, so that the threshold voltage rises. If you want to remove the electrons in the floating gate, like other erasable programmable read-only memory (EPROM), the flash memory is also in the floating gate and source. Between the poles or the substrate, a high electric field is applied to cause electrons on the floating gate to pass through the oxide layer to the source or the substrate. Referring to Figures 3A to 3C, an embodiment of the present invention is illustrated, a flash First, as shown in FIG. 3A, after a substrate 12 is provided, an oxide layer (first insulating layer) 14 and an aluminum oxide layer 30 are sequentially formed on the substrate 12. Next, in the aluminum oxide layer. A patterned nitride layer 32 is formed on 30. Thereafter, the patterned nitride layer 32 is used as a mask to etch the I layer 30 to expose the oxide layer 14 to define a trench 34, as shown in FIG. 3B. As shown, after the patterned nitride layer 3 2 is removed, it is formed satisfactorily An oxide layer (second insulating layer) 20 is on the surface (not shown) of the aluminum oxide layer 30 and the sidewalls and the bottom of the trench 34. Thereafter, a polycrystalline layer 36 is overlaid on the oxide layer 20 (not shown). And filling the trench 34. The oxide layer 20 and the germanium layer 36 on the aluminum oxide layer 30 are removed by a planarization step such as chemical mechanical polish (CMP) to A control gate 16 is formed in 34. Thereafter, another patterned nitride layer 38 is formed on the germanium layer 36, and spacers 40 are formed on both sides of the patterned nitride layer 38. Next, the patterned nitride layer 38 and the spacers 40 are used as masks to etch the oxide layer 30 to define two floating gates 18, as shown in FIG. 3C. Thus, one of the present inventions is completed. For example, a semiconductor floating process with a double floating gate flash 200919738 memory 10 can be used as a suitable flash memory structure. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTI ID=0.0>> </ RTI> </ RTI> Quasi-safe heart circumference 200919738 [Simple description of the drawings] Figure 1 is an embodiment of the invention, illustrating the planar configuration of a flash memory device. Fig. 2 is a cross-sectional view showing the structure of a flash memory as a cross-sectional view taken along line A-A of Fig. 1 according to an embodiment of the present invention. 3A to 3C are diagrams showing an embodiment of the present invention, illustrating a method of manufacturing a flash memory. [Main component symbol description] 10~ flash memory; 12~ substrate; 14~ first insulating layer (oxide layer); 16~ control gate; 18, 120~ floating gate; 20~ second insulating layer ( Oxide layer); 2 2 ~ source; 24 ~ drain; 26 ~ channel; 28 ~ 卩-11 junction; 30 ~ alumina layer; 32, 38 ~ patterned nitride layer 34 ~ trench; 36 ~ complex Wafer layer; 40~ spacer; 100~ active area, 110~ gate layer. 10

Claims (1)

200919738 X. Patent application scope: A flash memory, comprising: a substrate; a first insulating layer formed on the substrate; = a control gate disposed on the first insulating layer; And "the knife and the substrate are coplanar floating 1 control the sides of the gate., the knife is" and the κ is the bottom of the bottom #^申, the patent supplements the flash memory described in item 1, wherein The I substrate is a p-type germanium substrate. The flash memory according to the item 1 of the substrate, wherein the 4. as claimed in the patent scope 筮Ί and the flash memory described in the 1st or 3rd item of the smashing, 2, 3, The rim layer is an oxide layer. 5. For example, the flash memory of the first part of the patent scope is the one of the 门 , 丄 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 6. The gates controlled by item 4 of the scope of application for patents consist of polycrystalline pins. _德脰' where the 7 is as claimed in the fourth item of the patent scope _ + 8. As stated in the fourth paragraph of the patent scope of the application, the 快 等 等 丄 贝 贝 贝 贝 贝 贝 所 所 所 所 所 所 ' ' ' ' The gate is composed of a nitride or an oxide. 9. The floating gate system, such as the scope of application for patent application, includes tantalum nitride. And flash memory, wherein the flash memory of the eight items, wherein the dirty gate system comprises a metal oxide. /, T 11 · Flash memory as described in the patent application scope, wherein the floating idle poles include yttrium oxide (ZirC=m〇^ or oxidation_“num()xidZe), Oxidized erroneous body, more package = C« flash memory layer and these floats: =, formed in the control between the pole and the first absolute 13. If you want to specialize in the scope of the first -th - (four) thought / The flash memory described in the item further includes a brother-, and a rim layer formed between the control gates and the floating gates. /, the brother's seven-edge layer and the 14's Please refer to the patent for the 7th, second, second insulation sound, the slogan, &amp;&lt;&lt;&gt;&apos;&apos;&apos; The flash memory described in item U of the benefit range, further comprising a layer of the first layer of the brother, formed in the control; between the floating gates. The insulating layer and the flash memory described in item 12 of the present scope Body, in which the sorrow of the sorrow 纟 缘 缘 缘 为 一 一 。 & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & Located separately The control flash 18·, = the flash memory described in claim 17 of the patent application, further includes an overnight connection formed between the source and the drain. 19. As described in claim 17 Flash memory, more space. The surface (P_njuncti〇n), formed in the channel and the source and the pole of the 〇2〇^° Shenqing patent range, according to the flash memory, in which μ The ρ-η junction is a gradual junction (graded juncti).