CN107316808A - A kind of semiconductor devices and preparation method thereof, electronic installation - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic installation Download PDFInfo
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- CN107316808A CN107316808A CN201610261460.9A CN201610261460A CN107316808A CN 107316808 A CN107316808 A CN 107316808A CN 201610261460 A CN201610261460 A CN 201610261460A CN 107316808 A CN107316808 A CN 107316808A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 238000009434 installation Methods 0.000 title claims abstract description 11
- 238000007667 floating Methods 0.000 claims abstract description 107
- 239000011248 coating agent Substances 0.000 claims abstract description 50
- 238000000576 coating method Methods 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 238000007254 oxidation reaction Methods 0.000 claims description 17
- 230000003647 oxidation Effects 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 238000011049 filling Methods 0.000 abstract description 10
- 238000005429 filling process Methods 0.000 abstract description 8
- 239000000463 material Substances 0.000 description 22
- 238000005530 etching Methods 0.000 description 11
- 239000012212 insulator Substances 0.000 description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 238000000926 separation method Methods 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof, electronic installation.Methods described includes：Semiconductor substrate is provided, some FGS floating gate structuries are formed with the semiconductor substrate, the fleet plough groove isolation structure extended downward into the Semiconductor substrate is formed between the adjacent FGS floating gate structure；Etch-back removes the partial oxide in the fleet plough groove isolation structure, to form groove, exposes the FGS floating gate structure；The FGS floating gate structure exposed is aoxidized, to form oxide skin(coating) on the surface of the FGS floating gate structure；The oxide skin(coating) is removed, to increase the width of the groove between the FGS floating gate structure.Methods described is advantageously in the filling of control gate, and can avoid producing hole in filling process, broader active area critical size can also be kept simultaneously, to obtain bigger cell current, so that the performance and yield of semiconductor devices are further enhanced.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor devices and its preparation
Method, electronic installation.
Background technology
With the increasingly increase of the semiconductor storage demand for high power capacity, these semiconductor storages dress
The integration density put by people more concerns, in order to increase the integration density of semiconductor storage,
Many different methods are employed in the prior art, for example, tied by reducing memory cell size and/or changing
Structure unit and more memory cell are formed on single wafer, for by change cellular construction increase collection
Into for the method for density, have attempted to the horizontal layout by changing active area or change cell layout
Carry out reduction unit area.
Nand flash memory is a kind of storage scheme more more preferable than hard disk drive, because nand flash memory is with page
Data are read and write for unit, so being suitable for storing continuous data, such as picture, audio or alternative document number
According to；Simultaneously because the advantage that its cost is low, capacity is big and writing speed is fast, the erasing time is short is in mobile communication
The field of storage of device and portable multimedia device is widely used.At present, in order to improve
The capacity of nand flash memory in preparation process, it is necessary to improve the integration density of nand flash memory.
With the diminution of device size, the size of nand flash memory also constantly reduces, and nand flash memory is existed
Many problems are produced in preparation process, such as the filling of control gate between floating boom, because device size subtracts
It is small to cause that hole is formed in the filling process of control gate, the increase of electrical loss is caused, so that most
Making the performance of device eventually reduces.
Therefore, how to overcome in control gate filling process in the preparation process of nand flash memory and form hole
The problem of turn at present the problem of need urgent need to resolve.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be in embodiment
It is further described in part.The Summary of the present invention is not meant to attempt to limit institute
The key feature and essential features of claimed technical scheme, do not mean that more and attempt to determine to want
Seek the protection domain of the technical scheme of protection.
The invention provides a kind of preparation method of semiconductor devices, methods described includes：
Semiconductor substrate is provided, some FGS floating gate structuries are formed with the semiconductor substrate, adjacent
The fleet plough groove isolation structure extended downward into the Semiconductor substrate is formed between the FGS floating gate structure；
Etch-back removes the partial oxide in the fleet plough groove isolation structure, to form groove, exposes institute
State FGS floating gate structure；
The FGS floating gate structure exposed is aoxidized, to form oxide skin(coating) on the surface of the FGS floating gate structure；
The oxide skin(coating) is removed, to increase the width of the groove between the FGS floating gate structure.
Alternatively, methods described is still further comprised：
Layer deposited isolating in the groove and on the surface of the FGS floating gate structure；
Coating is deposited, to fill the groove and cover the FGS floating gate structure；
Control gate is formed on the coating.
Alternatively, the oxidation includes O2Rapid thermal oxidation, decoupled plasma oxidation or the generation of annealing
Oxygen plasma microwave.
Alternatively, the thickness of the oxide skin(coating) is 10~60 angstroms.
Alternatively, the step of removing the oxide skin(coating) includes prerinse step.
Alternatively, still further comprise and covered described in etch-back before forming the control gate on the cover layer
The step of layer.
Alternatively, it is also formed with tunnel oxide between the Semiconductor substrate and the floating boom.
Alternatively, the FGS floating gate structure includes polysilicon.
Present invention also offers a kind of semiconductor devices, the semiconductor devices is prepared by above-mentioned method
Obtain.
Present invention also offers a kind of electronic installation, the electronic installation includes above-mentioned semiconductor devices.
There is provided a kind of preparation of semiconductor devices in order to solve problems of the prior art by the present invention
Method, methods described is after core space memory cell opens (COPEN) step to the FGS floating gate structure
Side wall aoxidized, oxide skin(coating) and removed with being formed on the surface of FGS floating gate structure, remove the oxidation
After nitride layer the slot opening between the FGS floating gate structure can be made further to expand, thus advantageously in
The filling of control gate, and can avoid producing hole in filling process, while can also keep broader
Active area critical size, to obtain bigger cell current, so that the performance and yield of semiconductor devices
It is further enhanced.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Show in accompanying drawing
Embodiments of the invention and its description are gone out, for explaining the device and principle of the present invention.In the accompanying drawings,
Fig. 1 is the preparation technology flow chart of heretofore described semiconductor devices；
Fig. 2 a-2f are the preparation process schematic diagram of heretofore described semiconductor devices；
Fig. 3 is the external view of the example of mobile phone handsets in the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more thoroughly
Understand.It is, however, obvious to a person skilled in the art that the present invention can be without one
Or these multiple details and be carried out.In other examples, in order to avoid obscuring with the present invention,
It is not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to this
In the embodiment that proposes.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will be originally
The scope of invention fully passes to those skilled in the art.In the accompanying drawings, for clarity, Ceng He areas
Size and relative size may be exaggerated.Same reference numerals represent identical element from beginning to end.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to " or " coupling
Close " other elements or layer when, its can directly on other elements or layer, it is adjacent thereto, connection
Or other elements or layer are coupled to, or there may be element or layer between two parties.On the contrary, when element is claimed
For " on directly existing ... ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other members
When part or layer, then in the absence of element or layer between two parties.Although it should be understood that term first, the can be used
2nd, the third various elements of description, part, area, floor and/or part, these elements, part, area,
Layer and/or part should not be limited by these terms.These terms be used merely to distinguish element, part,
Area, floor or part and another element, part, area, floor or part.Therefore, the present invention is not being departed from
Under teaching, the first element discussed below, part, area, floor or part be represented by the second element,
Part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ",
" ... on ", " above " etc., it can for convenience describe and be used so as in description figure herein
A shown element or feature and other elements or the relation of feature.It should be understood that except shown in figure
Orientation beyond, spatial relationship term be intended to also including the use of the different orientation with the device in operation.Example
Such as, if device upset in accompanying drawing, then, it is described as " below other elements " or " its it
Under " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, example
Property term " ... below " and " ... under " may include it is upper and lower two orientation.Device can additionally take
Correspondingly explained to (being rotated by 90 ° or other orientations) and spatial description language as used herein.
The purpose of term as used herein is only that description specific embodiment and not as the limit of the present invention
System.Herein in use, " one " of singulative, " one " and " described/should " be also intended to include plural number
Form, unless context is expressly noted that other mode.It is also to be understood that term " composition " and/or " comprising ",
When in this specification in use, determining the feature, integer, step, operation, element and/or part
Presence, but be not excluded for one or more other features, integer, step, operation, element, part
And/or the presence or addition of group.Herein in use, term "and/or" includes any of related Listed Items
And all combinations.
In order to thoroughly understand the present invention, detailed step and detailed knot will be proposed in following description
Structure, to explain technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but
In addition to these detailed descriptions, the present invention can also have other embodiment.
There is provided a kind of preparation of semiconductor devices in order to solve problems of the prior art by the present invention
Method, methods described includes：
Semiconductor substrate is provided, some FGS floating gate structuries are formed with the semiconductor substrate, adjacent
The fleet plough groove isolation structure extended downward into the Semiconductor substrate is formed between the FGS floating gate structure；
Etch-back removes the partial oxide in the fleet plough groove isolation structure, to form groove, exposes institute
State FGS floating gate structure；
The FGS floating gate structure exposed is aoxidized, to form oxide skin(coating) on the surface of the FGS floating gate structure；
The oxide skin(coating) is removed, to increase the width of the groove between the FGS floating gate structure；
The layer deposited isolating in the groove, to cover the surface of the FGS floating gate structure；
Coating is deposited, to fill the groove and cover the FGS floating gate structure；
Control gate is formed on the coating.
Wherein, the oxidation includes selecting O2Rapid thermal oxidation, decoupled plasma oxidation and the life of annealing
Into oxygen plasma microwave.
Wherein, the thickness of the oxide skin(coating) is 10~60 angstroms.
There is provided a kind of preparation of semiconductor devices in order to solve problems of the prior art by the present invention
Method, methods described is aoxidized after COPEN steps to the side wall of the FGS floating gate structure, with
The surface of FGS floating gate structure side wall forms oxide skin(coating) and removed, and can make institute after the removal oxide skin(coating)
The slot opening stated between FGS floating gate structure further expands, so that advantageously in the filling of control gate, and
And can avoid producing hole in filling process, while broader active area critical size can also be kept,
To obtain bigger cell current, so that the performance and yield of semiconductor devices are further enhanced.
Embodiment one
There is provided a kind of preparation of semiconductor devices in order to solve problems of the prior art by the present invention
Method, is further described to methods described below in conjunction with the accompanying drawings.
Wherein, Fig. 2 a-2f are the preparation process schematic diagram of heretofore described semiconductor devices；Fig. 3 is this
The external view of the example of mobile phone handsets in invention.
Fig. 1 is the preparation technology flow chart of heretofore described semiconductor devices, specifically includes following steps：
Step S1：Semiconductor substrate is provided, some FGS floating gate structuries are formed with the semiconductor substrate,
Be formed between the adjacent FGS floating gate structure shallow trench that extends downward into the Semiconductor substrate every
From structure；
Step S2：Etch-back removes the partial oxide in the fleet plough groove isolation structure, to form groove,
Expose the FGS floating gate structure；
Step S3：The FGS floating gate structure exposed is aoxidized, is aoxidized with being formed on the surface of the FGS floating gate structure
Nitride layer；
Step S4：The oxide skin(coating) is removed, to increase the width of the groove between the FGS floating gate structure
Degree.
Below based on the process chart in accompanying drawing 1, methods described expansion is described in detail.
Step one is performed there is provided Semiconductor substrate, some floating boom knots are formed with the semiconductor substrate
Structure, is formed with the shallow ridges extended downward into the Semiconductor substrate between the adjacent FGS floating gate structure
Recess isolating structure.
Specifically, as shown in Figure 2 a, during the Semiconductor substrate 201 can be the following material being previously mentioned
At least one：Silicon, silicon-on-insulator (SOI), stacking silicon (SSOI) on insulator, on insulator
It is laminated SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI)
Deng.
Some FGS floating gate structuries are formed on the semiconductor substrate, are specifically comprised the following steps：
Floating gate layer, mask layer are formed on the semiconductor substrate, and is patterned, to form floating boom knot
Structure 204 and shallow trench.Specifically, floating gate layer is formed on the semiconductor substrate, and the floating gate layer can
To select polysilicon layer, to form FGS floating gate structure in subsequent steps.
Wherein described mask layer can select hard mask layer, such as SiN, to form the process of shallow trench
The middle protection floating gate layer is not damaged.
Then, dry etch process is performed, successively to hard mask layer, floating gate layer and Semiconductor substrate 201
Perform etching to form shallow trench.Specifically, the figuratum photoresist of tool can be formed on hard mask layer
Layer, carries out dry etching, to transfer a pattern to hard mask by mask of the photoresist layer to hard mask layer
Layer, and floating gate layer and Semiconductor substrate 201 are performed etching as mask using photoresist layer and hard mask layer,
To form groove, and formed in the floating gate layer by the mutually isolated FGS floating gate structure 204 of the groove.
Wherein, the number of the FGS floating gate structure is not limited to and a certain number range.
Then shallow trench isolated material is filled in groove, to form fleet plough groove isolation structure 202.Specifically
Ground, can form shallow trench isolated material, the shallow trench isolated material on hard mask layer and in groove
Can be silica, silicon oxynitride and/or other existing advanced low-k materials；Chemical machinery is performed to grind
Grinding process is simultaneously stopped on hard mask layer, to form fleet plough groove isolation structure.
Finally, hard mask layer is removed.The method for removing remaining hard mask layer can be wet etching process,
Because the etching agent for removing hard mask layer is thought it is known in the art, being therefore no longer described in detail.
The pattern with fleet plough groove isolation structure is just obtained after removing hard mask layer, alternatively, the step is also
Including carrying out trap and threshold voltage adjustment to the pattern.
Alternatively, tunnel oxide can also be formed between the Semiconductor substrate and the FGS floating gate structure
Layer 203.The preparation of the tunnel oxide includes carrying out N~+ implantation or doping first on substrate,
Nitride layer is formed, high-temperature oxydation then is carried out to the nitride layer, oxide skin(coating) is obtained, enters recently
Row nitrogen treatment, nitrogenizes the oxide the superiors, obtains SiON of the top and bottom rich in nitrogen and ties
Structure, methods described is more prone to control, more efficient, can better meet semiconductor devices toward smaller chi
The demand of very little development.
Step 2 is performed, etch-back removes the partial oxide in the fleet plough groove isolation structure 202, with
Groove is formed, exposes the side wall of the FGS floating gate structure 204.
Specifically, as shown in Figure 2 a, blanket type dry etching (Blank etch) is passed through in this step
The partial oxide in the fleet plough groove isolation structure 202 is removed, groove is formed, to expose the floating boom
The partial sidewall of structure 204, so that the FGS floating gate structure 204 in subsequent steps can be with control gate knot
Structure has bigger contact area, and the step is referred to as the step of memory cell is opened (cell open, COPEN)
The step of, i.e., by removing the shallow trench isolation oxide between the floating boom of part, with exposed portion institute
FGS floating gate structure is stated, so as to which stable contact can be formed with the FGS floating gate structure after deposit polycrystalline silicon layer,
Avoid causing the problem of contact is unstable because device size reduces.
Wherein, the COPEN techniques can select process commonly used in the art, no longer go to live in the household of one's in-laws on getting married herein
State.
In this step in order to prevent the side wall to the FGS floating gate structure cause damage, from the floating boom
Structure has the engraving method of larger etching selectivity, alternatively, in this step from including at least O2
Etching atmosphere, from including O2Etching atmosphere can not only improve the oxide and the floating boom knot
The etching selectivity of structure, and can make to expose the side wall with rounder and more smooth profile (rounding
Profile), to improve the coupling effect of the FGS floating gate structure and control gate structure.
Further, in embodiments of the present invention, the etching atmosphere is except including O2In addition, may be used also
Further to include C4F6, C4F8Or C5F8Or the similar etching gas rich in C, further to improve institute
The etching selectivity of FGS floating gate structure and oxide is stated, to reduce the damage to FGS floating gate structure side wall.Its
Described in FGS floating gate structure side wall it is rounder and more smooth, and without defect, half prepared relative to other method
Conductor device performance is greatly improved.
Alternatively, after the FGS floating gate structure 204 is exposed, it is wet that methods described still further comprises execution
The step of method is cleaned.DHF is selected in the wet clean step, not only can be with by the wet-cleaning
Reduce the hole of oxide in fleet plough groove isolation structure, and the coarse of the oxide surface can be reduced
Degree, to improve the performance and yield of device.
Step 3 is performed, the FGS floating gate structure exposed is aoxidized, is formed with the surface in the FGS floating gate structure
Oxide skin(coating) 205.
Specifically, as shown in Figure 2 b, the oxidation includes selecting O in this step2The fast speed heat of annealing
Oxidation, decoupled plasma oxidation and generation oxygen plasma microwave.
Wherein, O is selected in the embodiment of the present invention2Or contain O2Atmosphere to described
FGS floating gate structure is heat-treated, and the heat treatment temperature is at 800-1500 DEG C, preferably 1100-1200 DEG C,
Processing time is 2-30min, and it is 10~60 that a layer thickness is formed on the FGS floating gate structure by the processing
Angstrom oxide skin(coating) 205.
In the embodiment of the present invention, the FGS floating gate structure selects polysilicon, therefore described
The surface of FGS floating gate structure forms silicon oxide layer.
Step 4 is performed, the oxide skin(coating) is removed, to increase the groove between the FGS floating gate structure
Width.
Specifically, as shown in Figure 2 c, the oxide skin(coating) is removed by prewashed method in this step
205, to increase the opening of the groove.
Alternatively, in this step with the hydrofluoric acid DHF of dilution (wherein comprising HF, H2O2And H2O)
Prerinse is carried out to the surface of the bottom wafers 301, to remove the oxide skin(coating) 205.
Wherein, the concentration of the DHF is not limited strictly, in the present invention preferably
HF:H2O2:H2O=0.1-1.5:1:5.
As alternate embodiment, in this step it is also an option that and the FGS floating gate structure 204 have compared with
The method of big etching selectivity, for example, remove the oxide skin(coating) 205 from SiCoNi processing procedures, described
SiCoNi processing procedures have specific in high selectivity, the SiCoNi processing procedures to the oxide skin(coating) 205
Parameter, those skilled in the art can need to be selected according to technique, it is not limited to a certain numerical value.
The method of the invention is aoxidized after COPEN steps to the side wall of the FGS floating gate structure,
Oxide skin(coating) and removed with being formed on the surface of FGS floating gate structure side wall, removing after the oxide skin(coating) can be with
The slot opening between the FGS floating gate structure is set further to expand, so that advantageously in the filling of control gate,
And can avoid producing hole in filling process, while broader active area critical size can also be kept,
To obtain bigger cell current, so that the performance and yield of semiconductor devices are further enhanced.
Perform step 5, the layer deposited isolating 206 in the groove, to cover the table of the FGS floating gate structure
Face.
Specifically, as shown in Figure 2 d, the separation layer 206 can select commonly used in the art in this step
Insulating materials, such as ONO (the structural insulation separation layer of oxidenitride oxide), but simultaneously
It is not limited to the material.
Wherein, the thickness of the separation layer 206 is not limited to a certain number range.
Step 6 is performed, coating 207 is deposited, to fill the groove and cover the FGS floating gate structure,
Finally control gate is formed on the coating.
Specifically, as shown in Figure 2 e, coating 207 is deposited in this step, due to the FGS floating gate structure
Between groove there is larger opening, therefore can be avoided the formation of during the coating is filled
The problem of hole, solve well as device size reduces the problem of being difficult to filling.
Alternatively, the coating 207 selects semiconductor material layer, such as polysilicon, but does not limit to
In the material.
Coating described in etch-back is still further comprised before forming the control gate 208 on the cover layer
Step.
Then control gate material layer is formed above the coating, as shown in figure 2f, wherein the control
Gate material layer can be selected and floating gate material layer identical material, can also select different materials,
Control gate 208 for example can be used as forming metal gates.
So far, the introduction of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed.Upper
State after step, other correlation steps can also be included, here is omitted.Also, except above-mentioned step
Outside rapid, the preparation method of the present embodiment can also be among each above-mentioned step or between different step
Including other steps, these steps can be realized by various techniques of the prior art, herein not
Repeat again.
Embodiment two
The present invention is described in order to solve problems of the prior art there is provided a kind of semiconductor devices
Semiconductor devices is prepared from the method described in embodiment one.
The plate for semiconductor equipment device includes：
The Semiconductor substrate 201；
Shallow trench is isolated, in the Semiconductor substrate,
FGS floating gate structure, in the Semiconductor substrate, between the shallow trench isolation；
Separation layer, above the floating boom；
Control gate 208, on the separation layer.
Wherein, the Semiconductor substrate 201 can be at least one of following material being previously mentioned：Silicon,
Silicon (SSOI) is laminated on silicon-on-insulator (SOI), insulator, SiGe is laminated on insulator
(S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Some FGS floating gate structuries are formed on the semiconductor substrate, are specifically comprised the following steps：
Alternatively, it is also formed with tunnel oxide between the Semiconductor substrate and the FGS floating gate structure
203.The preparation of the tunnel oxide includes carrying out N~+ implantation or doping, shape first on substrate
Into nitride layer, high-temperature oxydation then is carried out to the nitride layer, oxide skin(coating) is obtained, carried out recently
Nitrogen treatment, nitrogenizes the oxide the superiors, obtains the SiON structures that top and bottom are rich in nitrogen,
Methods described is more prone to control, more efficient, can better meet semiconductor devices and be sent out toward smaller szie
The demand of exhibition.
Wherein, in the preparation process of the FGS floating gate structure of the semiconductor devices, the FGS floating gate structure is carried out
Oxidation, oxide skin(coating) and is removed with being formed on the surface of FGS floating gate structure side wall, remove the oxide skin(coating) it
Afterwards the slot opening between the FGS floating gate structure can be made further to expand, so that advantageously in control gate
Filling, and can avoid producing hole in filling process, while broader active area can also be kept
Critical size, to obtain bigger cell current, so that the performance and yield of semiconductor devices are entered
One step is improved.
Separation layer 206 can select insulating materials commonly used in the art, such as ONO (oxide-nitrides
The structural insulation separation layer of thing-oxide), but be not limited to that the material.
Wherein, the thickness of the separation layer 206 is not limited to a certain number range.
Alternatively, the device still further comprises coating 207, on the FGS floating gate structure
Side.
Alternatively, the coating 207 selects semiconductor material layer, such as polysilicon, but does not limit to
In the material.
The step of coating described in etch-back is still further comprised before forming the control gate on the cover layer
Suddenly.
Then control gate material layer is formed above the coating, wherein the control gate material layer can be with
From with the floating gate material layer identical material, can also select different materials, for example can be in shape
Control gate is used as into metal gates.
Side of the semiconductor devices in preparation process after COPEN steps to the FGS floating gate structure
Wall is aoxidized, and to form oxide skin(coating) on the surface of FGS floating gate structure side wall and remove, removes the oxidation
After thing the slot opening between the FGS floating gate structure can be made further to expand, so that advantageously in control
The filling of grid processed, and can avoid producing hole in filling process, while can also keep broader has
Source region critical size, to obtain bigger cell current, so that the performance and yield of semiconductor devices are obtained
To further raising.
Embodiment three
It is described present invention also offers a kind of electronic installation, including the semiconductor devices described in embodiment two
Semiconductor devices is prepared according to the methods described of embodiment one.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, net book,
Game machine, television set, VCD, DVD, navigator, DPF, camera, video camera, recording
Any electronic product such as pen, MP3, MP4, PSP or equipment, or any centre including circuit
Product.The electronic installation of the embodiment of the present invention, the above-mentioned circuit due to having used, thus with more preferable
Performance.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300 be equipped with including
Display portion 302, operation button 303, external connection port 304, loudspeaker 305 in shell 301,
Microphone 306 etc..
Wherein described mobile phone handsets include the semiconductor devices described in embodiment two, the semiconductor device
The side wall of the FGS floating gate structure is aoxidized after part COPEN steps, with FGS floating gate structure side wall
Surface forms oxide skin(coating) and simultaneously removed, and removing can make after the oxide between the FGS floating gate structure
Slot opening further expands, so that advantageously in the filling of control gate, and can avoid filling
Hole is produced in journey, while broader active area critical size can also be kept, to obtain bigger unit
Electric current, so that the performance and yield of semiconductor devices are further enhanced.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment
The purpose illustrated and illustrated is only intended to, and is not intended to limit the invention to described scope of embodiments
It is interior.In addition it will be appreciated by persons skilled in the art that the invention is not limited in above-described embodiment, root
More kinds of variants and modifications can also be made according to the teachings of the present invention, these variants and modifications all fall within this
Invent within scope claimed.Protection scope of the present invention is by the appended claims and its waits
Effect scope is defined.
Claims (10)
1. a kind of preparation method of semiconductor devices, it is characterised in that methods described includes：
Semiconductor substrate is provided, some FGS floating gate structuries are formed with the semiconductor substrate, adjacent
The fleet plough groove isolation structure extended downward into the Semiconductor substrate is formed between the FGS floating gate structure；
Etch-back removes the partial oxide in the fleet plough groove isolation structure, to form groove, exposes institute
State FGS floating gate structure；
The FGS floating gate structure exposed is aoxidized, to form oxide skin(coating) on the surface of the FGS floating gate structure；
The oxide skin(coating) is removed, to increase the width of the groove between the FGS floating gate structure.
2. according to the method described in claim 1, it is characterised in that methods described is still further comprised：
Layer deposited isolating in the groove and on the surface of the FGS floating gate structure；
Coating is deposited, to fill the groove and cover the FGS floating gate structure；
Control gate is formed on the coating.
3. according to the method described in claim 1, it is characterised in that O is selected in the oxidation2Annealing
Rapid thermal oxidation, decoupled plasma oxidation or generation oxygen plasma microwave.
4. according to the method described in claim 1, it is characterised in that the thickness of the oxide skin(coating) is
10~60 angstroms.
5. according to the method described in claim 1, it is characterised in that the step of removing the oxide skin(coating)
Including prerinse step.
6. method according to claim 2, it is characterised in that form the control on the cover layer
The step of coating described in etch-back being still further comprised before grid.
7. according to the method described in claim 1, it is characterised in that in the Semiconductor substrate and described
Tunnel oxide is also formed between floating boom.
8. according to the method described in claim 1, it is characterised in that the FGS floating gate structure includes polysilicon.
9. a kind of semiconductor devices, it is characterised in that the semiconductor devices passes through claim 1 to 8
One of described in method prepare.
10. a kind of electronic installation, it is characterised in that the electronic installation is included described in claim 9
Semiconductor devices.
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