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TW200805620A - Method of packaging a plurality of integrated circuit devices and semiconductor package so formed - Google Patents

Method of packaging a plurality of integrated circuit devices and semiconductor package so formed Download PDF

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Publication number
TW200805620A
TW200805620A TW096122872A TW96122872A TW200805620A TW 200805620 A TW200805620 A TW 200805620A TW 096122872 A TW096122872 A TW 096122872A TW 96122872 A TW96122872 A TW 96122872A TW 200805620 A TW200805620 A TW 200805620A
Authority
TW
Taiwan
Prior art keywords
semiconductor
layer
conductive
semiconductor device
package
Prior art date
Application number
TW096122872A
Other languages
English (en)
Inventor
Ken M Lam
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of TW200805620A publication Critical patent/TW200805620A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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200805620 九、發明說明： 【發明所屬之技術領域】 士本發明^有Μ於-種三維可堆疊半導體封裝件，以及更 =別地’疋有關於—種設計成用以安裝積 :的三維可堆疊半導體封裳件，其㈣等積體電路= 基板材料之本體隔離。 - 【先前技術】 箄積體電路晶片變得更多功能及高度整合時，該 專曰曰片包括更多接合塾（或端子塾），以及因此，該等晶片 有：多外部端子(或引線)。當一沿著封裝之周圍 '有ii’統封装必納大量電性連接點時，該封裝 之涵蓋範圍（foot print)與加 4夕 …“ η ηΐ”曰加了。然而，許多電子系統之 係要农小化該等系統之總尺寸。因此，要容納 :不增加該封裝之涵蓋範圍，該封裝之接腳間距(或引 I距）必須減少及/或積體電路晶粒需要被堆疊在一單 =(-堆疊封裝）内n —小於約G 之接腳間距 =起許多技術問題。例如：一具有小於04丽之接腳間 ，的^之整修需要昂貴整修工具，以及該等引線在該封 衣之處理㈣傾向於彎曲。此外’由於—需求臨界對準 曰主ticaial ignment)步驟，此等封裝之表面安裝需要一 叩貴且複雜表面安裝製程。 ，而’該堆疊封裝可能增加在該封裝之相同涵蓋範圍内 又面孩、度。此等堆疊組態在該項技藝中係已知的。 在一標準積體電路（例如：在整塊矽上所形成之電路） 2/發明說明書(補件)/96·08/96122872 5 200805620 中，一 1C設計者將在該1C之上層設計上包含一個或多個 接合墊。該接合墊藉由打線接合該1C至一接地電位以電 性連接至該基板。為了此方案適當地作用，在該上必 須有一接地接合墊。 然而，許多先進半導體積體電路裝置係被建構在基板 上，其中在一與該基板之下部分（基底）電性隔離之上層上 衣k邊積體電路裝置。這些基板型態包括植氧分離（SIM0X) 及覆矽絕緣層（SOI)。在這些情況中，沒有從該絕緣基板 之最上部分上之積體電路至該基板之下部分的電性連 接。因此，在SOI技術中，該積體電路（與任何接合墊） 被製造於該SOI材料之上層中。該絕緣層避免針對一 裝置而設計一基板-接地接合墊至該Ic設計中。因此，以 一焊線將一接地接合墊接地將不會將該絕緣基底 性接地。 - % 田圖1係一習知技藝堆疊晶粒封裝件1〇〇之立視圖。該堆 豐晶粒封裝件100包括一晶粒黏接谭盤10卜數個封穿塾 103、一矽積體電路晶粒105及一 s〇I積體電路晶粒1〇\。 該石夕積體電路晶粒1G5藉由導電環氧樹脂1G9而黏附至該 晶ΐϊί焊盤101。接著該S01積體電路晶粒107藉由一Λ f導，環氧樹月旨111而黏附至該矽積體電路晶粒i二(注 ::? 了黏附該謝晶粒107而使用導電環氧樹 曰〃、不此兵在該SOI晶粒107之上層的製造電路 接觸。）在财晶粒⑽及該撕晶粒107上形成 接塾⑴。數錢i祥線113及數條梦焊線115將該2 312/發明說明書(補件)/96·08/96122872 200805620 晶粒107及矽晶粒1〇5分別電性連接至該數個封裝墊 10 3。在形成所有電性連接後，一封裝材料層12〗保護該 •等積體電路晶粒105及107及該數條焊線113及115。 ‘ 一在該晶粒107上之絕緣層123的存在使一 s〇i基 底125與在該上層所形成之電路電性隔離。此外，在該矽 晶粒105之一保護層（passivati〇n layer)(未顯示）上方 安裝該SOI晶粒1〇7,藉此進一步防止該s〇i基 因此，所需要的是-種將在包含一絕緣層之積體電接路也生 產材料中之基底電性接地的簡單且經濟手段。 【發明内容】 揭示一種多晶粒封裝裝置及技術，其特別是可用於包含 絕緣基板（例如：覆矽絕緣層（S0I))之積體電路晶粒，其中 在習知技藝下要將一基底層接地係相當不可實施的。揭示 有效地將一積體電路裝置之所有層接地的手段，而不 官是否該裝置與一晶粒黏接焊盤直接接觸。例如·可以一 鲁起使用導電膠與打線技術，以連接該S0I裴置之一不同絕 緣基底至一接地面。在另一情況中，如果在一堆疊中最上 裝置大於底下的安裝裝置’則可以使用—金屬板間特徵 (贴tal inter-plate feature)連接該s〇I基底至接地。 該等所述裝置及技術可王作於晶粒之任何尺寸或在相同 封裝中之各種尺寸的晶粒，而無關於堆疊組態。 在一示範性具體例中，本發明係一種在一半導體封裝件 中封裝數個半導體裝置之方法，包括：以一第一導電❹ 安裝一第-半導體裝置至該半導體封裝件之—晶粒黏^ 312/發明說明書(補件)脉〇8/96122872 200805620 知a及卩第一導電膠層安裝一第二半導體裝置至該第 半導體衣置之最上面。提供該第二導電膠層之一跡線以 -仗5亥第一與第二半導體裝置間電性耦接該第二導電膠層 之部分至一在該第一半導體裝置之最上面的接地墊。 在另一示範性具體例+，本發明係一種在一 件中封裝數個半導體裝置之方法，包括：以一第一導電ς 層=裝H導體I置至該半導體封裝件之—晶粒黏 • 盤及以一第二導電膠層安裝-導電内層間隔物至該 弟一半導體裝置之最上面。以一第三導電膠層安裝一第二 =導體裝置至該導電内層間隔物之最上面及提供該第二 ¥電膠層之-跡線以從該第—半導體褒置與該導電内層 間隔物間電性輕接該第二導電膠層之部分至—在該第二 半導體裝置之最上面的接地墊。 在本發明之另-示範性具體财，-半導體封裝件包括 ,、曰曰粒黏接焊盤；數個封裝墊，位於該晶粒黏接焊盤之至 少，側上且與該晶粒黏接焊盤電性隔離；以及一第一半導 體叙置’安裝於該晶粒黏接焊盤。—接地塾，位於該第一 半Τ體裝置之最上部分上且配置成電性耦接該第一半導 體衣置之部分至一接地電位。—由具有與—半導體部分電 性絕緣之基底部分的覆魏緣層（s G υ材料所製成之第二 體1置使該基底部分經由一導電膠層而與該第一半 =裝置之最上面電性通信。該導電踢層進—步電性 至在該第一半導體裝置上之接地議。 接 在本發明之另1難具體財，-半導體封裝件包括 312/發明說明書(補件)脉08/96122872 8 200805620 小黏接焊盤；數個封㈣’位於該晶粒黏接焊盤之至 =則上且與該晶粒黏接焊盤電性隔離；以及—第一半導 置安衣至3亥晶粒黏接焊盤。一接地墊，位於該第一
興壯衣置之最上0卩分上且配置成電性耦接該第一半導 -衣置之部分至—接地電位。—具有—第—及第二面之内 二間隔物以一導電膠層經由該第一面而電性耦接至該第 一半導體裝置之最上部分。該導電膠層電性柄接至在該第 +半Τ體裝置上之接地接合墊。一由具有與一半導體部分 電性絕緣之基底部分的覆梦絕緣層（SGI)材料所製成之第 二半導體裝置使該基底部分經由一導電膠層而與該内層 間隔物之第二面電性通信。 【實施方式】 本务明主要應用至在一絕緣基板材料（例如：覆矽絕緣 層（SOI))上所形成之堆疊積體電路。在一 s〇i晶粒中，一 在孩SOI基板之最上層上所製造之積體電路與該基板之 Φ最下部分（該基板基底材料）沒有任何電性接觸。因此，嗜 積體電路不能電性連接至該基底材料且無法輕易地完成 積體電路接地。只在該咖基板基底材料直接與該晶粒黏 β接焊盤接觸之情況下，可使該SOI基板基底材料本身輕易 地接地。然而，上面所製造之積體電路保持浮接。 在一堆疊晶粒封裝件中，一底部（基底）晶粒常常藉由例 如導電環氧樹脂黏附至該晶粒黏接焊盤。該晶 亦連接至接地。在該基底晶粒之上面所堆疊之任 晶粒最後將安裝至該基底晶粒之一保護層。該保護層本質 312/發明說明書(補件y96-08/96122872 9 200805620 上係絕緣的。因此，額外防止該上SOI晶粒被接地。 在此揭露方法及裝置以對未直接鄰近一封裝件之晶粒 黏接焊盤安裝之任何SOI晶粒提供一基板-接地連接。當 期望最理想半導體晶粒基板接地時，本發明亦應用至堆疊. 半導體（塊材材料）晶粒封裝件。雖然在下面的具體例中討 論SOI晶粒，其它具體例可以使用具有不同型態之絕緣基 板的其它晶粒型恶。 參考圖2，本發明之一堆疊晶粒封裝件200的一示範性 ®具體例包括一晶粒黏接焊盤201、數個封裝墊203、一矽 積體電路晶粒205及一 SOI積體電路晶粒207。在另一情 況中，該矽積體電路晶粒205可以是像下面圖3所論述之 一第二SOI積體電路晶粒。在此示範性具體例中，該矽積 體電路晶粒205之一面具有大於該SOI積體電路晶粒207 之幾何面積。 該SOI積體電路晶粒207係由三主層所構成.·一基底層 0 225、一絕緣層223及一積體電路製造層227。在一典型 SOI晶圓中，該基底層225係通常約670μιη厚之矽（雖然 此厚度係根據晶圓直徑而有所不同）。該絕緣層223常常 係一約500nm厚之二氧化矽層及該積體電路製造層227常 a 常係一約2μιη厚之矽層。在該積體電路製造層227中所製 • 造之電路藉由該絕緣層223與該基底層225電性隔離。在 該SOI積體電路晶粒207之積體電路製造層227中所製造 之數個焊接墊219藉由該絕緣層223與該基底層225絕 緣。在該矽積體電路晶粒205中亦製造另外數條焊線。 312/發明說明書(補件)/96-08/96122872 10 200805620 該矽積體電路晶粒205藉由導電環氧樹脂2〇9黏附至該 曰曰粒黏接知盤2(Π。接著該s〇I積體電路晶粒2〇7亦藉由 電％氧樹脂211黏附至該矽積體電路晶粒2〇5。該導 電壞㈣脂211可以例如填充有銀、鎳或金。在施加該導 電環氧樹脂211後，允許該環氧樹脂211硬化。在另-情 況中’該導電環氧樹脂可以是—導電帶或其它黏著劑形 式。 在該堆疊晶粒封裝件200組態中，該S0I積體電路晶粒 207常常被安裝在一保護層（未顯示）上，而該保護層係形 成於該矽積體電路晶粒205之最上部分上方。在一些應用 中，該SOI晶粒207之基底層225至接地電位的電性連接 可能是必要的。當分配該導電環氧樹脂211時，該分配圖 案係配置成加入導電環氧樹脂211之一跡線，該跡線電性 連接該SOI晶粒207之基底層225至一在該矽晶粒205上 之焊接接地墊217。該焊接接地墊217用以電性連接該矽 _積體電路晶粒205至接地電位。該數個焊接墊219係形成 於4石夕a曰粒2 0 5及該SO I晶粒2 〇 7兩者上。數條s〇 I焊線 213及數條矽焊線215分別電性連接該S0I晶粒2〇7之積 體電路製造層227及該矽晶粒205至該數個封裝墊203。 在形成所有電性連接後，一封裝材料221保護該等積體電 路晶粒205及207及該數條焊線213及215。 在圖3中’一包含相似尺寸（亦即，相似面積）之晶粒的 堆疊積體電路晶片載體封裝件300之一示範性具體例包 括一晶粒黏接焊盤201、數個封裝墊203、一第一 s〇l積 312/發明說明書(補件)/96-08/96122872 11 200805620 體電路晶粒301、一第二SOI積體電路晶粒303及一金屬 内層間隔物305。當該第一及第二SOI積體電路晶粒301 及303近乎相似尺寸時，圖3之組態係特別有用。在一替 代具體例中，可以使用一由一絕緣或半導體材料而不是金 屬所製造之核心製造該金屬内層間隔物305。然後，在安 裝前，以一導電材料塗佈該絕緣或半導體核心材料。 如同圖2之SOI積體電路晶粒207，該等SOI積體電路 晶粒301及303之每一晶粒係由三主層所構成·.一基底層 籲325A及325B、一絕緣層323A及323B以及一積體電路製 造層327A及327B。在一典型SOI晶圓中，該等基底層325A 及325B係通常約670μιη厚之矽（雖然此厚度係根據晶圓直 徑而有所不同），該等絕緣層323Α及323Β常常係一約 500nm厚之二氧化矽層，以及該等積體電路製造層327Α 及327B常常係一约2μπι厚之矽層。在該等積體電路製造 層327Α及327Β中所製造之電路藉由該等個別絕緣層323Α _及323Β與該等基底層325Α及325Β電性隔離。 在該等積體電路製造層327A及327B中製造數個焊接墊 219以及該數個焊接墊219亦藉由該等個別絕緣層323A 及323B與該等基底層325A及325B絕緣。 該第一 S 01積體電路晶粒3 01猎由導電環氧樹脂2 0 9黏 p 附至該晶粒黏接焊盤201。接著，根據一特別應用而定， 該金屬内層間隔物305以一導電環氧樹脂或一非導電環 氧樹脂211A黏附至該第一 SOI積體電路晶粒301。然而， 為了提供接地電位至該第二SOI積體電路晶粒303，使用 312/發明說明書(補件)/96-08/96122872 12 200805620 一導電環氧樹脂。接著，該 藉由一導電或非導f M + 貝體電路晶粒303亦 人开午屬％虱樹脂211b黏p 隔物305之最上面。該導 、w屬内層間 鈞斗、八 > “ 宁电衣乳树月曰可以例如埴充右招 鎳或金。在施加該環氧樹脂2〇9、2iu及咖、充有銀、 該環氧樹脂硬化。注音刭所古_ 後，允許
、911d 忍到所有二個環氧樹脂層209、211 A
及211B可以是相同材料。 211A 在該堆疊晶粒封褒件3〇〇組態中H 晶謂常:被安震在一保護層(未顯示)上，而； 係形成於5亥第—SGI積體電路晶粒3G1之最上部分上 在一些應用中，該第-S〇T曰私qnQ ^ ° 罘一 SOI日日粒303之基底層325B至 地電位的電性連接可能是必要的。告八 较 靶疋义要的田为配該導電環氧樹脂 211AH刀配圖案係配置成加入導電環氧樹脂21"之 一跡線，該跡線經由該金屬内層間隔物3〇5將該第二sm 晶粒303之基底層325B電性連接至一在該第一 s〇i晶粒 301上之焊接接地墊317。該焊接接地墊317用以電性連 接該第一 SOI積體電路晶粒301至接地電位。 在該第一及第二SOI晶粒301及303兩者上形成數個焊 接墊219。數條第二SOI焊線213及數條第一 S0I焊線215 分別電性連接該第二SO I晶粒30 3之積體電路製造層32 7B 及該第一 SOI晶粒301之積體電路製造層327A至該數個 封裝墊203。在形成所有電性連接後，一封裝材料22〗保 護該等積體電路晶粒301及303以及該數條焊線213及 215。 然 在前述說明中，已參考特定具體例來描述本發明 312/發明說明書(補件)/96-08/96122872 13 200805620 而’熟習技藝者明顯易知在不脫離所附請求項所述之本發 明的較廣精神及範圍内可實施各種修飾及變更。例如：熟 白技藝者將察覺到本發明之具體例可容易地應用至在各 種型態之封裝（例如：TAPP⑯（薄陣列塑膠封裝）、ulga@(超薄 f板柵格陣列）、BCC (凸點晶片載體）或其它相似封裝型 中所文衣的堆璺積體電路晶粒。並且，可以容易地使 用描述技術藉由例如相對於一下方晶粒以倒過來方 式女衣個或多個晶粒來安裝兩個以上之晶粒。除了 SIM0X、及SOI之外，各種其它型態之積體電路基板可從在 此所述之技術獲得益處。其它基板形態包括例如聚對苯二 甲酸乙二S旨（PET)基板、光罩或各種接合晶圓型態。此外， 匕3像石夕（或其匕第IV族材料）之塊材材料及化合物半導 =(例如·· 70素之化合物，特別是來自週期表第V及 二1族之元素）之基板可容易地被安I且可從上述技術 而非限定用。X將t兄明及該相式視為描述用 【圖式簡單說明】 立^圖1#習知技藝之—堆疊韻電路晶片_封裝件之 載L2^依據本發明之一具體例的一堆疊積體電路晶片 戟體封叙件之立視圖。 ^ 3係依據本發明之另一具體例的—包含相似尺寸之 曰曰拉的堆疊積體電路晶片载體封裝件之立視圖。 【主要元件符號說明】 U 2/發明說明書(補件)/96-08/96122 872 200805620 100 習知技藝堆疊晶粒封裝件 101 晶粒黏接焊盤 103 封裝墊 105 矽積體電路晶粒 ^ 107 SOI積體電路晶粒 109 導電環氧樹脂 110 晶粒黏接焊盤 111 非導電環氧樹脂 ® 113 焊線 115 焊線 119 焊接墊 121 封裝材料層 123 絕緣層 125 SOI基底 200 堆疊晶粒封裝件 201 晶粒黏接焊盤 203 封裝墊 205 矽積體電路晶粒 207 SOI積體電路晶粒 ^ 209 導電環氧樹脂 —211 導電環氧樹脂 211A 導電或非導電環氧樹脂 211B 導電或非導電環氧樹脂 213 焊線 312/發明說明書(補件)/96-08/96122872 15 200805620 215 焊線 217 焊接接地墊 219 焊接墊 ^ 221 封裝材料 1 223 絕緣層 225 基底層 227 積體電路製造層 300 堆疊積體電路晶片載體封裝件 • 301 第一 SOI積體電路晶粒 303 第二SOI積體電路晶粒 305 金屬内層間隔物 317 焊接接地墊 323A 絕緣層 323B 絕緣層 325A 基底層 0 325B 基底層 327A 積體電路製造層 327B 積體電路製造層 312/發明說明書(補件)/96-08/96122872 16

Claims (1)

  1. 200805620 十、申請專利範園： 1. 一種在一半導體封裝件中封裴數個積體電路裝置之 方法’該方法包括： 以一第—導電膠層安裝-第-半導體I置至該半導體 封裝件之一晶粒黏接焊盤； 以-第=導電膠層$裝一第二何體I置至該 導體裝置之最上面；以及 一提供該第二導電膠層之一跡線以電性耦接在該第一與 第=半導體裝置間之第二導電膠層的部分至一在該第一 半導體裝置之最上面的接地墊。 2·如申請專利範圍第1項之方法，進一步包括： 以=線將在該第一及第二半導體裝置上之數個接合墊 中的每個接合墊接合至該半導體封裴件之數個墊中的 一個；以及 以一封裝材料封裝該第一及第二半導體裝置及該等焊 3 ·如申明專利範圍第1項之方法，其中該第一導電膠層 及該第二導電膠層係選擇由相同材料構成。 4.如申請專利範圍第丨項之方法，進一步包括由一覆矽 絕緣層（3114〇11-011-111別1&1：〇]^材料製造該第二半導體 裝置。 5·如申請專利範圍第5項之方法，其中該第一半導體裝 置係選擇成具有一面積大於該第二半導體裝置之一面的 面。 312/發明說明書(補件)/96-08/96122872 17 200805620 6. -種在-半導體封裝件中封裝數個積體電路裝置之 方法，該方法包括： ^杜弟—導電膠層安裝—第—半導體裝置至該半導體 封衣件之一晶粒黏接焊盤，· ::第二導電膠層安裝一導電内層間隔物 導體裝置之最上面； 步干 以一第三導電膠層安裝一 層間隔物之最上面；以及弟一 +導體裝置至該導電内 導二導電膠層之-跡線以電性雜接在該第-半 m轉電内層間隔物間之第二導電膠層的部分 至-在该弟一半導體裝置之最上面的接地墊。 7·如申請專利範圍第6項之方法， 中^線將在該第H半導體裝置上之數個接合塾 一中:二一及個接合塾接合至該半導趙封裝件之數個塾中的 以一封裝材料封裝該第一及第二半導體 層間隔物及該等焊線。 、忒¥電内 8. 如申請專利範圍第6項之方 層、該第二導電#芦及兮楚一”中該弟一導電膠 構成。 勝層及該弟二導電膠層係選擇由相同材料 9. 如申請專利範圍第6項之方法， 牛 絕緣層材料製造該第二半導體裝置。少匕一覆矽 10·如申請專韻圍第6項之方H步包 矽絕緣層材料製造該第一半導體骏置。 覆 3 12/發明說明書(補件y96^96i22872 18 200805620 Π•如申請專利範圍第6 製造該導電内層間隔物。項之方法，進一步包括由金屬 12·如申請專利範圍第6 由一絕緣杜粗制 、之方法，進一步包括·· 及 4衣造該導電内層間隔物之一核心内部；以 形成一導電層於該 _ 方 。 、 ㈢間隔物之絕緣核心内部上 13·如申請專利範圍第6 由一本逡縣从μ 貝之方法，進一步包括： 以及、體材w造該導電内層間隔物之—核心内部； 上=成—導電層於該導電内層間隔物之半導體核心内部 14· 一種半導體封裝件，包括： 一晶粒黏接焊盤； 數個封裝藝’位於該晶粒黏接焊盤之至少兩侧上且與該 日日粒黏接焊盤電性隔離; 、 第一半導體裝置，與該晶粒黏接焊墊電性通俨· 、一接地墊，位於該第一半導體裝置之最上部分上°且配置 成電性轉接該第-半導體裝置之部分至一接地電位以及 一第二半導體裝置，具有至少一部分經由—導電膠層而 與該第-半導體裝置之最上面電性通信，該導電膠層進一 步電性麵接至在該第一半導體裝置上之接地接合塾曰。 15.如申請專利範圍第14項之半導體封襞件，進一卉包 括： ^ 〇 3U/發明說明書(補件)/96-08/96122872 19 200805620 條焊線電性耦接該接 耦接至一接地電位的 數條焊線，該數條焊線中之至少一 地墊至該數個封裝墊中之要配置成 一封裝墊；以及 一封裝材料，覆蓋該第一 線。 及第二半導體裝置及該數條焊 16·、如申請專利範圍第14項之半導體封裝件，其中該第 半$體1置之一面及該第二半導體裝置之一且 同的幾何面積。 /、 不
    17.如申請專利範圍第14項之半導體封裝件， 二半導體裝置係由一具有一盥一丰邕舻 ^ /、另并牛V體部分電性絕緣之 土 &部分的覆矽絕緣層(s〇I)材料所製成，該基底部分細 由該導電㈣而與該第—半導體裝置之最上面電性通作二 18· —種半導體封裝件，包括： σ 一晶粒黏接焊盤； 數個封裝塾，位於該晶粒黏接谭盤之至少兩側上且與該 _晶粒黏接焊盤電性隔離； Λ 第半導體衣置，以與該晶粒黏接焊盤電性通信方式 來安裝； -接地墊’位於該第一半導體裝置之最上部分上且配置 成電㈣接該第-半導體裝置之部分至—接地電位； 間隔物’具有一第一面及一第二面，該内層間隔 弟一面經由—第—導電膠層而電性純至該第-半 導體f置之最上部分，該第一導電膠層進-步電性耦接至 在該第-半導體裝置上之接地接合墊;以及 312/發明說明書(補件)/96-08/96122872 20 200805620 - ^二半導體裝置，具有至少—部分經由—第二導電膠 运而/、该内層間隔物之第二面電性通信。 步包 括： 19·如申請專利範圍第18項之半導體封裝件，進一 ^條焊線’該數條焊線中之至少—條焊線電性耦接該接 至该數個封裝墊中之要配置絲接至-接地電位的 一封裝墊；以及 線y封裝材料，覆蓋該第—及第二半導體I置及該數條焊 2 0 ·如申請專利範 一半導體裝置之一 似的幾何面積。 圍第18項之半導體封裝件，其中該第 面及該第二半導體裝置之一面具有相 21.如申請專利範圍第18項之半導體封裝件，其中該内 層間隔物係由一金屬材料所製成。 22·如申請專利範圍 馨層間隔物係由一被一 製成。 第18項之半導體封裝件，其中該内 金屬材料所包圍之絕緣核心材料所 如中請專利範圍第18項之半導體封裝件，其中該内 二：：物係由一被一金屬材料所包圍之半導體核心材料 所製成。 24.如申請專利範圍第18項之半導體封裝件，其中該第 =導體裝置係由-具有—與—半導體部分電性絕緣之 =1卩分的㈣絕緣㈣GI)材料所製成，該基底部分經 “弟-導電膠層而與該内層間隔物之第二面電性通信。 312/發明說明書(補件)抓〇8/96122872 21
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