SU957108A1 - Digital converter of speed - Google Patents

Description

one

The invention relates to a measurement technique and can be used to measure the speed of sea currents.

A flow meter is known that includes an impeller placed in the flow and an impeller rotation speed meter l.

The disadvantages of this meter are low noise immunity and measurement accuracy.

The closest to the invention to the technical essence is a digital converter of the angle of rotation of the shaft, containing a disk with evenly spaced circumferential marks, two reading elements mutually displaced in the direction of rotation, and a reversible counter, the counting input of which is connected to the output of the first reading element 23.

A disadvantage of the known transducer is the complexity of the design, due to the relatively complex circuit that determines the direction of rotation,

The aim of the invention is to simplify the device.

The goal is achieved by the fact that the digital speed converter is equipped with a shortening circuit. counting pulses, an NAND logic element and an O-trigger with a grounded D input, the first device connected to the pulse shortening circuit, which through the first input of the NAND element is connected to the S input of the D flip-flop and co. , 5 is the counting input of the D-flip-flop, and the output of the second device is connected to the second input of the NAND element, and the outputs of the D-flip-flop are connected to the control inputs of the reversing

20 counters.

FIG. 1 shows a flow rate digital converter circuit; in fig. 2 - time diagrams.

The speed converter consists of an impeller 1, on the ring rim of which are placed through equal intervals between the marks 2 (for example, small magnets). In the immediate vicinity of the rim, two reading elements (removal devices) are installed at close distances, consisting of readers of labels 3 and j (for example, magnetic cores) and formers 5 and 6. The output of the former 6 is connected to the inputs of the pulse shortening circuit 7, as well as with a 0-trigger counting input. 9 with a grounded O-input. The S-input of the D-trigger E is connected to the output of the NAND element. to the first input of which the output of the forcing device is connected .5 s to the second input - the output of the circuit 7 for shortening the pulse pulse. The output of the imaging unit 8 is connected to the counting input of the reversible counter 11, the control inputs are connected to the output O-trig of which the SSC converter works as follows. When the impeller rotates in one of the directions, for example, counterclockwise, pulse shifts are formed at the outputs of shapers 5 and 6, shifted relative to each other, and from the shaper 6 output, the front front pulse is formed before the forward edge of the pulse from the shaper 5 by a time interval , significantly longer pulse duration from the output and pulse shortening circuit 7 (Fig. 2). Therefore, the output element AND-NOT 10 output signals are missing. . At the same time, the O-flip-flop E remains in the state of logical zero, since with its arrival at its counting input the implants and the output of the flip-flop repeat the state of the grounded D-input, which corresponds, for example, to the summation state. The input of the reversible counter 11 is also fixed in the summation state. When changing the direction of rotation of the Impeller to the opposite (clockwise), the leading edge of the pulses from the output of the imager 5 will be ahead of the leading edge of the pulses from the output of the imager 6. Therefore, the pulse from the output of the pulse shortening circuit 7

coincide with the pulse of the sequence b (Fig. 2), with the result that at the output of the element AND-NOT 10 pulses will be formed. The duration and position of which are the same as in sequence c.

Claims (2)

Each of these pulses, entering the input of D-flip-flop 9, will turn it into the Subtraction position with its leading edge, while the trailing edge of each pulse of the sequence will return the D-flip-flop to its initial summation state. The counting pulses from the output of the imaging unit 8 arrive at the input of the reversible counter, and the change in the states of the reversible counter 11 occurs on the falling front of the sequence d (Fig. 2). As follows from the timing diagram, in the first part of it (before the breaks), the counter produces the summation of the sequence of the second — subtraction. Thus, in the proposed scheme, the sign of the direction of rotation is determined by the position of the leading edge of one pulse sequence relative to the second pulse sequence, which reduces the number of circuit elements used without reducing its noise immunity, since the operation of the circuit does not depend on the speed of rotation. DETAILED DESCRIPTION OF THE INVENTION A digital speed converter comprising a ring with tags evenly spaced around the circumference, two reading elements mutually displaced in the direction of rotation, and a reversible counter, the counting input of which is connected to the output of the first reading element, in order to simplify the device equipped with a shortening circuit of the counting pulses, a logical element AND-NOT and an O-trigger with a grounded D-input, while the first input of the element AND-NOT is connected via a shortening circuit of the counting pulses with Exit pickup element, a second input connected to the output of the second pickup element, and 5 9571084 output - to the S-INPUT D-flip-flop, score-1. USSR author's certificate which entrance is connected to the output Iff, cl. G 01 P 5/06, the first reading element, and you-1973. strokes - with control inputs of the reversible counter. . $ 2. USSR author's certificate Sources of information, No. 2b0980, class. G O S 9/06, 1962 taken into account in the examination (prototype).