SU432506A1 - DEVICE FOR PROCESSING OF INFORMATION - Google Patents

Description

one

The invention relates to the field of computer technology and is intended for the automated processing of information stored on magnetic media.

The known information processing devices comprise a playback unit, a valve unit, a threshold element unit, a matching circuit, an OR circuit, an information selection unit, a digital converter, and a processing line.

A disadvantage of the known devices is that they do not allow the selection of information according to its nature. This leads to an increase in the processing time of information and the results of processing small accuracy.

The purpose of the invention is to remedy these disadvantages.

This goal is achieved by introducing into the device a unit for determining the stationarity of processes by estimating an average square, whose inputs are connected respectively to the outputs of another integrating unit, a third key, a playback unit and a decoder, and its outputs are connected respectively to the second inputs of the first and second keys.

The scheme of the proposed device is shown in the drawing.

It contains the playback unit 1, quad 2, keys 3-6, delay element 7, counter 8, decoder 9, integrating blocks 10 and 11, and block 12 for determining the stationarity of the process according to estimates of the average square, which consists of Schmitt triggers 13 and 14, divider eg: pa resistors 15 and 16, circuits “OR 17, circuits“ Prohibit 18, 19 and 20, counter 21, decoder 22, switch 23, triggers 24 and 25; 26 and 27 - inputs of processing lines, respectively, stationary and non-stationary processes.

The device works as follows.

When playing a selected piece of information recorded on a closed magnetic carrier of playback unit 1, the ring-mark pulse is read with each turn of the closed magnetic carrier.

The measurement information is fed to the input of the quadrant 2, the output of which relieves a voltage proportional to the square of the signal, which is fed to the integrating unit 10, where this signal is averaged, and from the output of the integrating unit 10, the voltage proportional to the estimated average square of the signal over the following period is taken. ring pulses. This voltage is applied as a formation level to one of the Schmitt trigger inputs 13 and a voltage divider across resistors 15 and 16. The voltage divider is applied as a formation level to one of the Schmitt trigger inputs 14. From the square output 2, the voltage proportional to the square of the signal , arrives at the integrating block II, from the output of which the voltage is removed, and it is estimated that the average value of the signal for the period of the clock pulses is removed.

The clock pulses from the output of the playback unit 1 to the input of the key 5 open it, and pulses pass through it, the amplitude of which is proportional to the estimated mean value of the signal.

The delayed clock pulses open the key 6, and the output of the integrating unit AND is reset to zero. The delay time of the delay element 7 is chosen to be equal to the transit time of pulses proportional to the estimated average value of the signal through the key 5.

With the arrival of the next clock pulse, the process of calculating an estimate of the average value of the signal and transmitting this value through key 5 is repeated.

From the output of the key 5, the pulses arrive at the inputs of Schmitt triggers 13 and 14. The Schmitt trigger 13 generates a pulse if the amplitude of the pulse is proportional to the estimated average value of the signal for the clock period, greater than or equal to the voltage proportional to the estimates of the average square of the signal.

The Schmitt Trigger 14 generates a pulse at the output if the amplitude of the pulses, proportional to the estimated average value of the signal for the period of the clock pulse, is greater or equal to the voltage from the divider.

From the output of the Schmitt trigger 14, the pulses are sent to one of the inputs of the Ban 18 circuit, to the other input of which clock pulses are applied. At the output of this circuit, pulses are generated synchronously with pulses of the clock frequency only if from the output of the Schmitt trigger 14 to the input of the “Forbid 18” circuit the pulses do not arrive.

From the outputs of the Schmitt trigger 13 and the “Forbid 18” circuit, the pulses through the “OR 17” circuit are fed to the input of the “Prohibit 19” circuit and then pass through it until one of the outputs of the decryptor 9 connected to the other input of the “Prohibit 19” circuit. no voltage is developed to open it.

The voltage at this output of the descrambler 9 is generated when two ring pulses arrive at the counter 8. In this case, the output of the integrating unit 10 is set

the average value of the square of the signal for the period of the pulse ring. During the second revolution of the closed magnetic carrier, the formation levels for the Schmitt triggers 13 and 14 will be constant.

Counter 21 is reset by a ring pulse with each turn of the closed magnetic carrier and counts the number of pulses

proportional to the estimated mean value of the signal and not falling in the interval between the voltage, and the proportional estimate of the average square of the signal for the period of the ring pulse, and the voltage from the divider

on resistors 15 and 16. As soon as this number reaches a predetermined setpoint value, the voltage drop from the output of decider 22 via switch 23 sets the trigger 24 to the normal position. Connected

with the release of this trigger, the key 4 opens, and the measurement information from the playback unit 1 enters the processing line 27 of non-stationary processes. If the number of emulsions entering the input

After the arrival of the third ring pulse, the Ban 20 misses this pulse on the trigger 25, the voltage from the output of which opens the key 3, passes measuring information to the processing line 26 of stationary processes.

Subject invention

An information processing device comprising a playback unit, the first output of which is connected to the first inputs of the first and second keys and through a quad

the inputs of the integrating units, the output of one of which is connected to the third and fourth keys, the second output of the playback unit is connected to the third key and through the delay element to the fourth key, the third output of the playback unit is connected to a counter connected to the decoder, characterized in that In order to increase speed and increase the reliability of the device, it contains a block for determining the stationarity of processes according to estimates of the average square, the inputs of which are connected respectively to the outputs of another int a third block, a playback unit and a descrambler, and its outputs

Connected accordingly to the second inputs of the first and second keys.