SU790341A1 - Multitreshold logic element - Google Patents

Description

one

The invention relates to automation and computing, in particular to threshold logic elements.

Known multithreshold logic element containing a linear adder connected to a resistive divider connected to a multi-threshold discriminator 1.

A disadvantage of the known multi-threshold logic element is the high power consumption.

A multithreshold logic element is known, containing a linear adder consisting of input diodes and a rheistor matrix, connected through separating diodes to a resistive divider connected to the same inputs of NAND logic elements, forming a multithreshold discriminator, the second input of each of which is connected to the output of the next logical element AND-NOT fZJ

The disadvantage of this multi-threshold element is that the input signals in the form of positive potentials are locked in any combination of input diodes included in the linear adder. This ensures that the current is switched from the power source to the resistive divider circuit. When entering the inputs of a multithreshold logic element

5 of a large number of logical variables equal to one, the potential at the output of the linear adder increases. This leads to a decrease in the degree of saturation of the separation diodes, the input 0 is quiet in the linear adder, due to the decrease in the potential difference between the anode and cathode of the diode. This, in turn, leads to an increase in the error and decrease

5 linearization summation due to the change in current through the diodes. In addition, even in this case, when the input signals of a multithreshold logic element are zero,

20 power consumption by a linear adder due to the flow of currents cherz input diodes.

The purpose of the invention is to reduce power consumption, increase linearity and decrease the error of the linear adder.

To achieve this goal, a multithreshold logic element containing a resistive divider,

30 outputs of which are connected to one

the inputs of NAND logic gates are a multi-threshold discriminator, the second input of each of which is connected to the output of a subsequent logic element, contains transistors whose emitters are connected to the negative pole of the power source, the base is connected to the output terminals of the multi-threshold element, and the collectors are connected via resistors to the output resistive divider, the input of which is connected to the positive pole of the power source.

The drawing shows a circuit diagram of a multithreshold logic element.

For each input, the multithreshold logic element contains a key on transistor 1, in series with which resistor 2 is connected, determining the weight of this input. Transistors 1 of transistor switches are connected to resistor divider output resistors 2

3, the input of which will be connected to terminal

4 connected to the positive pole of the power supply. The emitters of the transistors are connected and connected to terminal 5, which is connected to the negative pole of the power supply. Multithreshold discriminator 6 consists of two-input logic elements

AND-NOT 7, forming multi-threshold discriminators. Terminal 8 is connected to the positive pole of the power source, terminals e are inputs, and terminal 10 is the output of a multi-threshold logic element. The power source is not shown in the drawing. The single-threshold discriminator on the NAND 7 element, one of the inputs of which is connected to terminal 8, has the lowest response threshold, and the single-sign discriminator on the IS-NE element 7, the output of which is the output of a multi-threshold logic element, has the highest response threshold. .

Multithreshold logical element works as follows.

In the absence of input signals, the transistors 1 are locked, the potentials of the connection points of the resistors 3 are equal to the voltage of the power source. At the output of the single-threshold discriminator with the smallest threshold, the level is logical zero. At output 10 of a multithreshold logic element, there is a logical unit level if k6l 1 quality with even threshold discriminators is even, and the logical zero level is in the opposite case (with an odd number of single threshold discriminators).

Let the number of single-threshold discriminators be odd. Then the input signals in the form of positive voltage potentials open

in any combination, the transistors 1. In this case, the current through the circuit of series-connected resistors 3 is defined as S LL uJc where x., respectively, the signal and weight of the i-th input of the multi-threshold logic element; n is the number of inputs.

If for thresholds of single-threshold discriminators of a multithreshold logic element the condition T T ... T is met, then at output 10 of a multithreshold logic element there is a logic zero level. If, then the potential at point 11 of the connection of resistors 3 is below the threshold of the discriminator on the AND-NE logic element 7 and a high voltage level is established at its output. This leads to the fact that the outputs of all single-threshold discriminators with large trigger thresholds are reversed and the level of the logical unit is set at the output 10 of the multi-threshold logic element.

 The emergence at the outputs 9 of a multithreshold logic element of a combination of source signals, which corresponds to T., leads to the appearance of a low voltage level at the output of a single threshold discriminator with a threshold Tj and a logic zero at the output 10.

If the combination of input variables corresponds to a value, then the potential of point 12 becomes lower than the threshold of operation of the corresponding discriminator at a logical one: the NAND element 7 and the output 10 of the multi-threshold element establish a high level of voltages corresponding to a logical unit.

These changes in the structure of a multithreshold logic element can improve linearity and reduce the error of the linear adder due to the fact that the degree of saturation of the transistor switches 1 in the proposed scheme of their inclusion is determined by the voltage value at the inputs 9 and is almost independent of the number of input signals equal to one . In addition, the power consumed by the linear adder is reduced, since the currents of the inputs, to which the zero values of the logic variables are supplied, are equal to zero.

Claims (2)

1. Author's certificate of the USSR 608266, cl. H 03 K 19/42, 1978. 2. Authors certificate of the USSR 538490. cl. H 03 K 19/12, 1977.