RU2789166C1 - And/and-not trigger logic element - Google Patents

Abstract

FIELD: digital circuit engineering, automation engineering, industrial electronics.

SUBSTANCE: invention relates to digital circuit engineering, automation engineering and industrial electronics and, in particular, can be used in computer technology units built on logic elements. The AND/AND-NOT trigger logic element additionally contains two additional p-n-p-transistors, one additional n-p-n-two-emitter transistor and six additional resistors. The first additional resistor, the first additional p-n-p transistor and the second additional resistor are connected in series with each other. The common collector terminal of the first additional transistor and the second additional resistor is connected to the base of the third transistor. The base of the first additional transistor is connected to the common terminal of the third resistor and the collectors of the second and third transistors. A second additional p-n-p transistor and a third additional resistor are connected in series. The emitter of the second additional transistor is connected to the common terminal of the first additional resistor and the emitter of the first additional transistor. The base of the second additional transistor is connected to the common terminal of the first resistor and the collectors of the first and fourth transistors. The common terminal of the collector of the second additional transistor and the third additional resistor is connected to the base of the fourth transistor. The common output of the emitters of the fifth and sixth transistors is grounded. The base of the fifth transistor is connected to an additional fourth resistor. The base of the sixth transistor is connected to an additional fifth resistor. The free terminal of the additional fifth resistor is connected to the collector of the fifth transistor, the free terminals of the fourth and additional second resistors and their common output forms an inverting output of the logic element relative to the ground. The collector of the sixth transistor is connected to the free terminals of the fifth and additional third and fourth resistors and their common output forms a non-inverting output of the logic element relative to the ground. The outputs of the emitters of the additional n-p-n-two-emitter transistor form two inputs of the logic element relative to the ground. A sixth additional resistor is connected to the base of an additional n-p-n-two-emitter transistor. The free terminal of the sixth additional resistor is connected to the free terminal of the first additional resistor and the common terminal of the first and third resistors and the output of the supply voltage source. The collector of an additional n-p-n-two-emitter transistor is connected to the base of the first transistor.

EFFECT: increasing the output capacity of the trigger logic element AND/AND-NOT.

1 cl, 2 dwg

Description

The invention relates to digital circuitry, automation and industrial electronics. In particular, it can be used in computer technology blocks built on logical elements.

Known two-input logic element AND-NOT [1 Yampolsky B.C., Fundamentals of automation and computer technology. - M.: Enlightenment, 1991, p. 74, fig. 3.5], containing four transistors, four resistors, one diode and a DC power supply.

Its disadvantage is that it has a low load capacity. The electric current of only one of the available transistors forms the electric current of the external load. If it were possible to increase the number of transistors that form the load current, this would lead to an increase in the maximum electric current of the external load of the logic element and, as a result, to an increase in its load capacity.

The closest in technical essence and the achieved result is the logical element OR/OR-NOT chosen as a prototype [Manaev E.I. Fundamentals of radio electronics. - M .: Radio and communication, 1985, p. 342, figure 14.23], containing six transistors, five resistors and two constant voltage sources.

Its disadvantage lies in the low load capacity. The electric current of only one of the six transistors generates an external load current. If it were possible to increase the number of transistors that form the electric current of the external load, then this would lead to an increase in the maximum strength of the electric load current of the logic element and, as a result, to an increase in the load capacity. The above logical element refers to ESL elements (ESL - emitter-coupled logic).

The problem to be solved by the invention is to increase the load capacity of the trigger logic element AND/AND-NOT.

This is achieved by the fact that in the trigger logic element AND / AND-NOT, containing a supply DC voltage source, the negative output of which is connected to a common bus and grounded, the first resistor, the first n-p-n transistor and the second resistor are connected in series, free the output of the first resistor is connected to the output (positive terminal) of the supply source, the free terminal of the second resistor is grounded, the third resistor and the second NPN transistor are connected in series, the free terminal of the third resistor is connected to the common terminal of the first resistor and the output of the power source, the emitter of the second transistor connected to the common output of the emitter of the first transistor and the second resistor, a reference voltage source, the negative terminal of which is grounded, and the positive terminal is connected to the base of the second transistor, the third n-p-n transistor connected in series and the fourth resistor connected to the emitter of the third transistor, connected in series fourth n-p-n transistor and fifth resistor stor connected to the emitter of the fourth transistor, also the fifth and sixth are also n-p-n transistors, the emitters of which are interconnected, two additional p-n-p transistors, one additional n-p-n two-emitter transistor and six additional resistors are introduced, the first additional resistor, the first additional p-n-p transistor and the second additional resistor are connected in series with each other, the free terminal of the first additional resistor is connected to the common terminal of the first, third resistors and the output of the supply voltage, the common terminal of the collector of the first additional transistor and the second additional resistor connected to the base of the third transistor, the base of the first additional transistor is connected to the common terminal of the third resistor and the collector of the second transistor, as well as to the collector of the third transistor, the free terminal of the second additional resistor is connected to the free terminal of the fourth resistor and their common terminal forms a relative about the "ground" inverting output of the logic element, the second additional p-n-p transistor and the third additional resistor are connected in series, the emitter of the second additional transistor is connected to the common terminal of the first additional resistor and the emitter of the first additional transistor, the base of the second additional transistor is connected to the common terminal of the first resistor and collector of the first transistor, as well as with the collector of the fourth transistor, the common terminal of the collector of the second additional transistor and the third additional resistor is connected to the base of the fourth transistor, the free terminal of the third additional resistor is connected to the free terminal of the fifth resistor and their common terminal forms a non-inverting relative to the "ground" the output of the logic element, the common output of the emitters of the fifth and sixth transistors is grounded, the base of the fifth transistor is connected to an additional fourth resistor, the free output of which is connected to the common output of the fifth, additional of the third resistor and the non-inverting output of the logic element, the collector of the fifth transistor is connected to the common terminal of the fourth, additional second resistors and the inverting output of the logic element, the base of the sixth transistor is connected to the additional fifth resistor, the free output of which is connected to the common terminal of the fourth, additional second resistors, the collector of the fifth transistor and the inverting output of the logic element, the collector of the sixth transistor is connected to the common terminal of the fifth, additional third, additional fourth resistors and the non-inverting output of the logic element, the outputs of the emitters of the additional n-p-n two-emitter transistor form two inputs of the logic element relative to the "ground", to the base of the last transistor is connected to the sixth additional resistor, the free output of which is connected to the common output of the first, third, additional first resistors and the output of the supply source, the collector of this the last transistor is connected to the base of the first transistor.

The essence of the invention is illustrated by the trigger logic element AND/AND-NOT (Fig. 1) and the truth table (Fig. 2).

In the trigger logic element AND / AND-NOT, the common bus (negative output) of the source 1 of the DC supply voltage is grounded. One of the terminals of the resistor 2 is connected to the output (positive terminal) of this source, its other terminal is connected to the base of the two-emitter n-p-n transistor 3. The two outputs of the emitters of this transistor form, relative to the "ground", two inputs x ₁ and x ₂ of the logic element. Resistor 4, n-p-n transistor 5 and resistor 6 are connected in series with each other. The free terminal of resistor 4 is connected to the common terminal of resistor 2 and the output of source 1. The base of transistor 5 is connected to the collector of transistor 3, and the free terminal of resistor 6 is grounded.

Resistor 7 and n-p-n transistor 8 are connected in series. The free terminal of resistor 7 is connected to the common terminal of resistors 2, 4 and the output of power source 1. The emitter of transistor 8 is connected to the common terminal of resistor 6 and the emitter of transistor 5. It is connected to the base of transistor 8 the output (positive terminal) of the reference voltage source 9, the negative terminal of this source is grounded.

.An n-p-n transistor 10 and a resistor 11 are connected in series with each other. The collector of the transistor 10 is connected to the common terminal of the resistor 7 and the collector of the transistor 8. The free terminal of the resistor 11 forms an inverting output of the logic element relative to the "ground". Resistor 12, p-n-p transistor 13 and resistor 14 are connected in series. The free terminal of resistor 12 is connected to the common terminal of resistors 2, 4, 7 and source output 1. The base of transistor 13 is connected to the common terminal of resistor 7 and collectors of transistors 8 and 10 The collector of transistor 13 is connected to both the base of transistor 10 and to one of the terminals of resistor 14. The other terminal of resistor 14 is connected to the common terminal of resistor 11 and the inverting output of the logic element

.

The p-n-p transistor 15 and resistor 16 are connected in series. The emitter of transistor 15 is connected to the common terminal of resistor 12 and the emitter of transistor 13. The base of transistor 15 is connected to the common terminal of resistor 4 and the collector of transistor 5. The free terminal of resistor 16 forms relative to the "ground" non-inverting output of the logic element. An n-p-n transistor 17 and resistor 18 are connected in series. The collector of transistor 17 is connected to the common terminal of resistor 4, the collector of transistor 5 and the base of transistor 15. The base of transistor 17 is connected to the common terminal of the emitter of transistor 15 and resistor 16. The free terminal of resistor 18 is connected with a common output of the resistor 16 and the non-inverting output y of the logic element.

логического элемента. К базе транзистора 20 подсоединен первый вывод резистора 22, второй его вывод подключен к общему выводу резисторов 11, 14, коллектора транзистора 19 и инвертирующего выхода у логического элемента. Коллектор транзистора 20 соединен с общим выводом резисторов 16,18, 21 и неинвертирующего выхода y логического элемента.The emitter terminal of the npn transistor 19 is connected to the emitter terminal of the npn transistor 20 and their common terminal is grounded. One of the outputs of the resistor 21 is connected to the base of the transistor 19, the other output of this resistor is connected to the common output of the resistors 16, 18 and the non-inverting output of the logic element. The collector of the transistor 19 is connected to the common terminal of the resistors 11, 14 and the inverting output

logical element. The first output of the resistor 22 is connected to the base of the transistor 20, its second output is connected to the common output of the resistors 11, 14, the collector of the transistor 19 and the inverting output of the logic element. The collector of the transistor 20 is connected to the common terminal of the resistors 16,18, 21 and the non-inverting output y of the logic element.

In FIG. 1 part of the circuit on transistors 5, 8 is a current switch, part of the circuit on transistors 10, 13 is the first trigger on transistors of the opposite type of conductivity and part of the circuit on transistors 15, 17 is the second trigger on transistors of the opposite type of conductivity. Resistor 12 is included in both the first and second flip-flops and can be called a common emitter resistor. Resistor 4 is also included in the current switch on transistors 5, 8, and in the second trigger on transistors of the opposite type of conductivity 15.17. Resistor 7 enters both the current switch and the first trigger on transistors of the opposite type of conductivity 10, 13.

Trigger logic AND/AND-NOT works as follows. Digital electronics uses low and high level electrical input and output signals. Low level - the level of logical zero corresponds to voltage values in the region of zero or closer to zero, high level - the level of logical one corresponds to voltage values \u200b\u200bin the region of units of volts (often in the region of four volts).

The trigger on transistors 10, 13 of the opposite type of conductivity has two equilibrium states. In the first (conditionally) state, both transistors are closed and do not conduct electricity. Then, including resistors 7 and 14, zero voltage values. They are applied to the bases of transistors 10, 13 less than the threshold voltages of these transistors in absolute value and, as a result, keep these transistors in the closed state. In the second (conditionally) state, transistors 10 and 13 are open, their electric currents create voltages, including those on resistors 7 and 14, in absolute value and in values greater than the threshold voltages of the transistors and keep transistors 10, 13 in the open state. A flip-flop on transistors of the opposite type of conductivity, like other common flip-flops, passes from the first state to the second and vice versa when the control input voltages exceed the values of the voltages of the corresponding trigger thresholds. The second trigger works exactly the same way on transistors 15, 17 of the opposite type of conductivity.

условное отображение сигналов на неинвертирующем и инвертирующем выходах логического элемента и N - номер строки по порядку. В соответствии со строками 1 -3 таблицы истинности на один или оба входа x₁ и x₂ логического элемента поступает напряжение уровня логического нуля. Тогда один или оба базо-эмиттерных р-n перехода транзистора 3 открыты и на них весьма малое значение напряжения, как на диодах в проводящим электрический ток состоянии. Базо-коллекторный р-n переход транзистора 3 тоже открыт, в итоге на базе транзистора 5 низкий уровень напряжения. За счет соответствующего значения напряжения источника 9 опорного напряжения обеспечивается требующееся значение силы электрического тока через транзистор 8. Этот ток создает на резисторе 6 напряжение, которое плюсом приложено к эмиттеру транзистора 5. Значением напряжения на резисторе 6 обеспечивается значение разности напряжений между базой и эмиттером транзистора 5 в районе порогового напряжения или близкое к нему значение. Тогда имеется малое значение силы коллекторного тока этого транзистора и малое напряжение на резисторе 4. Это малое напряжение не может обеспечить второе состояние второго триггера и включено между базой р-n-р транзистора 15 и через резистор 12 его эмиттером плюсом к эмиттеру и минусом к базе. Значением сопротивления резистора 7 обеспечивается открытое состояние n-р-n транзистора 13 и второе состояние первого триггера на транзисторах противоположного типа проводимости. Напряжение на резисторе 7 включено между базой и эмиттером р-n-р транзистора 13 минусом к базе и плюсом через резистор 12 к эмиттеру. Электрические токи транзисторов 10 и 13 триггера на транзисторах противоположного типа проводимости во втором состоянии создают на внешней нагрузке и на инвертирующем выходе

логического элемента напряжение уровня логической единицы. Электрический ток эмиттера транзистора 13 создает на резисторе 12 напряжение, которое минусом приложено к эмиттеру транзистора 15 и дополнительно способствует первому состоянию второго триггера на транзисторах противоположного типа проводимости 15, 17. Сила токов этих транзисторов равна нулю или почти равна нулю и создает на внешней нагрузке и на неинвертирующем выходе у логического элемента напряжение уровня логического нуля (фиг. 2).The operation of the AND/AND-NOT logical element is reflected in the truth table (Fig. 2), where x ₁ and x ₂ are a conditional display of the input signals, y and

conditional display of signals on the non-inverting and inverting outputs of the logic element and N is the line number in order. In accordance with lines 1-3 of the truth table, one or both inputs x ₁ and x ₂ of the logic element receives a logic zero level voltage. Then one or both base-emitter p-n junctions of transistor 3 are open and they have a very low voltage value, as on diodes in a conductive state. The base-collector p-n junction of transistor 3 is also open, as a result, the base of transistor 5 has a low voltage level. Due to the corresponding voltage value of the reference voltage source 9, the required value of the electric current through the transistor 8 is provided. This current creates a voltage on the resistor 6, which is positively applied to the emitter of the transistor 5. The voltage value across the resistor 6 provides the value of the voltage difference between the base and the emitter of the transistor 5 near the threshold voltage or a value close to it. Then there is a small value of the collector current of this transistor and a low voltage across resistor 4. This low voltage cannot provide the second state of the second trigger and is connected between the base of the p-n-p transistor 15 and through resistor 12 by its emitter plus to the emitter and minus to the base . The resistance value of the resistor 7 provides the open state of the n-p-n transistor 13 and the second state of the first trigger on transistors of the opposite type of conductivity. The voltage across the resistor 7 is connected between the base and the emitter of the p-n-p transistor 13 minus to the base and plus through the resistor 12 to the emitter. The electric currents of the transistors 10 and 13 of the trigger on transistors of the opposite type of conductivity in the second state are created at the external load and at the inverting output

logic element voltage level logic one. The electric current of the emitter of the transistor 13 creates a voltage on the resistor 12, which is negatively applied to the emitter of the transistor 15 and additionally contributes to the first state of the second trigger on transistors of the opposite type of conductivity 15, 17. The current strength of these transistors is equal to zero or almost equal to zero and creates on the external load and at the non-inverting output of the logic element, the voltage is at the logic zero level (Fig. 2).

логического элемента напряжение уровня логической единицы приложено к резистору 22 и в итоге поддерживает транзистор 20 в открытом состоянии. Тогда через этот транзистор разряжается ранее заряженная эквивалентная паразитная емкость (сумма выходной емкости логического элемента и входной емкости нагрузки). Малое сопротивление открытого транзистора 20 уменьшает постоянную времени разряда эквивалентной паразитной емкости, тем самым уменьшает время ее разряда и в результате заметно не ухудшается быстродействие схемы из-за имеющихся паразитных емкостей. С неинвертирующего выхода у логического элемента напряжение уровня логического нуля приложено к резистору 21, поэтому состояние транзистора 19 в худшем случае в районе его порогового напряжения. Сила тока этого транзистора весьма мала и электрический ток транзисторов 10, 13 почти полностью замыкается на внешнюю нагрузку, подключенную к инвертирующему выходу

From reverse output

gate voltage is applied to the resistor 22 and ultimately keeps the transistor 20 in the open state. Then, through this transistor, the previously charged equivalent parasitic capacitance (the sum of the output capacitance of the logic element and the input capacitance of the load) is discharged. The low resistance of the open transistor 20 reduces the discharge time constant of the equivalent parasitic capacitance, thereby reducing its discharge time and, as a result, the circuit speed does not noticeably deteriorate due to the presence of parasitic capacitances. From the non-inverting output of the logic element, the logic zero level voltage is applied to the resistor 21, so the state of the transistor 19 is, in the worst case, in the region of its threshold voltage. The current strength of this transistor is very small and the electric current of transistors 10, 13 is almost completely closed to an external load connected to the inverting output

Повышение силы электрического тока транзистора 5 приводит к уменьшению значения напряжения на базо-эмиттерном переходе транзистора 8, уменьшению силы коллекторного тока транзистора 8 и весьма малому значению напряжения на резисторе 7. Для краткости можно сказать, что напряжение на резисторе 7 настолько мало, что не оказывает влияния на работу схемы и не может перевести первый триггер на транзисторах противоположного типа проводимости во второе состояние, хотя минусом оно приложено к базе р-n-р транзистора 13. Эмиттерный ток транзистора 15 создает на резисторе 12 напряжение, которое плюсом через резистор 7 приложено к базе р-n-р транзистора 13 и минусом к его эмиттеру и тоже обеспечивает первое состояние первого триггера на транзисторах противоположного типа проводимости. Почти нулевые значения силы электрических токов транзисторов 10, 13 первого триггера на транзисторах противоположного типа проводимости в первом состоянии создают на внешней нагрузке и на инвертирующем выходе

логического элемента напряжение уровня логического нуля (фиг 2.).In accordance with the fourth line of the truth table (Fig. 2) on both inputs x ₁ and x ₂ of the logic element receives the voltage level of the logical unit. Both base-emitter junctions of transistor 3 and its base-collector junction, as before, are open, then there is a high voltage level at the base of transistor 5. This leads to an increase in the electric current of the transistor 5 and an increase in the voltage across the resistor 4, which is applied by the minus to the base of the p-n-p transistor 15 and by the plus through the resistor 12 to its emitter. This voltage maintains the transistor 15 in the open state, and the second flip-flop in the second state. The electric currents of the transistors 15, 17 of the second trigger on transistors of the opposite type of conductivity in the second state create a logic-one level voltage at the external load and the non-inverting output y. Up to this voltage, the equivalent parasitic capacitance at the non-inverting output will be charged.

An increase in the current strength of transistor 5 leads to a decrease in the voltage value at the base-emitter junction of transistor 8, a decrease in the collector current strength of transistor 8 and a very small voltage across resistor 7. For brevity, we can say that the voltage across resistor 7 is so small that it does not influence on the operation of the circuit and cannot transfer the first trigger on transistors of the opposite type of conductivity to the second state, although it is applied to the base of the p-n-p transistor 13 with a minus. The emitter current of the transistor 15 creates a voltage on the resistor 12, which is applied to the base p-n-p transistor 13 and a minus to its emitter and also provides the first state of the first trigger on transistors of the opposite type of conductivity. Almost zero values of the strength of electric currents of transistors 10, 13 of the first trigger on transistors of the opposite type of conductivity in the first state are created at the external load and at the inverting output

logic element voltage level of logic zero (Fig. 2.).

логического элемента напряжение уровня логического нуля приложено к резистору 22, поэтому состояние транзистора 20 в худшем случае в районе его порогового напряжения. Сила тока этого транзистора весьма мала и электрический ток транзисторов 15, 17 почти полностью замыкается на внешнюю нагрузку, подключенную к неинвертирующему выходу у логического элемента. При переходе одного или двух входных сигналов от уровня логического нуля к двум входным сигналам уровня логической единицы сила эмиттерного тока транзистора 5 возрастает, а сила эмиттерного тока транзистора 8 убывает. При переходе двух входных сигналов от уровня логической единицы к одному или двум входным сигналам уровня логического нуля сила эмиттерного тока транзистора 5 убывает, а сила эмиттерного тока транзистора 8 возрастает.From the non-inverting output of y, a logic-one level voltage is applied to resistor 21 and, as a result, keeps transistor 19 in the open state. Through this transistor, the previously charged equivalent parasitic capacitance is discharged. The low resistance of the open transistor 19 reduces the discharge time constant of the equivalent parasitic capacitance, thereby reducing its discharge time and, as a result, the speed of the circuit does not noticeably deteriorate due to the presence of parasitic capacitances. From inverting output

logic element voltage logic zero applied to the resistor 22, so the state of the transistor 20 in the worst case in the region of its threshold voltage. The current strength of this transistor is very small and the electric current of the transistors 15, 17 is almost completely closed to an external load connected to the non-inverting output of the logic element. When one or two input signals go from a logic zero level to two input signals of a logic one level, the emitter current strength of the transistor 5 increases, and the emitter current strength of the transistor 8 decreases. When the two input signals go from the logic one level to one or two input signals of the logic zero level, the emitter current strength of the transistor 5 decreases, and the emitter current strength of the transistor 8 increases.

The given prototype and trigger logic element AND/AND-NOT refer to ESL elements (ESL - emitter-coupled logic). It is known that ESL elements have increased performance [for example, Goldenberg L.M. impulse devices. - M .: Radio and communication, 1981, p. 57, section "Dynamic characteristics", paragraphs 1, 2, ... 6].

Thus, in the trigger logic element AND/AND-NOT, the strength of the electric currents of external loads is equal to the sum of the strength of the currents of the two transistors 10, 13 and 15, 17, which increases the load capacity of this logic element. In the prototype, the load current forms only one of the transistors.

Claims (1)

Trigger logical element AND/AND-NOT, containing a source of DC supply voltage, the negative output of which is connected to a common bus and grounded, the first resistor, the first n-p-n-transistor and the second resistor are connected in series with each other, the free output of the first resistor is connected to output (positive terminal) of the supply source, the free terminal of the second resistor is grounded, the third resistor and the second n-p-n-transistor are connected in series, the free terminal of the third resistor is connected to the common terminal of the first resistor and the output of the power source, the emitter of the second transistor is connected to the common terminal the emitter of the first transistor and the second resistor, the reference voltage source, the negative terminal of which is grounded, and the positive terminal is connected to the base of the second transistor, the third n-p-n-transistor connected in series and the fourth resistor connected to the emitter of the third transistor, the fourth n-p connected in series -n-transistor and fifth resistor connected to the emitter ru of the fourth transistor, also the fifth and sixth are also n-p-n-transistors, the emitters of which are interconnected, characterized in that two additional p-n-p-transistors are introduced into it, one additional n-p-n-two-emitter transistor and six additional resistors, the first additional resistor, the first additional p-n-p transistor and the second additional resistor are connected in series with each other, the free terminal of the first additional resistor is connected to the common terminal of the first, third resistors and the output of the supply voltage, the common terminal of the collector of the first of the additional transistor and the second additional resistor is connected to the base of the third transistor, the base of the first additional transistor is connected to the common terminal of the third resistor and the collector of the second transistor, as well as to the collector of the third transistor, the free terminal of the second additional resistor is connected to the free terminal of the fourth resistor and their common terminal forms relatively about the "ground" inverting output of the logic element, the second additional p-n-p transistor and the third additional resistor are connected in series, the emitter of the second additional transistor is connected to the common terminal of the first additional resistor and the emitter of the first additional transistor, the base of the second additional transistor is connected to the common terminal of the first resistor and the collector of the first transistor, as well as with the collector of the fourth transistor, the common terminal of the collector of the second additional transistor and the third additional resistor is connected to the base of the fourth transistor, the free terminal of the third additional resistor is connected to the free terminal of the fifth resistor and their common terminal forms relative to the "ground" non-inverting output of the logic element, the common output of the emitters of the fifth and sixth transistors is grounded, the base of the fifth transistor is connected to an additional fourth resistor, the free output of which is connected to the common output of the fifth, additional of the third resistor and the non-inverting output of the logic element, the collector of the fifth transistor is connected to the common terminal of the fourth, additional second resistors and the inverting output of the logic element, the base of the sixth transistor is connected to the additional fifth resistor, the free output of which is connected to the common terminal of the fourth, additional second resistors, the collector the fifth transistor and the inverting output of the logic element, the collector of the sixth transistor is connected to the common output of the fifth, additional third, additional fourth resistors and the non-inverting output of the logic element, the outputs of the emitters of the additional n-p-n-two-emitter transistor form two inputs of the logic element relative to the "ground", the sixth additional resistor is connected to the base of the last transistor, the free output of which is connected to the common output of the first, third, additional first resistors and the output of the supply source, the collector of this the last transistor is connected to the base of the first transistor.

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